DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed 4/19/2023 contains an item that fails to comply with 37 CFR 1.98(a)(1), which requires the following: (1) a list of all patents, publications, applications, or other information submitted for consideration by the Office; (2) U.S. patents and U.S. patent application publications listed in a section separately from citations of other documents; (3) the application number of the application in which the information disclosure statement is being submitted on each page of the list; (4) a column that provides a blank space next to each document to be considered, for the examiner’s initials; and (5) a heading that clearly indicates that the list is an information disclosure statement. In this case, Cite No. 1 under U.S. PATENT APPLICATION PUBLICATIONS is improper because the name of the Patentee or Applicant of the cited document (Lutich) does not match with the application publication number (20180040672), and has therefore not been considered. The remaining citations are proper and have been considered.
Claim Objections
Claim 6 objected to because of the following informalities:
As per Claim 6:
Line 3, the word “Partitioning” should not be capitalized.
Line 8, the word “bboxof” should be --bbox of-- for proper grammar.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-9 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "each group" in line 8. There is insufficient antecedent basis for this limitation in the claim.
Claim 4 recites the limitation "the graphic in the new group" in line 7. There is insufficient antecedent basis for this limitation in the claim, as the claim previously recites plural “ungrouped graphics” in the new group, and therefore it is not clear as to which of these is being referred to by the claim limitation.
Claims 2-3 and 5-9 are rejected based on their dependency to Claim 1 for the reasons stated above.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, and 4 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Abt et al., hereinafter Abt, US Patent No. 6,907,583.
Regarding Claim 1, Abt teaches a method for reconstructing physical connection relationships of general EDA model layouts comprising:
separately establishing interconnection relationships between stack layers in an EDA model (Abt Col. 4, Lines 32-62 and Col. 6, Lines 51-67, wherein images of each layer of an IC layout are generated and used to establish connectivity between circuit elements across layers), connection relationships of graphics on each stack layer (Abt Col. 6, Lines 51-67, wherein connectivity between circuit elements is established through signal tracing of the images or graphics of each layer, including within each layer), and connection relationships of graphics on interconnected stack layers (Abt Col. 6, Lines 51-67, wherein connectivity between circuit elements is established through signal tracing of the images or graphics across layers); summarizing the connection relationships established, and then establishing the connection relationships of all graphics in the EDA model (Abt Col. 6, Lines 51-67, wherein a signal list of all lines in the circuit is created, which is a summary of connection relationships established, and are used to establish the connection relationships in the model through naming and coloring); and separately establishing physical connection relationships of interconnected graphics in each group to obtain physical connection relationships of an EDA model layout (Abt Col. 6, Lines 51-67, wherein the physical connection relationship of lines belonging to the same signal are established for each signal in the signal list).
Regarding Claim 2, Abt further teaches steps of:
S100-establishing the interconnection relationships between the stack layers according to a stackup file of the EDA model (Abt Col. 4, Lines 50-62, wherein interconnection relationships are formed according to a vector representation file of the layers);
S200-establishing the connection relationships of graphics on each of the stack layers (Abt Col. 5, Lines 57-67 and Col. 6, Lines 1-35, wherein alignment is performed on the images of the layers to establish connection relationships);
S300-selecting interconnected graphics on adjacent stack layers to establish the connection relationships (Abt Col. 5, Lines 57-67 and Col. 6, Lines 1-35, wherein performing alignment includes a user selecting images of the layers to perform the alignment);
S400-establishing the connection relationships of all graphics of the EDA model layout according to the connection relationships obtained in steps S200 and S300 (Abt Col. 5, Lines 57-67 and Col. 6, Lines 1-35, wherein the alignment establishes connection relationships);
S500-grouping graphics having the connection relationships and establishing physical connection relationships of groups (Abt Col. 6, Lines 51-67, wherein the signal lines having a connection relationship are grouped under the same name in the signal list); and
S600-summarizing the physical connection relationships of all the groups to obtain physical connection relationships of the EDA model layout (Abt Col. 6, Lines 51-67, wherein the signal list is a summary of the physical connection relationships).
Regarding Claim 4, Abt further teaches wherein grouping graphics having connection relationships in the S500, comprises following steps of:
S510-establishing a new group (Abt Col. 6, Lines 51-67, wherein naming signals is establishing new groups);
S520-selecting any of ungrouped graphics and adding the same to the new group established in S510 (Abt Col. 6, Lines 51-67, wherein line tracing discovers lines that are connected to each other and marks them as belonging to the same signal line);
S530-finding all graphics connected to the graphic in the new group formed in step S520 and adding the same to the new group (Abt Col. 6, Lines 51-67, wherein line tracing discovers all signal lines in the image that are connected together);
S540-judging whether there is a graphic that needs to be added, if none, finishing establishing the new group and executing S550; and if any, continuing to execute S530 (Abt Col. 6, Lines 51-67, wherein line tracing traverses the images and discovers all signal lines that are connected to each other); and
S550-judging whether there is a graphic that has not been included in the new group, if none, finishing grouping; and if any, going back to execute S510 (Abt Col. 6, Lines 51-67, wherein line tracing discovers all signal lines that are connected together, including additional lines previously not grouped as part of the line tracing).
Allowable Subject Matter
Claims 3 and 5-9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and if the 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph rejection set forth above are overcome.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding Claim 3, the prior art of record does not teach or suggest the following claim limitations:
wherein the connection relationships of all graphics in steps S200 and S300 are established specifically through following steps of:
step (1)-preprocessing all graphics and calculating bounding boxes of all graphics, referred to as bbox;
step (2)-putting all graphics together to generate a graphic set and calculating a bbox of the graphic set;
step (3)-partitioning the bbox of the graphic set into two subsets along a central x-axis or y-axis of the bbox of the graphic set in a partitioning manner that a sum of amount of graphics in the two subsets after being partitioned reaches a minimum value;
step (4)-separately judging whether to continue to partition the two subsets partitioned is possible, if yes, skipping to step (2) to continue partitioning; and if no, executing step (5);
step (5)-judging whether there are interconnected graphics in different subsets, if yes, recording relationships of intersected subsets, and obtaining connection relationships of the subsets after judging and recording relationships of all the intersected subsets;
step (6)-merging subsets having the connection relationships and generating the connection relationships of a parent set;
step (7)-judging whether the parent set is connecting to other sets or subsets, if yes, continuing to merge until generating a final parent set that connects to no set or subset; and
step (8)-finishing merging all subsets when the final parent set overlaps the graphic set generated by putting all original graphics together, finishing establishing the connection relationships.
Claims 5-9 would be allowable based on their dependency to Claim 3.
Conclusion
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/ERIC D LEE/Primary Examiner, Art Unit 2851
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