Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the claim listing filed on February 6th, 2026. Claims 19-33 are currently pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 19-33 are rejected 35 U.S.C. 103 as being unpatentable over FRYMAN et al. (USPGPUB No. 2019/0303159 A1, hereinafter referred to as Fryman) in view of Asaad et al. (USPGPUB No. 2011/0219208 A1, hereinafter referred to as Asaad) and further in view of Yamazaki et al. (USPGPUB No. 2018/0032911 A1, hereinafter referred to as Yamazaki) and further in view of Catanzaro et al. (USPGPUB No. 2017/0148433 A1, hereinafter referred to as Catanzaro).
Referring to claim 19, Fryman discloses an apparatus comprising {“core 2190”, see Fig. 21b [0321]}:
detect {“execution engine unit 2150” to detect/recognize/identifies (see Fig. 21b, [0316]) via “memory unit 2170” (see Fig. 21b [0319])} a first chunk {“directly cause a direct memory access (DMA) to send or receive blocks of data”, see Fig. 21b [0141]} and a second chunk of a message {“communication with short messages of up to 4-8 [chunk] data values”, see Figs. 10 and 21b [0148, 2nd sentence]; “different ones of which store one or more different data types [chunks]”, see Fig. 21b [0318]} in a first multi-buffer node {“execution may be implemented (e.g., using a [multi-buffer] reorder buffer(s)”, see Fig. 21b [0318]; “The ring network ensures coherency for shared data” (see Fig. 22a-b [0326]) also referred as “ring based interconnect unit 2312” (see Fig. 23, [0331])};
Fryman does not appear to explicitly disclose send, from a receive buffer, a first chunk of a message; However, Asaad discloses send, from a receive buffer {“multiple rMEs can receive and process packets belonging to the same message in parallel”, see Fig. 7 [1351]}, a first chunk of a message {“interface master, the rME writes descriptors from the packet [message] payload to the memory system location in the imFIFO pointed to”, see Fig. 7 [1354]};, and reduce a plurality of chunks of the message {“daisy chain connection connecting the central storage unit and the plurality of processing cores and forming a daisy chain ring layout”, see Fig. [1230]}.
Fryman and Asaad are analogous art because they are from the same problem-solving area, method and systems for handling data over MPI interface.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Fryman and Asaad before him or her, to modify Fryman’s “core 2190” (see Fig. 21b [0321]) incorporating Asaad’s “multiple rMEs” (see Fig. 7, [1351])).
The suggestion/motivation for doing so would have been to provide a full virtual node mode, each of the processing cores will perform its own MPI (message passing interface) process independently in turn uses a sixteenth of the memory (L2 and SDRAM) of the node, while coherence among the 64 processes within the node and across the nodes is maintained by MPI ((Asaad [0025]) which means the torus' DMA feature, internode communications can overlap with computations running concurrently on the nodes (Asaad [0026]) that improves reliability and redundancy (Asaad [0046], last sentence).
Therefore, it would have been obvious to combine Asaad with Fryman to obtain the invention as specified in the instant claim(s).
Neither Fryman or Asaad appear to explicitly disclose an apparatus comprising: a first multi-buffer node of a ring of nodes, the first multi-buffer node including processing circuitry coupled to a memory. However, Yamazaki discloses an apparatus comprising {an appropriate apparatus to perform “aggregation process, the inter-node communication process” ([0137], see Figs. 19 and 20): a first multi-buffer node {“ one set of buffers to store the weights (w).”, see Figs. 19 and 20 [0140]} of a ring of nodes {forming a ring of nodes during “image recognition and a determination of correct solution are iteratively executed” that includes “forward propagation processes at the respective neuron layers on a batch-by-batch basis by using the weight parameters (w) possessed by the individual neuron layers, and next executing the backward propagation processes sequentially at the individual neuron layers” (Emphasis added by Examiner, see Figs. 2, 3, and 4, all cited from [0051]}, the first multi-buffer node including processing circuitry coupled {“[processing circuitry] computing nodes 10 of the change of the processing sequence by the MPI ALLReduce algorithm”, see Fig. 18, [0134], last sentence} to a memory {“ the memory transfer (to the GPU 13 from the CPU 11” which are subcomponents to processing circuitry “computing nodes 10” (see Fig. 18 [0131], 2nd sentence)}.
Fryman/Asaad and Yamazaki are analogous art because they are from the same problem-solving area, method and systems for handling data over MPI interface.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Fryman/Asaad and Yamazaki before him or her, to modify Fryman/Asaad’s system incorporating Yamazaki’s “configuration of a parallel information processing apparatus” (see Fig. 3, [0043], 1st sentence).
The suggestion/motivation for doing so would have been to implement an intra-node parallel architecture and an inter-node parallel architecture that facilitates utilization of the computing component instanced by the GPU is effective in the learning process, such as fast computing of operations which are in a heavy usage of the learning processes instanced by product-sum operations or a cluster environment (Yamazaki [0004])).
Therefore, it would have been obvious to combine Yamazaki with Fryman/Asaad to obtain the invention as specified in the instant claim(s).
Neither one of the group consisting of Fryman, Asaad, and Yamazaki appears to explicitly send, from a receive buffer at a current index of a send buffer to a next node in the ring of nodes, detect a first chunk and a second chunk of a message;
receive, in parallel with sending the first chunk, from a previous node in the ring of nodes, a second chunk of the message and store the second chunk at a current index of the receive buffer;
reduce, in parallel with sending the first chunk and receiving the second chunk, a third chunk in the send buffer at a previous index of the receive buffer and a fourth chunk in the receive buffer at the previous index of the receive buffer and store a result at the previous index of the receive buffer; and
update the current index of the send buffer and the current index of the receive buffer. However, Catanzaro discloses send, from a receive buffer {“transport that can send and receive buffers”, see Fig. 10, [0133], 3rd sentence} at a current index {“where i represents an index of neuron in the current layer [buffer]”, see Fig. 7 [0111], 1st sentence} of a send buffer {“send one or more [buffer] batches to the compute engine”, [0228]} to a next node {“send a batch only if the [next node] compute engine is not busy.”, see Fig. 7 [0229]} in the ring of nodes, detect a first chunk {“The term ‘chunk’ refers to a size of data related to a neural network input size”, see Fig. 15, [0206]} and a second chunk of a message {“a [second] chunk whose size may be determined by the neural network input size”, [0226], 1st sentence};
receive, in parallel with sending the first chunk {“converged faster for the same degree of data parallelism”, [0039]}, from a previous node {“the previous batch is completed” with an appropriate node/node layer, see Figs. 13 and 14 [0202] 1st sentence} in the ring of nodes, a second chunk {“pre-processing may take place in chunks of data”, [0225], 2nd sentence} of the message and store the second chunk at a current index of the receive buffer {“transferred from the pre-processed buffer to the next [current or next] eligible batch”, [0226], 1st sentence};
reduce, in parallel with sending the first chunk and receiving the second chunk {during the back-propagation by using all-reduce”, [0129], last sentence}, a third chunk {“exchanges a matrix between multiple processes and sums the result so that at the end,” including a plurality of chunks, see Fig. 10 [0129], last sentence} in the send buffer at a previous index {“the context window of the previous layers activations”, see Fig. 2 [0059], 1st sentence} of the receive buffer {“transport that can send and receive buffers”, see Fig. 10, [0133], 3rd sentence} and a fourth chunk {“exchanges a matrix between multiple processes and sums the result so that at the end,” including a plurality of chunks, see Fig. 10 [0129], last sentence} in the receive buffer at the previous index {“These gradients are then back-propagated [indexed] through the network”, [0139], last two sentences} of the receive buffer and store a result {“store activation data for variable length utterances, and for intermediate results”, [0157], 1st sentence} at the previous index of the receive buffer {“These gradients are then back-propagated [indexed] through the network”, [0139], last two sentences}; and
update the current index of the send buffer {“values are the indices of each character in the utterance”, see Fig. [0153], 1st sentence} and the current index of the receive buffer {“The indices generated by the sort are then used to sequentially [update the current index] sum up the gradients for each character”, see Fig. 12 [0153], 4th sentence}.
an apparatus comprising {an appropriate apparatus to perform “aggregation process, the inter-node communication process” ([0137], see Figs. 19 and 20): a first multi-buffer node {“ one set of buffers to store the weights (w).”, see Figs. 19 and 20 [0140]} of a ring of nodes {forming a ring of nodes during “image recognition and a determination of correct solution are iteratively executed” that includes “forward propagation processes at the respective neuron layers on a batch-by-batch basis by using the weight parameters (w) possessed by the individual neuron layers, and next executing the backward propagation processes sequentially at the individual neuron layers” (Emphasis added by Examiner, see Figs. 2, 3, and 4, all cited from [0051]}, the first multi-buffer node including processing circuitry coupled {“[processing circuitry] computing nodes 10 of the change of the processing sequence by the MPI ALLReduce algorithm”, see Fig. 18, [0134], last sentence} to a memory {“ the memory transfer (to the GPU 13 from the CPU 11” which are subcomponents to processing circuitry “computing nodes 10” (see Fig. 18 [0131], 2nd sentence)}.
Fryman/Asaad/Yamazaki and Catanzaro are analogous art because they are from the same problem-solving area, method and systems for handling data over MPI interface.
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art, having the teachings of Fryman/Asaad/Yamazaki and Catanzaro before him or her, to modify Fryman/Asaad/Yamazaki’s system incorporating Catanzaro’s “OpenMPI is configured with the smcuda transport that can send and receive buffers” (see Fig. 10, [0133]).
The suggestion/motivation for doing so would have been to implement a ring algorithm was implemented for higher performance and better stability, since all-reduce is important to the scalability of training (Catanzaro [0133], 1st sentence) as a function of Scalability and Data Parallelism ([0128], [0129]) as a key component of speech recognition have been taken over by a deep learning method involving long short term memory (LSTM) and recurrent neural network (RNN) (Catanzaro [0007], last sentence).
Therefore, it would have been obvious to combine Catanzaro with Fryman/Asaad/Yamazaki to obtain the invention as specified in the instant claim(s).
As per claim 20, the rejection of claim 19 is incorporated and Asaad discloses wherein to reduce the third chunk and the fourth chunk comprises performing an allreduce ring operation on the third chunk and the fourth chunk, {“"chunk" refers to a 32B block that starts from 32B-aligned address”, see Fig. 4 [1320]} wherein the allreduce ring operation comprises a message passing interface (MPI) operation {“collective operations such as an MPI operation, for example, MPI Allreduce”, see Fig. 1, [1822]}, and wherein the ring of nodes comprises an allreduce ring of nodes {“collective class route bits” (see Fig. 6 [1917]) implemented destination “address bits for each dimension, a through e, within a [ring of nodes] 5-dimensional torus” (see Fig. 6, [1918])}.
As per claim 21, the rejection of claim 19 is incorporated and Asaad discloses wherein the message comprises 2*N chunks {“chunk" refers to a [2*N] 32B block that starts from 32B-aligned address”, see Fig. 4 [1320]}, where N represents a number of nodes in the ring of nodes {“intra-rack interprocessor links 90 which may be configurable as a 5-D torus”, see Fig. 1 [0512]}.
As per claim 22, the rejection of claim 21 is incorporated and Asaad discloses wherein a node in the ring of nodes comprises a send buffer having 2*N entries and a receive buffer having 2*N entries {“t two arrays called [send and receive] write-combine buffers 225 and 230”, see Fig. 2, [0181]; other example 2*N entries “example, subunit 262 may be dual-ported, such that a read or write by JTAG access” ([1727], see Fig. 1}.
As per claim 23, the rejection of claim 19 is incorporated and Fryman discloses wherein the processing circuitry comprises one or more of application processing circuitry or graphics processing circuitry {“well as graphics processor 212”, see Fig. 2 [0063]}.
As per claims 24-28 are method claims reciting claim functional language corresponding to the apparatus claim of claims 19-23, respectively, thereby rejected under the same rationale as claims 19-23 recited above.
As per claims 29-33 are computer-readable medium claims reciting claim functional language corresponding to the apparatus claim of claims 19-23, respectively, thereby rejected under the same rationale as claims 19-23 recited above.
Response to Arguments
Applicant’s arguments filed on 02/06/2026 have been considered but deemed moot in view of the new ground of rejection(s).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The following references are indicative the current state of the art regarding claim 19’s “first chunk”/”second chunk, “multi-buffer”, or “message passing interface” (see dependent claim 20): US 12210473 B2, US 11347567 B2, US 20170148433 A1, US 20160364347 A1, US 8990497 B2, and US 6735679 B1.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER A. BARTELS whose telephone number is (571)270-3182. The examiner can normally be reached on Monday-Friday 9:00a-5:30pm EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on 571-272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C. B./
Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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