Detailed Action
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
2. Applicant’s arguments/remarks, filed on 05/27/2026, are acknowledged. Amended claims 1, 10-11, and 15-18 and cancelled claims 5-6 are acknowledged. Claims 1, 3-4, and 7-18 remain pending and have been examined.
Response to Arguments
3. Applicant’s arguments, as per “Applicant Arguments/Remarks Made in Amendment”, dated 05/27/2026, with respect to the rejections of claims 1, 11, and 17 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Yonemoto (US 2021/0314516 A1).
See claims rejection below with regards to claims 1, 11, and 17.
Information Disclosure Statement
4. The information disclosure statements (IDS) submitted on 08/21/2026 and 07/15/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 112
5. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
6. Claims 10 and 17 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contain subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
[0117] of the instant application’s specification teaches a “third layer” on which it is possible to arrange “circuits related to reading”. Elements 121 and 124 are specified as being a substrate each and elements 122 and 123 are taught as being a layer each, in [0115].
Though in a broad perspective a substrate and a layer may in certain electronic applications and usage of language define a common element; in a narrower perspective the substrate and the layer can define different elements of one stacking, thus define different elements; in particular in the makeup or design of an image sensor. As such, for example, the substrate is foundational and a base whereon different layers may be arranged as deposits or etching.
A “third” substrate, according to either claims 10 or 17, is not taught in the specification, though a third layer is.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 1, 3-4, 7-13, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Otaka (US 2018/0198997 A1) in view of Lee et al. (US 2012/0038809 A1) and Yonemoto (US 2021/0314516 A1) and further view of Decker et al. (US 2002/0154231 A1).
8. Regarding claim 1, an imaging device, comprising:
a first substrate (…Otaka, in [0090], teaches a first substrate…);
a second substrate (Otaka, in [0090], teaches a second substrate…);
a photoelectric conversion section (…Otaka teaches photoelectric conversion circuit 20; Fig. 3…) configured to
generate a first signal (…[0073] teaches a signal at holding node ND 24…) and a second signal (…[0072] teaches a signal at holding node ND23…) based on photoelectric conversion (…wherein the holding nodes are part of photoelectric conversion circuit 20…) , wherein
the photoelectric conversion section is in the first substrate (…[0090] teaches pixel array 230 (photoelectric conversion circuit 20) formed on the first substrate…);
a first capacitor configured to hold the first signal (…wherein [0073] teaches a signal holding capacitor CR 21, which is connected to ND 24; Fig. 3…);
a second capacitor configured to hold the second signal (…wherein [0072] teaches signal holding capacitor CS 21, which is connected to ND 23; Fig. 3…);
a first reading section configured to read the first signal held in the first capacitor (…wherein [0096] teaches a readout reset signal VRST; Fig. 3…);
a second reading section configured to read the second signal held in the second capacitor (…wherein [0096] teaches a readout signal VSIG; Fig. 3…).
Otaka does not further teach
a differential amplifier including a first end and a second end; the first signal is input at the first end, and the second signal is input at the second end (…however, (…Lee in [0052] teaches a differentially driven column ADC architecture, circuit 400 to include an inverting and non-inverting ends (fig. 4) which receives two pixel signals (Fig. 4); wherein a pixel output level 410 in a first operating state represents a pixel reset level and in a second operating state output level 410 represents a pixel signal level…); and an initialization section configured to initialize the differential circuit (…wherein switches 440 (a-d) may be viewed as being partial elements of initializing circuit 400.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, that the teaching according Otaka can further be enhanced by a differential column ADC architecture as taught by Lee so to achieve lower read noise and higher dynamic range…), wherein
the differential amplifier is in the second substrate, the second substrate is stacked on the first substrate (…though Otaka teaches a second substrate to include several elements of the imaging device in [0109], Otaka doesn’t teach an amplifier on the second substrate. However, Yonemoto teaches a solid state image capturing device wherein a second 11B includes a comparator (viewed as a differential amplifier), as taught in [0072-0075]; further, [0059] teaches three layers of substrates 11A-C); Fig. 2.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that comparator (amplifier) noise can be reduced by dedicating a substrate that primarily isolates the amplifier from other electronic components (e.g., photoelectric conversion section) of an image sensor…).
Though the combination of prior arts, Otaka in view of Lee and Yonemoto, teaches switches 440 (a-d) (viewed as an initialization section), the prior art combination doesn’t further teach:
wherein the initialization section comprises
at least one third capacitor (…however, Decker teaches a differential amplifier, as taught in [0063], to include feedback capacitor C706 or C708…), and
the at least one third capacitor is in parallel connection with the at least one switch (…wherein C706 and C708 are in parallel with switch transistors M701 and M702.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a comparator circuit, as taught by Lee, could have been implemented with a differential amplifier, as taught by Decker, thus to have the ability to store pixel values at different stages of the pixel’s operation (integration, reset) which is useful for further arithmetic functions thereby obtaining signal value for digital conversion…).
9. Regarding claim 3, Otaka in view of Lee and Yonemoto and further view of Decker teaches the imaging device according to claim 1 (see claim 1 above), wherein
the first capacitor is further configured to hold a reset level (…wherein Lee in [0052]
teaches a pixel output level 410, in a first state, represents a pixel reset level sampled
onto capacitor 445-a…), and
the second capacitor is further configured to hold a signal level (…wherein pixel output
410, in a second state, represents a pixel signal level sampled onto capacitor 445-b
Therefore, it would have been obvious to one skilled in the art before the effective
filing date of the claimed invention, that the teaching according Otaka can further be enhanced by a differential column ADC architecture as taught by Lee so to achieve lower read noise and higher dynamic range…).
10. Regarding claim 4, Otaka in view of Lee and Yonemoto and further view of Decker teaches the imaging device according to claim 1 (see claim 1 above), wherein
a ramp signal is input to one of the first end or the second end (…wherein Lee, in [0052] teaches that circuit 400 receives two ramp signals being input into the circuit; see Fig. 4.
Therefore, it would have been obvious to one skilled in the art before the effective
filing date of the claimed invention, that the teaching according Otaka can further be
enhanced by a differential column ADC architecture as taught by Lee so to achieve lower
read noise and higher dynamic range…).
11. Regarding claim 7, Otaka in view of Lee and Yonemoto and further view of Decker teaches the imaging device according to claim 1 (see claim 1 above) wherein
a ramp signal is input to one of the first end or the second end (…wherein [0052]
(Lee) teaches that ramp reset level 405 is supplied to the positive input of the
comparator 460, Fig. 4…), and
a signal, in which a polarity of the ramp signal is inverted, is input to the second end
(…wherein [0052] (Lee) teaches that ramp signal level 415 is supplied to the inverting
(negative) input of the comparator 460, Fig. 4.
Therefore, it would have been obvious to one skilled in the art before the effective
filing date of the claimed invention, that the teaching according Otaka can further be
enhanced by a differential column ADC architecture as taught by Lee so to achieve lower
read noise and higher dynamic range…).
12. Regarding claim 8, Otaka in view of Lee and Yonemoto and further view of Decker teaches the imaging device according to claim 1 (see claim 1 above) wherein
a ramp signal is input to one of the first end or the second end (…wherein [0052] (Lee)
teaches that ramp signal level 415 is supplied to the positive input of the comparator 460,
Fig. 4…), and
a signal of a constant voltage is input to the second end (…[0060] teaches that ramp
reset level 405 may be a DC signal.
Therefore, it would have been obvious to one skilled in the art before the effective
filing date of the claimed invention, that the teaching according Otaka can further be
enhanced by a differential column ADC architecture as taught by Lee so to achieve lower
read noise and higher dynamic range…).
13. Regarding claim 9, Otaka in view of Lee and Yonemoto and further view of Decker teaches the imaging device according to claim 1 (see claim 1 above) wherein
the first signal is photoelectrically converted in a first exposure period (…wherein Otaka
teaches CR 21 is (a first corresponding) signal holding capacitor, relative to a photoelectric conversion reading part 211 ([0073])…), and
the second signal is photoelectrically converted in a second exposure period (…wherein
Otaka teaches CS 21 is a second corresponding signal holding capacitor, relative to a
photoelectric conversion reading part 211 ([0072]).
Therefore, it would have been obvious to one skilled in the art before the effective
filing date of the claimed invention, that the teaching according Otaka can further be
enhanced by a differential column ADC architecture as taught by Lee so to achieve lower
read noise and higher dynamic range…).
14. Regarding claim 10, Otaka in view of Lee and Yonemoto and further view of Decker teaches the imaging device according to claim 1 (see claim 1 above), further comprising:
a third substrate that includes the first capacitor and the second capacitor, wherein
the first substrate and the third substrate are in a stacked arrangement (…wherein Otaka in [0090] teaches an imaging device 10 of a stacked structure of a first and second substrates; with pixel array 230 formed on a first substrate and a holding part array 240 formed on a third substrate…).
15. Regarding claim 11, an imaging method (…Otaka teaches a method for
driving a solid-state imaging device, [0002]…), comprising:
holding, in a first capacitor, a first signal from a photoelectric conversion section
(… Otaka, in [0073], teaches a signal holding capacitor CR 21, which is connected
to ND 24; wherein ND 24 via a transistor connects to circuit 211 (photoelectric
conversion circuit; Fig. 3…); wherein
the photoelectric conversion section is in a first substrate (wherein Otaka, in [0106], teaches a first substrate 110 including photoelectric conversion reading part 211…);
holding, in a second capacitor, a second signal from the photoelectric conversion
section (…Otaka, in [0072], teaches signal holding capacitor CS 21, which is
connected to ND 23; wherein ND 23 via a transistor connects to circuit 211
(photoelectric conversion circuit; Fig. 3…);
reading, via a first reading section, the first signal held in the first capacitor
(…wherein Otaka, in [0080], teaches a source-follower transistor SF3R-Tr outputs
a read-out voltage (VRST) of column output with respect to the held voltage of the
second signal holding capacitor CR 21 to the second vertical signal line
LSGN 12…);
reading, via a second reading section, the second signal held in the second
capacitor (…wherein Otaka, in [0077] teaches a source-follower transistor SF2S-Tr
outputs a read-out voltage (VSIG) of column output with respect to the held voltage of the first signal holding capacitor CS 21 to the first vertical signal line
LSGN 11…).
Though Otaka in [0055] teaches that converted signals corresponding to readout
signal and readout reset signal are in parallel supplied to as a differential signal to a
column readout circuit, Otaka does not disclose the following limitations which are
mapped in accordance with the teachings of Lee:
initializing, via an initializing circuit, a differential amplifier in which the first signal is
input to a first end of the differential amplifier, and the second signal is input to a second
end of the differential amplifier (…Lee in [0052] teaches a differentially driven column
ADC architecture, circuit 400 to include an inverting and non-inverting ends (fig.
4) which receives two pixel signals (Fig. 4); wherein a pixel output level 410 in a
first operating state represents a pixel reset level and in a second operating state
output level 410 represents a pixel signal level; wherein switches 440 (a-d) may
be viewed as being partial elements of initializing circuit 400.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention, that the teaching according Otaka can
further be enhanced by a differential column ADC architecture as taught by Lee so to
achieve lower read noise and higher dynamic range…).
Otaka in view of Lee doesn’t further teach wherein the differential amplifier is in a second substrate, the second substrate is stacked on the first substrate (…though Otaka teaches a second substrate to include several elements of the imaging device in [0109], Otaka doesn’t teach an amplifier on the second substrate. However, Yonemoto teaches a solid state image capturing device wherein a second 11B includes a comparator (viewed as a differential amplifier), as taught in [0072-0075]; further, [0059] teaches three layers of substrates 11A-C); Fig. 2.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that comparator (amplifier) noise can be reduced by dedicating a substrate that primarily isolates the amplifier from other electronic components (e.g., photoelectric conversion section) of an image sensor…).
Otaka in view of Lee and Yonemoto does not disclose the following limitation which are taught with respect to reference by Decker.
Decker teaches a differential amplifier 700 (comparable to circuit 400 as taught by Lee) wherein
the initializing circuit includes at least one third capacitor and at least one switch,
and the at least one third capacitor is in parallel connection with the at least one switch
(…Decker, in [0063], teaches feedback capacitors C706 or C708; wherein C706 and C708
are in parallel with switch transistors M701 and M702…); and
comparing a difference between the first signal and the second signal with a ramp signal (…wherein Decker, in [0065], teaches that the operation of the
differential amplifier 700, given the functions of its switching (initialization),
produces a resulting differential voltage between conductors 502a and 502b.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that a comparator circuit as taught by Lee
could have been implemented with a differential amplifier as taught by Decker, thus
having the ability to store pixel values at different stages of the pixels’ operation
(integration, reset) which can be useful for further arithmetic functions for obtaining
signal value for digital conversion…).
16. Regarding claim 12, Otaka in view of Lee and Yonemoto and further view of Decker teach the imaging method according to claim 11, wherein
the first signal is at a reset level (…wherein Lee in [0052] teaches a pixel output level 410, in a first state, represents a pixel reset level sampled onto capacitor 445-a…), and
the second signal is at a signal level (…wherein pixel output 410, in a second state, represents a pixel signal level sampled onto capacitor 445-b.
Therefore, it would have been obvious to one skilled in the art before the effective
filing date of the claimed invention, that the teaching according Otaka can further be
enhanced by a differential column ADC architecture as taught by Lee so to achieve lower
read noise and higher dynamic range...).
17. Regarding claim 13, Otaka in view of Lee and Yonemoto and further view of Decker teaches the imaging method according to claim 11 (see claim 11 above), further comprising:
holding a signal, photoelectrically converted in a first exposure period, in the first
capacitor as the first signal (…Otaka in [00118-119] teaches time t-3, wherein transistor
SHR-1 becomes high and readout signal VRST is held in holding capacitor CR 21; Fig.
7D…); and
holding a signal, photoelectrically converted in a second exposure period, in the second
capacitor as the second signal (…Otaka in [0122-123] teaches time t-5, wherein transistor
SHS-1 becomes high and readout signal VSIG is held in holding capacitor CS 21; Fig.
7E…).
18. Regarding claim 15, Otaka in view of Lee and Yonemoto and further view of Decker teaches the imaging device according to claim 1, further comprising
an auto-zero control section configured to execute an auto-zero process in which the at
least one switch is turned off, wherein the initialization section is further configured to initialize the differential amplifier based on the execution of the auto-zero process (…wherein Lee, in
[0054], teaches an auto-zero mode, with regards to a first and second operating states;
further, [0059], teaches that auto-zero mode takes placed when feedback loop switches
are closed; thus the first and second operating states along the use of switches 440 a-f
are control section which enable the auto-zero mode or the release thereof.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention, that the teaching according Otaka can
further be enhanced by a differential column ADC architecture as taught by Lee so to
achieve lower read noise and higher dynamic range…).
19. Regarding claim 16, claim 16 is rejected for reasons related to claim 15 (see claim 15
above).
20. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Otaka (US
2018/0198997 A1) in view of Lee et al. (US 2012/0038809 A1; further referred to as Lee)
and Yonemoto (US 2021/0314516 A1) and further view of Decker et al. (US 2002/0154231 A1; further referred to as Decker) and Fu et al. (US 2022/0150433 A1; further referred to as Fu).
21. Regarding claim 14, Otaka in view of Lee and Yonemoto and further view of Decker teaches the imaging method according to claim 13 (see claim 13 above).
However, the references do not further disclose the method further comprising:
determining whether a difference between the first signal and the second signal is
within a predetermined range.
However, Fu teaches a photoelectric conversion circuit including a differential circuit,
wherein Fu teaches:
determining whether a difference between the first signal and the second signal is within a predetermined range (…wherein [0006] teaches that a comparison circuit receives
a difference signal from a differential circuit and compares the difference signal with a
preset threshold to output a pulse signal.
Therefore, it would have been obvious to one of ordinary skill in the art that the
disclosed signal comparison as taught by Fu could have been incorporated in the
combined teachings of Otaka in view of Lee and Decker, thus to determine whether a
particular event may have transpired between corresponding exposure periods of the
pixel…).
22. Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Otaka
(US 2018/0198997 A1) in view of Otaka (US 2021/0144330 A1; further referred to as
Otaka-2) and Lee et al. (US 2012/0038809 A1) and further view of Yonemoto (US 2021/0314516 A1).
23. Regarding claim 17, an imaging device (…Otaka teaches a solid-state imaging device
in [0053], Fig. 2…), comprising:
a photoelectric conversion section (…Otaka in [0059] teaches photoelectric
conversion reading part 211; Fig. 3…) configured to generate
a first signal (…signal at holding node ND 24, as taught in [0073]…) and
a second signal based on photoelectric conversion (…signal at holding node ND 23,
as taught in [0072]; wherein the holding nodes are part of a photoelectric conversion
circuit 20 in Fig. 3…);
a first capacitor configured to hold the first signal (…[0073] teaches a signal holding
capacitor CR 21, which is connected to ND 24; Fig. 3…), wherein
the first capacitor is connected to a floating diffusion (FD) of the photoelectric conversion
section via an intra-pixel amplification transistor and a global shutter (GS) transistor (…wherein CR21 is connected to FD21 through SF1-Tr (which at its drain is connected to power
supply Vddpix, thus viewed as an amplifying transistor; see [0066] and Fig. 3) and SHR1-
Tr (wherein as stated in [0073] SHR1-Tr connects CR21 to output node 21 of the
photoelectric conversion reading part 211 through node ND 24 in the global shutter
period or the clearing period; see Fig. 3…);
a first reading section configured to read the first signal held in the first capacitor
(…wherein Otaka further, in [0096], teaches a readout reset signal VRST; wherein Fig. 3
depicts the reading out of VRST via output part 2124…), wherein
a second reading section configured to read the second signal held in the second
capacitor (…[0096] teaches a readout signal VSIG; wherein Fig. 3 depicts the reading out
of VSIG via output part 2123…), wherein
a first amplification transistor configured to output the first signal to the first reading
section via a first vertical signal line (VSL) (…[0078] teaches SF3R-Tr for outputting the
signal held in capacitor CR21 via LSGN12; Fig. 3…);
a second amplification transistor configured to output the second signal to the second
reading section via a second VSL (…[0077] teaches SF2S-Tr for outputting the signal held
in capacitor CS21 via LSGN11; Fig. 3…),
a second capacitor configured to hold the second signal, wherein the second capacitor is
connected to the FD of the photoelectric conversion section via the intra-pixel amplification
transistor and the GS transistor (…wherein CS21 connects to FD 21 through SF1-Tr and
SHS1-Tr; as such in this reference Otaka does not teach the same set of transistors
connecting capacitors CS21 and CR21 to FD21.
However, Otaka-2 teaches an imaging device wherein a similar pixel design is
taught; Fig. 2 discloses sample-and-hold capacitors CR21 and CS21; wherein each
capacitors are connected to floating diffusion FD21 through transistors SEL1-Tr (viewed
as an amplification transistor) and SF1-Tr (viewed as a global shutter transistor) as
taught in [0086] and [0088].
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that a 4Tr pixel design, as taught by Otaka-2
could have been implemented as the pixel design as taught by Otaka, wherein a 4Tr pixel
design may be applied in a case where a plurality of photodiodes and transfer transistors
share transistors of functionality and thereby reduce overall size of the pixel design…);
Further, though Otaka in [0055] teaches that converted signals corresponding to readout
signal and readout reset signal are in parallel supplied to as a differential signal to a column
readout circuit, Otaka does not disclose:
the first reading section comprises a third capacitor (…However, Lee, in [0052-0055],
teaches sampling capacitor 445a which holds a pixel output level of a pixel reset
value…);
the second reading section comprises a fourth capacitor (…wherein, Lee, in [0052-
0054], teaches sampling capacitor 445b which holds a pixel output level of a pixel signal
level…);
a differential amplifier comprising a first end and a second end, wherein the first signal is
input at the first end via the third capacitor, and the second signal is input at the second end via
the fourth capacitor (…Lee in [0052] teaches a differentially driven column ADC
architecture, circuit 400 to include an inverting and non-inverting ends (fig. 4) which
receives two pixel signals (Fig. 4); wherein a pixel output level 410 in a first operating
state represents a pixel reset level and in a second operating state output level 410
represents a pixel signal level…), and
an initialization section configured to initialize the differential amplifier (…wherein switches 440 (a-f) may be viewed as being partial elements of initializing circuit 400.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention, that the teaching according Otaka can further be enhanced by a differential column ADC architecture as taught by Lee so to
achieve lower read noise and higher dynamic range…), wherein
the photoelectric conversion section is in a first substrate (…wherein Otaka, in [0090],
teaches a stacked structure forming a solid-state imaging device made of a first
substrate containing pixel array; Fig. 3…),
each of the first capacitor and the second capacitor is in a second substrate (…wherein
Otaka, in [0090] teaches a second substrate for the holding part array. Further, [0109]
specifies the first and second substrate, containing the pixel and holding circuitries in
accordance with Fig. 3; in addition, [0018] teaches a column readout circuit that may be
included on the second substrate (which may include amplifiers and analog-to-
digital converters in accordance with [0098])…), and
the differential amplifier is in a third substrate, and the first substrate, the second substrate, and the third substrate are in a stacked arrangement (…Otaka does not further teach a third substrate whereon a differential circuit is included.
However, Yonemoto teaches a solid state image capturing device wherein a third substrate 11B includes a comparator (viewed as a differential amplifier), as taught in [0072-0075]; further, [0059] teaches three layers of substrates 11A-C) making up the solid state image capturing device; Fig. 2.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that comparator (amplifier) noise can be reduced by dedicating a substrate that primarily isolates the amplifier from other electronic components (e.g., photoelectric conversion section) of an image sensor…).
24. Regarding claim 18, Otaka in view of Otaka-2 and Lee and further view of Yonemoto teaches the imaging device according to claim 17 (see claim 17 above), further comprising
an auto-zero control section configured to execute an auto-zero process, wherein
the initialization section is further configured to initialize the differential amplifier based on the
execution of the auto-zero process (…wherein Lee, in [0054], teaches an auto-zero mode,
with regards to a first and second operating states implemented through circuit 400;
further, [0059], teaches that auto-zero mode takes placed when feedback loop switches
are closed; thus the first and second operating states along the use of switches 440 a-f
are control section which enable the auto-zero mode or the release thereof.
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention, that the teaching according Otaka can
further be enhanced by a differential column ADC architecture as taught by Lee so to
achieve lower read noise and higher dynamic range…).
Conclusion
25. Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SURAFEL YILMAKASSAYE whose telephone number is (703)756-1910. The examiner can normally be reached Monday-Friday 8:30am-5:00pm.
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/SURAFEL YILMAKASSAYE/Examiner, Art Unit 2639
/TWYLER L HASKINS/Supervisory Patent Examiner, Art Unit 2639
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