Detailed Action
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgements
2. Applicant’s arguments/remarks, filed on 01/08/2026, are acknowledged. Newly added claims 15-18 are acknowledged. Claims 1 and 3-18 remain pending and have been examined.
Response to Arguments
3. The Applicant argues/remarks, on pages 8-10 (of 16), without particularly stating which rejection and which limitation is without a proper motivation to be combined with a reference, thus to teach a limitation lacking in a primary or secondary reference, the Applicant sets a principled basis for what a rejection under 35 U.S.C. 103 should entail.
The Applicant, on pages 10-13(of 16), particularly points out, with regards to claims 1 and 11, that Otaka, in view of Lee and Decker fail to teach the feature of:
“…wherein the initialization section comprises at least one third capacitor and at least one switch, and the at least one capacitor is in parallel connection with the at least one switch…”.
Further, on pages 12-13, Applicant, with regards to Fig. 7 as taught by Decker, states that capacitor C706 fails to be in a parallel relationship with switch M702; for the reason that capacitor C706’s one end is either connected to switch M703 or switch M705. Likewise, capacitor C708 is said not to be in a parallel relationship with switch M701; for the reason that capacitor C708’s one end is connected either to switch M704 or the switch M706.
Further, the Applicant, on page 13 (of 16), states that claims 3-10 and 12-13 are not further taught based their dependence on claims 1 or 11.
4. Response
Examiner respectfully disagrees for the following reasons:
The rational to combine the prior art references is defined within the technical functionalities of certain circuitries which are implemented for particular reasons. Thus, the motivation to combine the reference in accordance with Lee is that Lee teaches a differentially driven column ADC architecture which in part relies on a pixel signal level and a pixel reset level thus to produce image data. As such, one may say that Lee is relied upon for teaching a secondary or third stage function in a process of photoelectrically converting a light signal into a stable image data. As such, the primary reference, in accordance with Otaka, is relied upon for teaching a first stage of capturing a light signal and electrically converting and temporarily storing the electrical signal. Therefore, the references teach a shared art and do complement one another in functionality.
The relied upon teaching in accordance with Decker, in particular Fig. 7, does present a capacitor C706 which is in a parallel relationship with switch M702 when switch M703 is in a conductive state (or similarly capacitor C708 relative to switch M701). Whether C706 has two switches at a junction which branch into separate circuit lines, as such either through M705 or M703, does automatically eliminate a potential parallel relationship between the nodes that are common to switch M702 and capacitor C706 (through switch M703). As such, as currently limited, claim 1 is broad enough wherein Decker addresses the limited parallel relationship of capacitor C706 and switch M702.
It remains that sensor based signal processing (of variously sensed environmental data; light, temperature, pressure...etc.) can rely on common or similar electrical circuits, used for amplification, filtering, linearization, to convert raw sensed information to data information that is implemented into an output format.
5. Regarding claim 14, the Applicant, on pages 13-15 (of 16) argues/remarks that Fu fails to teach what is particularly claimed in claim 14. The Applicant further presents detailed subject matter defined within the specification of the instant application, as specified in [0086] and [0129] of the instant application. Fu is not referenced as teaching the specific inputs and outputs of the differential comparator, regarding a difference between a first and second signal wherein the difference might indicate a movement (or the absence thereof) of a subject. Neither claims 13 or claim 11, on which claim 14 is dependent on, detail to limit how claimed signals are relative to a movement condition of a subject; which itself is subject to logical determination of further image processing analysis further down the pipeline from the analog domain of difference amplification and common-mode noise rejection. As specified in [0144] of the instant application, “…a signal charge amount is obtained by taking the difference, and it is determined whether or not there is a change in the signal charge amount, thereby detecting whether or not there is motion in the subject”
Thus, for the broadly claimed subject matter of claim 14, Fu teaches “…the determining whether or not a difference between the first signal and the second signal is within a predetermined range…” (as limited in claim 14); wherein Fu in [0006] teaches a comparison circuit which receives a difference signal from differential circuit, so to compare the difference signal with a preset threshold.
The motivation to combine Fu with an art reference which teaches a differential amplifier (as such Decker) would be obvious to one of ordinary skill in the art since the differential output of the taught differential amplifier, relative to a threshold, can be used to make conclusive determinations to various conditions of sensed subject matters of environmental observations.
Information Disclosure Statement
6. The information disclosure statement (IDS) submitted on 01/28/2026 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
8. Claims 1, 3-13 and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Otaka (US 2018/0198997 A1) in view of Lee et al. (US 2012/0038809 A1; further referred to as Lee) and further view of Decker et al. (US 2002/0154231 A1; further referred to as Decker).
9. Regarding claim 1 an imaging device, comprising:
a photoelectric conversion section (…Otaka in [0059] teaches photoelectric conversion reading part 211; Fig. 3…) configured to generate:
a first signal (…signal at holding node ND 24, as taught in [0073]…) and
a second signal based (…signal at holding node ND 23, as taught in [0072]…) on photoelectric conversion (…wherein the holding nodes are part of a photoelectric conversion circuit 20 in Fig. 3…);
a first capacitor configured to hold the first signal (…[0073] teaches a signal holding capacitor CR 21, which is connected to ND 24; Fig. 3…);
a second capacitor configured to hold the second signal (…[0072] teaches signal holding capacitor CS 21, which is connected to ND 23; Fig. 3…);
a first reading section configured to read the first signal held in the first capacitor (…[0096] teaches a readout reset signal VRST; Fig. 3…);
a second reading section configured to read the second signal held in the second
capacitor (…[0096] teaches a readout signal VSIG; Fig. 3…).
Though Otaka in [0055] teaches that converted signals corresponding to readout signal
and readout reset signal are in parallel supplied to as a differential signal to a column readout
circuit, Otaka does not disclose:
a differential circuit including a first end and a second end, wherein which the first signal
is input at the first end and the second signal is input at the second end and
the second signal is input at the second end; and
an initialization section configured to initialize the differential circuit.
However, Lee teaches a differential column ADC architecture for image sensing in which
pixel and ramp outputs are used to differentially drive a comparator stage of a column ADC;
wherein Lee teaches
a differential circuit including a first end and a second end, wherein the first signal is
input at the first end and the second signal is input at the second end and the second signal is
input at the second end (…Lee in [0052] teaches a differentially driven column ADC
architecture, circuit 400 to include an inverting and non-inverting ends (fig. 4) which
receives two pixel signals (Fig. 4); wherein a pixel output level 410 in a first operating state represents a pixel reset level and in a second operating state output level 410
represents a pixel signal level…); and
an initialization section configured to initialize the differential circuit (…wherein switches 440 (a-d) may be viewed as being partial elements of initializing circuit 400.
Therefore it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention, that the teaching according Otaka can
further be enhanced by a differential column ADC architecture as taught by Lee so to
achieve lower read noise and higher dynamic range…).
Though the combination of prior art, Otaka in view of Lee, teaches switches 440 (a-d),
the prior art combination doesn’t further teach:
wherein the initialization section comprises at least one third capacitor, and
the at least one third capacitor is in parallel connection with the at least one switch.
However, Decker teaches a differential amplifier to include
at least one third capacitor (…wherein Decker, in [0063], teaches feedback capacitors C706 or C708…), and
the at least one third capacitor is in parallel connection with the at least one
switch (…wherein C706 and C708 are in parallel to with switch transistors M701 and M702
Therefore, it would have been obvious to one of ordinary skill in the art before the
effective filing date of the claimed invention that a comparator circuit as taught by Lee
could have been implemented with a differential amplifier as taught by Decker, thus
having the ability to store pixel values at different stages of the pixels’ operation
(integration, reset) which can be useful for further arithmetic functions for obtaining
signal value for digital conversion…).
10. Regarding claim 3, Otaka in view of Lee and further view of Decker teaches the imaging
device according to claim 1 (see claim 1 above) the imaging device according to claim 1 (see claim 1 above), wherein
the first capacitor is further configured to hold a reset level (…wherein Lee in [0052]
teaches a pixel output level 410, in a first state, represents a pixel reset level sampled
onto capacitor 445-a…), and
the second capacitor is further configured to hold a signal level (…wherein pixel output
410, in a second state, represents a pixel signal level sampled onto capacitor 445-b
Therefore it would have been obvious to one skilled in the art before the effective
filing date of the claimed invention, that the teaching according Otaka can further be
enhanced by a differential column ADC architecture as taught by Lee so to achieve lower
read noise and higher dynamic range.…).
11. Regarding claim 4, Otaka in view of Lee and further view of Decker teaches the imaging
device according to claim 1 (see claim 1 above), wherein a ramp signal is input to one of the
first end or the second end (…wherein Lee, in [0052] teaches that circuit 400 receives two
ramp signals being input into the circuit; see Fig. 4.
Therefore it would have been obvious to one skilled in the art before the effective
filing date of the claimed invention, that the teaching according Otaka can further be
enhanced by a differential column ADC architecture as taught by Lee so to achieve lower
read noise and higher dynamic range…).
12. Regarding claim 5, Otaka in view of Lee and further view of Decker teaches the imaging
device according to claim 1 (see claim 1 above) wherein
the differential circuit is a differential comparator (…wherein circuit 400 (Lee) may be
viewed as a differential comparator, [0062], Fig. 4.
Therefore it would have been obvious to one skilled in the art before the effective
filing date of the claimed invention, that the teaching according Otaka can further be enhanced by a differential column ADC architecture as taught by Lee so to achieve lower
read noise and higher dynamic range…).
13. Regarding claim 6, Otaka in view of Lee and further view of Decker teaches the imaging
device according to claim 1 (see claim 1 above) wherein
the differential circuit includes a differential amplifier (…wherein element 460 (of circuit
400 (Lee), [0053] may be viewed as a differential amplifier, Fig. 4.
Therefore it would have been obvious to one skilled in the art before the effective
filing date of the claimed invention, that the teaching according Otaka can further be
enhanced by a differential column ADC architecture as taught by Lee so to achieve lower
read noise and higher dynamic range…).
14. Regarding claim 7, Otaka in view of Lee and further view of Decker teaches the imaging
device according to claim 1 (see claim 1 above) wherein
a ramp signal is input to one of the first end or the second end (…wherein [0052]
(Lee) teaches that ramp reset level 405 is supplied to the positive input of the
comparator 460, Fig. 4…), and
a signal, in which a polarity of the ramp signal is inverted, is input to the second end
(…wherein [0052] (Lee) teaches that ramp signal level 415 is supplied to the inverting
(negative) input of the comparator 460, Fig. 4.
Therefore it would have been obvious to one skilled in the art before the effective
filing date of the claimed invention, that the teaching according Otaka can further be
enhanced by a differential column ADC architecture as taught by Lee so to achieve lower
read noise and higher dynamic range…).
15. Regarding claim 8, Otaka in view of Lee and further view of Decker teaches the imaging
device according to claim 1 (see claim 1 above) wherein
a ramp signal is input to one of the first end or the second end (…wherein [0052] (Lee)
teaches that ramp signal level 415 is supplied to the positive input of the comparator 460,
Fig. 4…), and
a signal of a constant voltage is input to the second end (…[0060] teaches that ramp
reset level 405 may be a DC signal.
Therefore it would have been obvious to one skilled in the art before the effective
filing date of the claimed invention, that the teaching according Otaka can further be
enhanced by a differential column ADC architecture as taught by Lee so to achieve lower
read noise and higher dynamic range…).
16. Regarding claim 9, Otaka in view of Lee and further view of Decker teaches the imaging
device according to claim 1 (see claim 1 above) wherein
the first signal is photoelectrically converted in a first exposure period (…wherein Otaka
teaches CR 21 is (a first corresponding) signal holding capacitor, relative to a
photoelectric conversion reading part 211 ([0073])…), and
the second signal is photoelectrically converted in a second exposure period (…wherein
Otaka teaches CS 21 is a second corresponding signal holding capacitor, relative to a
photoelectric conversion reading part 211 ([0072]).
Therefore it would have been obvious to one skilled in the art before the effective
filing date of the claimed invention, that the teaching according Otaka can further be
enhanced by a differential column ADC architecture as taught by Lee so to achieve lower
read noise and higher dynamic range…).
17. Regarding claim 10, Otaka in view of Lee and further view of Decker teaches the
imaging device according to claim 1 (see claim 1 above) further comprising:
a first substrate that includes the photoelectric conversion section, and a second
substrate that includes the first capacitor and the second capacitor, wherein the first substrate
and the second substrate are in a stacked arrangement (…wherein Otaka in [0090] teaches
an imaging device 10 of a stacked structure of a first and second substrates; with pixel
array 230 formed on a first substrate and a holding part array 240 formed on a second
substrate…).
18. Regarding claim 11, an imaging method (…Otaka teaches a method for
driving a solid-state imaging device, [0002]…), comprising:
holding, in a first capacitor, a first signal from a photoelectric conversion section
(… Otaka, in [0073], teaches a signal holding capacitor CR 21, which is connected
to ND 24; wherein ND 24 via a transistor connects to circuit 211 (photoelectric
conversion circuit; Fig. 3…);
holding, in a second capacitor, a second signal from the photoelectric conversion
section (…Otaka, in [0072], teaches signal holding capacitor CS 21, which is
connected to ND 23; wherein ND 23 via a transistor connects to circuit 211
(photoelectric conversion circuit; Fig. 3…);
reading, via a first reading section, the first signal held in the first capacitor
(…wherein Otaka, in [0080], teaches a source-follower transistor SF3R-Tr outputs
a read-out voltage (VRST) of column output with respect to the held voltage of the
second signal holding capacitor CR 21 to the second vertical signal line
LSGN 12…);
reading, via a second reading section, the second signal held in the second
capacitor (…wherein Otaka, in [0077] teaches a source-follower transistor SF2S-Tr
outputs a read-out voltage (VSIG) of column output with respect to the held
voltage of the first signal holding capacitor CS 21 to the first vertical signal line
LSGN 11…).
Though Otaka in [0055] teaches that converted signals corresponding to readout
signal and readout reset signal are in parallel supplied to as a differential signal to a
column readout circuit, Otaka does not disclose the following limitations which are
mapped in accordance with the teachings of Lee:
initializing, via an initializing circuit, a differential circuit in which the first signal is
input to a first end of the differential circuit, and the second signal is input to a second
end of the differential circuit (…Lee in [0052] teaches a differentially driven column
ADC architecture, circuit 400 to include an inverting and non-inverting ends (fig.
4) which receives two pixel signals (Fig. 4); wherein a pixel output level 410 in a
first operating state represents a pixel reset level and in a second operating state
output level 410 represents a pixel signal level; wherein switches 440 (a-d) may
be viewed as being partial elements of initializing circuit 400.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, that the teaching according Otaka can further be enhanced by a differential column ADC architecture as taught by Lee so to achieve lower read noise and higher dynamic range…).
Otaka in view of Lee does not disclose the following limitation which are taught
with respect to reference by Decker. Decker teaches a differential amplifier 700
(comparable to circuit 400 as taught by Lee) wherein
the initializing circuit includes at least one third capacitor and at least one switch,
and the at least one third capacitor is in parallel connection with the at least one switch
(…Decker, in [0063], teaches feedback capacitors C706 or C708; wherein C706 and C708 are in parallel with switch transistors M701 and M702…); and
comparing a difference between the first signal and the second signal with a
ramp signal (…wherein Decker, in [0065], teaches that the operation of the
differential amplifier 700, given the functions of its switching (initialization),
produces a resulting differential voltage between conductors 502a and 502b.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a comparator circuit as taught by Lee could have been implemented with a differential amplifier as taught by Decker, thus having the ability to store pixel values at different stages of the pixels’ operation (integration, reset) which can be useful for further arithmetic functions for obtaining signal value for digital conversion…).
19. Regarding claim 12, claim 12 is rejected for reasons related to claim 3.
20. Regarding claim 13, Otaka in view of Lee and further view of Decker teaches the
imaging method according to claim 11 (see claim 11 above), further comprising:
holding a signal, photoelectrically converted in a first exposure period, in the first
capacitor as the first signal (…Otaka in [00118-119] teaches time t-3, wherein transistor SHR-1 becomes high and readout signal VRST is held in holding capacitor CR 21; Fig.
7D…); and
holding a signal, photoelectrically converted in a second exposure period, in the second
capacitor as the second signal (…Otaka in [0122-123] teaches time t-5, wherein transistor
SHS-1 becomes high and readout signal VSIG is held in holding capacitor CS 21; Fig.
7E…).
21. Regarding claim 15, the imaging device according to claim 1, further comprising
an auto-zero control section configured to execute an auto-zero process in which the at least one switch is turned off, wherein the initialization section is further configured to initialize the differential circuit based on the execution of the auto-zero process (…wherein Lee, in [0054], teaches an auto-zero mode, with regards to a first and second operating states; further, [0059], teaches that auto-zero mode takes placed when feedback loop switches are closed; thus the first and second operating states along the use of switches 440 a-f are control section which enable the auto-zero mode or the release thereof.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, that the teaching according Otaka can further be enhanced by a differential column ADC architecture as taught by Lee so to achieve lower read noise and higher dynamic range…).
22. Regarding claim 16, claim 16 is rejected for reasons related to claim 15 (see claim 15 above).
23. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Otaka (US
2018/0198997 A1) in view of Lee et al. (US 2012/0038809 A1; further referred to as Lee)
and Decker et al. (US 2002/0154231 A1; further referred to as Decker) and further view
of Fu et al. (US 2022/0150433 A1; further referred to as Fu).
24. Regarding claim 14, Otaka in view of Lee and Decker teaches the imaging method
according to claim 13 (see claim 13 above).
However, the references do not further disclose the method further comprising:
determining whether or not a difference between the first signal and the second signal is
within a predetermined range.
However, Fu teaches a photoelectric conversion circuit including a differential circuit,
wherein Fu teaches:
determining whether or not a difference between the first signal and the second signal is
within a predetermined range (…wherein [0006] teaches that a comparison circuit receives
a difference signal from a differential circuit and compares the difference signal with a
preset threshold to output a pulse signal.
Therefore it would have been obvious to one of ordinary skill in the art that the
disclosed signal comparison as taught by Fu could have been incorporated in the
combined teachings of Otaka in view of Lee and Decker, thus to determine whether a particular event may have transpired between corresponding exposure periods of the pixel…).
25. Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Otaka (US 2018/0198997 A1) in view of Otaka (US 2021/0144330 A1; further referred to as Otaka-2) and Lee et al. (US 2012/0038809 A1; further referred to as Lee) and further view of Shim (US 11,206,367 B1).
26. Regarding claim 17, an imaging device (…Otaka teaches a solid-state imaging device in [0053], Fig. 2…), comprising:
a photoelectric conversion section (…Otaka in [0059] teaches photoelectric conversion reading part 211; Fig. 3…) configured to generate
a first signal (…signal at holding node ND 24, as taught in [0073]…) and
a second signal based on photoelectric conversion (…signal at holding node ND 23, as taught in [0072]; wherein the holding nodes are part of a photoelectric conversion circuit 20 in Fig. 3…);
a first capacitor configured to hold the first signal (…[0073] teaches a signal holding capacitor CR 21, which is connected to ND 24; Fig. 3…), wherein
the first capacitor is connected to a floating diffusion of the photoelectric conversion section via an intra-pixel amplification transistor and a global shutter (GS) transistor (…wherein CR21 is connected to FD21 through SF1-Tr (which at its drain is connected to power supply Vddpix, thus viewed as an amplifying transistor; see [0066] and Fig. 3) and SHR1-Tr (wherein as stated in [0073] SHR1-Tr connects CR21 to output node 21 of the photoelectric conversion reading part 211 through node ND 24 in the global shutter period or the clearing period; see Fig. 3…);
a second capacitor configured to hold the second signal, wherein the second capacitor is connected to the FD of the photoelectric conversion section via the intra-pixel amplification transistor and the GS transistor (…wherein CS21 connects to FD 21 through SF1-Tr and SHS1-Tr; as such in this reference Otaka does not teach the same set of transistors connecting capacitors CS21 and CR21 to FD21.
However, Otaka-2 teaches an imaging device wherein a similar pixel design is taught; Fig. 2 discloses sample-and-hold capacitors CR21 and CS21; wherein each capacitors are connected to floating diffusion FD21 through transistors SEL1-Tr (viewed as an amplification transistor) and SF1-Tr (viewed as a global shutter transistor) as taught in [0086] and [0088].
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that a 4Tr pixel design, as taught by Otaka-2 could have been implemented as the pixel design as taught by Otaka, wherein a 4Tr pixel design may be applied in a case where a plurality of photodiodes and transfer transistors share transistors of functionality and thereby reduce overall size of the pixel design…);
a first reading section configured to read the first signal held in the first capacitor (…wherein Otaka further, in [0096], teaches a readout reset signal VRST; wherein Fig. 3 depicts the reading out of VRST via output part 2124…), wherein
a second reading section configured to read the second signal held in the second capacitor (…[0096] teaches a readout signal VSIG; wherein Fig. 3 depicts the reading out of VSIG via output part 2123…), wherein
a first amplification transistor configured to output the first signal to the first reading section via a first vertical signal line (VSL) (…[0078] teaches SF3R-Tr for outputting the signal held in capacitor CR21 via LSGN12; Fig. 3…);
a second amplification transistor configured to output the second signal to the second reading section via a second VSL (…[0077] teaches SF2S-Tr for outputting the signal held in capacitor CS21 via LSGN11; Fig. 3…).
Further, though Otaka in [0055] teaches that converted signals corresponding to readout signal and readout reset signal are in parallel supplied to as a differential signal to a column readout circuit, Otaka does not disclose:
the first reading section comprises a third capacitor (…However, Lee, in [0052-0055], teaches sampling capacitor 445a which holds a pixel output level of a pixel reset value…);
the second reading section comprises a fourth capacitor (…wherein, Lee, in [0052-0054], teaches sampling capacitor 445b which holds a pixel output level of a pixel signal level…);
a differential circuit comprising a first end and a second end, wherein the first signal is input at the first end via the third capacitor, and the second signal is input at the second end via the fourth capacitor (…Lee in [0052] teaches a differentially driven column ADC architecture, circuit 400 to include an inverting and non-inverting ends (fig. 4) which receives two pixel signals (Fig. 4); wherein a pixel output level 410 in a first operating state represents a pixel reset level and in a second operating state output level 410 represents a pixel signal level…), and
an initialization section configured to initialize the differential circuit (…wherein switches 440 (a-f) may be viewed as being partial elements of initializing circuit 400.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, that the teaching according Otaka can further be enhanced by a differential column ADC architecture as taught by Lee so to achieve lower read noise and higher dynamic range…), wherein
the photoelectric conversion section is in a first substrate (…wherein Otaka, in [0090], teaches a stacked structure forming a solid-state imaging device made of a first substrate containing pixel array; Fig. 3…),
each of the first capacitor and the second capacitor is in a second substrate (…wherein Otaka, in [0090] teaches a second substrate for the holding part array. Further, [0109] specifies the first and second substrate, containing the pixel and holding circuitries in accordance with Fig. 3; in addition, [0018] teaches a column readout circuit that may be included on the second substrate (which can may include amplifiers and analog-to-digital converters in accordance with [0098])…), and
the differential circuit is in a third substrate (…Otaka does not further teach a third substrate whereon a differential circuit is included.
Shim, however, in column 4 (lines 28-38), teaches an image sensor which, in a global shutter operation, stores a reset voltage and pixel voltage , thus to eventually perform correlated double sampling (wherein the correlated double sampling is taught in columns 3-4 (lines 60-5). Further, in column 10 (lines 31-46), teaches a logic circuit may read reference voltage from circuits 110 and 120 (see Fig. 3) through column lines COL1 and COL2. In the design of the image sensor, different stacking of substrates are taught, wherein column 18 (lines 42-50) teaches a third layer that is purposed for logic circuits 631 and 632.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that placing logic circuits on a separate substrate, as taught by Shim, may offer better light sensitivity by providing more area for light sensing by the photodiode, in addition to isolating switching noise from the output of the photodiode…).
27. Regarding claim 18, Otaka in view of Otaka-2 and Lee and further view of Shim teaches the imaging device according to claim 17 (see claim 17 above), further comprising
an auto-zero control section configured to execute an auto-zero process, wherein
the initialization section is further configured to initialize the differential circuit based on the execution of the auto-zero process (…wherein Lee, in [0054], teaches an auto-zero mode, with regards to a first and second operating states implemented through circuit 400; further, [0059], teaches that auto-zero mode takes placed when feedback loop switches are closed; thus the first and second operating states along the use of switches 440 a-f are control section which enable the auto-zero mode or the release thereof.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, that the teaching according Otaka can further be enhanced by a differential column ADC architecture as taught by Lee so to achieve lower read noise and higher dynamic range…).
Conclusion
28. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SURAFEL YILMAKASSAYE whose telephone number is (703)756-1910. The examiner can normally be reached Monday-Friday 8:30am-5:00pm.
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/SURAFEL YILMAKASSAYE/Examiner, Art Unit 2639
/TWYLER L HASKINS/Supervisory Patent Examiner, Art Unit 2639