DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I (claims 17-29) in the reply filed on 1-9-2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 17-22 and 24-28 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Karp (US 10,497,677).
[claim 17] A silicon substrate (fig. 1-3) comprising: integrated circuits located on a first surface (120, fig. 2, see also fig. 1, fig. 2 is an expanded portion of fig. 1, lines 37-65, col. 4), ; a second surface (bottom of 201 in fig. 2, active side 116 of fig. 1, lines 37-65, col. 4) opposite to the first surface; a first via (206A and/or 206D, fig. 2, 126, fig. 1); and an ESD protection element (214, fig. 2, lines 46-48, col. 4 see also the ESD circuitry for 106/108, lines 20-36, col. 4), wherein the ESD protection element is fully integrated into the silicon substrate (fig. 1,2, lines 37-65, col. 4), wherein the ESD protection element is spatially distant from the first via (fig. 2, note that 214 is spatially away from 206A and 206D), wherein the ESD protection element is connected to the first via by a first rewiring (either 208 or 206B,206C, fig. 2), and wherein the ESD protection element comprises a suppressor diode, a transistor or a thyristor (diode or transistors, lines 46-48 col. 4).
[claim 18] The silicon substrate according to claim 17, wherein the ESD protection element is configured to provide system-level ESD protection (e.g. the ESD protection circuitry helps protects the system of IC dies 106 and 108 as shown in fig. 1, lines 20-36, col. 4).
[claim 19] The silicon substrate according to claim 18, wherein several electronic components or the integrated circuits have an individual ESD protection arranged in an on-chip structure in addition to the system-level ESD protection (e.g. the ESD protection circuitry has individual components the system of IC dies 106 and 108 as shown in fig. 1, lines 20-36, col. 4).
[claim 20] The silicon substrate according to claim 17, wherein the ESD protection element is configured to provide system-level input-to-output signal protection for a plurality of electronic components and the integrated circuits (e.g. the ESD protection circuitry protects the input to output signal circuity of each of IC die 106 and 108 as shown in fig. 1, lines 20-36, col. 4).
[claim 21] The silicon substrate according to claim 17, wherein the ESD protection element additionally comprises EMI protection structures (e.g. the ESD protection element may include a capacitor which may act as a EMI protection structure, lines 46-48, col. 4 , see also applicant’s specification which uses a capacitor as an EMI device).
[claim 22] The silicon substrate according to claim 21, wherein the EMI protection structures comprise coil structures, thin film resistors and/or capacitors (capacitor may be used, lines 46-48, col. 4).
[claim 24] The silicon substrate according to claim 17, wherein the ESD protection element is in contact with a first passivation layer (the dielectric material may be disposed between the metal layers of 201, fig. 2, lines 64-65, col. 4) arranged on the first surface of the silicon substrate.
[claim 25] The silicon substrate according to claim 17, further comprising: at least one additional rewiring (vias 210 and metal layers between 208 and 212, fig. 2, where the first rewiring is 206B and/or 206C), wherein the additional rewiring electrically connects the first via to a UBM contact pad (212, fig. 2), wherein the additional rewiring comprises adjustment elements, and wherein the adjustment elements comprise capacitors, inductors or delay elements (the stacks of vias and metal layers create a delay merely by spatially separating the electrodes since it takes time pass current through the metallization layers).
[claim 26] The silicon substrate according to claim 17, further comprising: a second via ( the other of 206A/206D distinct from the first via, fig. 2, 126, fig. 1)penetrating the silicon substrate from the first surface to the second surface, wherein the ESD protection element is spatially separated from the second via (fig. 2), wherein the ESD protection element is connected to the second via a second rewiring (208, fig. 2, where the first rewiring is 206B and/or 206C), and wherein the ESD protection element forms an ESD circuit via the first via, the first rewiring, the second via and the second rewiring (fig. 2).
[claim 27] The silicon substrate comprising: a plurality of ESD circuits, each ESD circuit being the ESD circuit according to claim 26 (e.g. the ESD structure has individual ESD protection circuitry for each of IC dies 106 and 108 as shown in fig. 1, lines 20-36, col. 4).
[claim 28] The silicon substrate according to claim 17, wherein the first via is insulated from the silicon substrate by an insulation layer (dielectric material may be disposed between the metal layers/vias of 201, fig. 2, lines 64-65, col. 4).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karp (US 10,497,677) in view of Morishita (US 2005/0017306).
Karp discloses the ESD protection device of claim 17 but does not expressly disclose that the ESD protection circuit may comprise a thyristor and diode configuration.
Morishita discloses an ESD protection structure which comprises a thyristor and diode configuration [0034].
It would have been obvious to one of ordinary skill in the art before the time of filing to have used the thyristor and diode configuration in Karp’s ESD protection circuit since it has been held that simple substitution of one known element (a thyristor and diode configuration) for another (a pure diode and transistor configuration) to obtain predictable result (an ESD protection element) is obvious. KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 415-421, 82 USPQ2d 1385, 1395-97 (2007). Moreover, the usage of a thyristor diode configuration allows for the use a greater number of device configurations in the ESD protection element
With this modification Karp discloses:
[claim 23] The silicon substrate according to claim 17, wherein the ESD protection element comprises embedded structures (the ESD protection structures are embedded in the IC dies, fig. 1,2) from a combination of the thyristor and the diode structures which are not part of the thyristor (upon modification).
Claim(s) 29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Karp (US 10,497,677) in view of Gueorguiev (US 2014/0177113).
.Karp discloses the ESD protection device of claim 17 but does not expressly disclose that the integrated circuits of the ESD protection device may comprise a MEM microphone.
Gueorguiev discloses an ESD protection device whose integrated circuits comprises a MEMS microphone [Abstract].
It would have been obvious to one of ordinary skill in the art before the time of filing to have used a MEMS microphone in Karp’s integrated devices that are protected by Karp’s ESD protection circuit in order to provide ESD protection to greater variety of device of device configurations.
Conclusion
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/AMAR MOVVA/Primary Examiner, Art Unit 2898