DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/03/2023 was filed and has been considered by the examiner.
Drawings
The drawings that were filed on 05/03/2023 have been considered by the examiner.
Response to Preliminary Amendment
The Preliminary Amendment filed on 05/03/2023 has been considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Claims 1, 2, 5, 6, and 11 in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 2, 10, 11, and 12 is rejected under 35 U.S.C. 103 as being unpatentable over Gallegos et al. (US 20130221919 A1), and herein after will be referred to as Gallegos.
Regarding Claim 1, Gallegos teaches an electrical energy storage system comprising (An electrical storage system comprising battery module units, Local Module Unit (LMUs), Pack Master, and Energy Storage Master (ESM); [0029]) at least one electrical energy storage device (1) with at least one module (100) that comprises cells (101) for storing electrical energy (Traction Pack System as the energy storage device and each Battery Module Unit with prismatic cells; [0029] [0037]),
galvanic isolation means configured to provide galvanic isolation between…the at least one module (100) configured to be connected to high voltage and…the at least one module (100) configured to be connected to low voltage and/or ground (LMU cell monitoring circuitry operates at traction voltage 50-240VDC and Pack Master side operates at 5V TTL. SPI Isolation Board provides 2500V RMS galvanic isolation between them ; [0046] [0087-0089] [0120]).
Gallegos does not explicitly disclose the term internal conductive elements of the at least one module.
However, Gallegos teaches that the Local Module Unit monitors individual battery cell voltages within the Battery Module Unit ([0118-0119]). The LMU cell monitoring circuitry necessarily operates at the battery cells electrical potential traction voltage of 50-240VDC ([0087]) and is mounted directly to the Battery Module Unit making its circuitry internal conductive elements of the module ([0120] FIG. 12]. Furthermore, Gallegos teaches that the SPI Isolation Board isolates the LMU’s signal levels from the Pack Master side at 2500V RMS ([0120]) and is mounted to the LMU. The Pack Master converts power to 24-28VDC, a low voltage level relative to the 50-240VDC ([0087]) and SPI communication signals operates at 5V ([0104]). These teachings are equivalent to the claimed limitation because the circuitry directly connected to and monitoring the battery cells at traction voltage are the internal conductive elements connected to high and low voltages
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention that Gallegos SPI Isolation Board, providing galvanic solation between the LMU and Pack Master SPI communications, constitutes as the galvanic isolation means between internal conductive elements of the module connected to high and low voltages. The battery cell monitoring side is the high voltage side and the communications signal path is the low voltage side.
Regarding Claim 2, Gallegos remains as applied above in claim 1. Gallegos further teaches the electrical energy storage device (1) comprises a battery management system (BMS) comprising a master block (200) and at least one slave block (300) configured to control a state of at least one module (100) of the electrical energy storage device (1) (The Pack Master Unit is the master block and the LMU is the slave block, the LMU monitors the Pack Cells and sends voltage/temperature conditions to the Pack Master; [0086] [0118]),
wherein the battery management system (BMS) comprises an isolation board (400) provided with galvanic isolation means to provide galvanic isolation between each slave block (300) and the master block (200) (SPI Isolation Board provides galvanic isolation between the LMU and Pack Master; [0120]).
Regarding Claim 10, Gallegos remains as applied above in claim 2. Gallegos further teaches the battery management system (BMS) is configured so that the data emitted and received by the master block (200) and by each slave block (300) is structured according to the SPI communications protocol (Pack Master communicates with the LMU using Serial Peripheral Interface (SPI) bus; [0029] [0086]).
Regarding Claim 11, Gallegos remains as applied above in claim 2. Gallegos further teaches the electrical energy storage device (1) comprises galvanic isolation means between the master block (200) and a power control module (1′) (Pack Master communicates with the Energy Storage Master (ESM) and Vehicle Master Controller (VMC) via CAN bus ([0086] [0088]). The Pack Master CAN bus interface is rated at 500V continuous isolation ([0100] Table 7), and the CAN transceiver provides galvanic isolation at levels up to 2500VDC ([0046]) which constitutes galvanic isolation between the master block, Pack Master, and the power control module, Vehicle Master Controller. The Pack Master being “galvanically isolated from anything external to the pack” confirms the isolation boundary of all external controllers including the VMC ([0087])).
Regarding Claim 12, Gallegos remains as applied above in claim 2. Gallegos further teaches a DC/DC converter (2) with an electronic control unit (2′) (Pack Master converts pack power 50-240VDC to 24-28VDC; [0087]), wherein the master block (200) is connected to the electronic control unit (2′) (The Pack Master communicates with VMC via ESM using the CAN bus; [0029] [0088]).
Claim(s) 3-9 are rejected under 35 U.S.C. 103 as being unpatentable over Gallegos et al. (US 20130221919 A1), and herein after will be referred to as Gallegos, in view of Kobayashi et al. (US 20210184481 A1), and herein after will be referred to as Kobayashi.
Regarding Claim 3, Gallegos remains as applied above in claim 2. Gallegos further teaches a first internal communication bus (404) for communication with at least one slave block (300) and a second internal communication bus (405) for communication with the master block (200) (The SPI Isolation Board provides galvanic isolation between the slave side SPI bus and the master side SPI bus at 2500V RMS for 1 minute per UL1577; [00120] [0123] Table 15).
Gallegos does not explicitly teach the isolation board (400) comprises at least one transformer (406) configured to provide galvanic isolation.
However, Kobayashi discloses a battery management system where communication between the Battery Management Unit (BMU) and the cell supervising circuits (CSCs) is galvanically isolated by transformers ([0032-0033] [0023-0024] [0042] [0110]). The transformer provides galvanic isolation between the communication circuit 37 slave side and the communication circuit 11 master side via AC power line. These teachings are functionally equivalent to the claimed limitation of the isolation board comprises at least one transformer configured to provide galvanic isolation because the transformer is an insulating element that provides galvanic isolation between the two communication circuits.
Gallegos and Kobayashi are considered to be analogous to the claim invention because they are in the same field of battery management systems. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to implement the SPI Isolation Board of Gallegos using a transformer as the isolation element as taught by Kobayashi based on the motivation to use the high voltage galvanic isolation in the communication signal paths. This modification yields the predictable result of an isolation board comprising a transformer providing galvanic isolation between the slave and master communication buses.
Regarding Claim 4, Gallegos remains as applied above in claim 3. Gallegos further teaches the isolation board (400) comprises a plurality of connection lines (401) (Interface J1 and J2 and two signal lines Signal lines 2 Serial Data out and 3 Serial Data in; [0121] [0123]),
wherein each connection line (401) comprises: a first area (401 a) configured to be connected to a communications bus for communication with at least one slave block (300); and a second area (401 b) configured to be connected to a communications bus for communication with the master block (200) (SPI Isolation Board J1 and J2 as the master and slave communication bus; [0120-0121]).
Gallegos does not explicitly teach the first area (401 a) of each connection line (401) comprises the first internal bus (404) connected between a first connection port (402) and a primary circuit of the transformer (406), and wherein the second area (401 b) of each connection line (401) comprises the second internal bus (405) connected between a second connection port (403) and a secondary circuit of the transformer (406).
However, Kobayashi teaches that within each cell supervising circuit 30 (slave block), communication circuit 37 transmits cell stage of charge measured by measuring circuit 31 to BMU 10 via transformer 38 ([0032] [0026]). This signal path runs from the measuring circuit 31 through communication circuit 37 to the transformer. These teachings are equivalent to the claimed limitation of the first area of each connection line comprises the first internal bus connected between a first connection port and a primary circuit of the transformer because the communication circuit 37 is the internal bus on the first (slave) area, connecting between the slave side connection measuring circuit 31 and the primary circuit of transformer 38 and carries the cell monitoring data across the connection line. Kobayashi further teaches that the master side communication circuit 11 within BMU 10 communicates with each cell supervising circuit 30 via alternating current power line 50 and the second transformer 38 ([0023]). This signal path runs from the BMU’s communication circuit 11 through AC power line 50 to the transformer. These teachings are equivalent to the claimed limitation of the second internal bus connected between a second connection port and a secondary circuit of the transformer bcause the AC power line 50 and communication unit 11 form the internal bus on the second master area connecting between the master side connection (BMU communication circuit) and the transformer. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the SPI Isolation Board of Gallegos to incorporate the teachings of the communication circuits connecting between the first and second connection ports and transformer as taught by Kobayashi based on the motivation to provide the signal path that routes communication signals through a transformer. This modification would predictably result in an isolation board with connection lines having a first area with an internal bus between a first connection port and transformer and a second area with internal bus between a second connection port and transformer.
Regarding Claim 5, Gallegos remains as applied above in claim 3. Gallegos does not explicitly teach the isolation board (400) comprises galvanic isolation means between the first areas (401 a) of each connection line (401).
However, Kobayashi teaches that each cell supervising circuit has a “one-to-one correspondence with secondary battery cells” ([0026]), meaning each CSC operates independently with its own dedicated transformer and measuring circuit. Each CSC’s communication circuit transmits cell state information to the BMU via its own transformer ([0032]) and AC power is fed across the galvanic isolation boundary to each CSC individually ([0024). This teaching is equivalent to the claimed limitation of galvanic isolation means between the first area because each CSC’s circuitry is dedicated to a single cell and connects to the shared AC power line through its own individual transformer. The individual transformers provide galvanic isolation between the first areas of each connection line as taught by “galvanic isolation boundary” ([0024]). It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify Gallegos to incorporate the individual transformers per block as taught by Kobayashi based on the motivation to provide galvanic isolation between each block’s circuitry using the established transformer-based isolation. This modification would predictably result in galvanic isolation between the first areas of each connection line via individual transformers.
Regarding Claim 6, Gallegos remains as applied above in claim 4. Gallegos does not explicitly teach the isolation board (400) comprises galvanic isolation means between the second areas (401 b) of each connection line (401).
However, Kobayashi teaches that the BMU communicates with each CSC via alternating current power line ([0023]) and that each CSC connects to the shared AC power line through its own transformer ([0033]). The AC power is fed from the BMU to each CSC “across the galvanic isolation boundary” ([0024]) which means that each transformer forms a distinct galvanic isolated master side circuit. This teaching is equivalent to the claimed limitation because each CSC communication circuit connects to the share power line via transformer, each transformer being a separate insulating element ([0033]). The windings of the individual transformers are galvanically isolated from one another by virtue of being separate transformer elements, each transformer having its own primary and secondary windings (FIG. 1). It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify Gallegos to incorporate the individual transformer elements for each connection as taught by Kobayashi based on the motivation to provide galvanic isolation on the primary master side of each connection line using the transformer located at each CSC. This modification would predictably result in galvanic isolation between the second areas of each connection line via individual transformer.
Regarding Claim 7, Gallegos remains as applied above in claim 5. Gallegos does not explicitly teach the galvanic isolation means between the first areas (401 a) and/or the second areas (401 b) of each connection line (401) comprise a separation strip with electrically insulating material.
However, Kobayashi teaches that the transformers are an “insulating element which enables measuring circuit to receive power supply in a non-contact manner” ([0033]). Furthermore, the transformer is identified as the insulating element of the system that is “exemplified as the insulating element…the insulating element may be another insulating element such as an electromagnetic resonance coupler” ([0119]). The transformer’s physical insulating barrier, the dielectric between the windings, is the component that provides the non-contact power transfer and galvanic isolation (FIG. 1). These teachings are equivalent to the claimed limitation because the transformer comprises a physical insulating barrier between the windings that separates the two conductive circuits sides. The winding insulation is a strip of electrically insulating material that physically separates the primary and secondary side conductors within the transformer structure. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify Gallegos to incorporate the teachings of a transformer as the insulating element as taught by Kobayashi based on the motivation to use the insulating element for achieving galvanic isolation in the communication signal paths. This modification would predictably result in galvanic isolation means comprising a separation strip with electrical insulating material, the transformer winding insulation, between the first and/or second areas of each connection line.
Regarding Claim 8, Gallegos remains as applied above in claim 2. Gallegos further teaches the master block (200) comprises a microcontroller (201), one or more communication centers (205) for communication with the slave blocks (300) (Pack Master Unit comprises a microcontroller utilizing a JTAG programming interface to communicate to the LMUs via SPI; ([0086]).
Gallegos does not explicitly teach one or more transformer substations (206) configured to provide galvanic isolation between a circuit in contact with the microcontroller (201) and a communications circuit that exits the master block (200) towards the slave blocks (300).
However, Kobayashi teaches that the BMU includes communication circuits, alternating current power supply, control microcomputer, and transformer ([0022]). The transformer physically resides inside the BMU and is positioned between the microcontroller and the alternating current power line used in communication with the BMU and CSC ([0023]). It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify Gallegos to incorporate the teachings of a transformer inside the BMU between the microcontroller and the outbound communication circuit as taught by Kobayashi based on the motivation to achieve galvanic isolation between the microcontroller circuit and the output communication circuit. This modification would predictably result in a master block containing transformer substations providing galvanic isolation between the microcontroller and the communication circuit exiting towards the slave blocks.
Regarding Claim 9, Gallegos remains as applied above in claim 2. Gallegos further teaches each slave block (300) comprises a monitoring unit (301) configured to monitor the status of a plurality of cells (301) of the module (100) (The LTC6802-2 data acquisition IC in the LMU monitors cell voltages; [0118-0119]), and
a communication unit (305) configured for communication with the master block (200) through at least one communication port (307) (The Pack Master Unit communicates with LMUs via SPI; [0086] [0121-123]).
Gallegos does not explicitly teach wherein the slave block (300) comprises a transformer unit (306) configured to provide galvanic isolation between the monitoring unit (301) and the at least one communication port (307).
However, Kobayashi teaches that each CSC includes “measuring circuit 31, communication circuit 37, transformer 38, converting circuit 39, clock generating circuit 40, and charging circuit 41.” ([0026]). The communication circuit transmits cell state-of-charge information measure by the measuring circuit to the BMU via transformer ([0032]) where the transformer is an insulating element physically inside each CSC ([0033] [0110]). These teachings are equivalent to the claimed limitation because the transformer resides in each CSC (slave block), positioned between the measuring circuit and the communication circuit /AC power line, providing galvanic isolation between the monitoring function and the communication function within the slave block. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify Gallegos to incorporate the teachings of a transformer inside each slave block between the monitoring circuit and the communication port as taught by Kobayashi based on the motivation to provide galvanic isolation between the cell monitoring function and the communication function within each slave block. This modification would predictably result in each slave block containing a transformer providing galvanic isolation between the monitoring unit and the communication port.
Claim(s) 13, 16, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Gallegos et al. (US 20130221919 A1), and herein after will be referred to as Gallegos, in view of Srinivasan et al. (US 20150228953 A1), and herein after will be referred to as Srinivasan.
Regarding Claim 13, Gallegos remains as applied above in claim 1. Gallegos does not explicitly teach spacers (102) configured to guarantee a minimum galvanic isolation distance between terminals (103) to which there are connected cells of the module (100) and other conductive components configured to be connected to ground potential.
However, Srinivasan discloses battery cell spacer within battery modules specifically configured to provide electrical isolation distances between cells and surrounding modules. Srinivasan teaches a battery cell space as a single piece unitary or molded part with a plurality of walls, dividing walls, and end walls ([0044-0045]). The spacer includes flaps that fold perpendicular under the battery cells to increase the electrical isolation and creepage distance ([0054-0055]) establishing that the spacer is designed to guarantee a minimum galvanic isolation distance between cell components and the surrounding module structures. These teachings are equivalent to the claimed limitation because the spacer is designed to increase electrical isolation and creepage distance which necessarily provides galvanic isolation distances between cell terminals and ground potential conductive components within the module.
Gallegos and Srinivasan are considered to be analogous to the claim invention because they are in the same field of battery modules for EVs and they pertain to address the same problem of electrical isolation within battery module components. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to modify the battery modules of Gallegos to incorporate the teachings of the battery cell spacers as taught by Srinivasan based on the motivation to provide galvanic isolation distance between the cell terminals and the ground potential module components. This modification would predictably result in battery modules having insulating spacers configured to guarantee a minimum galvanic isolation distances.
Regarding Claim 16, Gallegos remains as applied above in claim 1. Gallegos does not explicitly teach an isolation plug (107) on the front part and rear part thereof, wherein said plugs (107) are configured to guarantee a creepage, greater than a predetermined threshold, between terminals (103) and casing (106) of the module (100).
However, Srinivasan teaches an array structure is positioned at one or both ends of the battery cell spacer and the array structures are molded as part of the unitary battery cell spacer ([0059]) that is a single-piece, unitary or molded part made of insulating material, flaps folding perpendicular, designed to increase electrical isolation and creepage distance ([0043] [0055]). The array structures are discrete insulating element at the ends of the module, positioned where cell terminals interfaces with the module casing. These teachings are equivalent to the claimed limitation because the array structures are discrete insulating elements positioned at one or both ends of the battery module ([0059]), made of insulating material ([0043]), and positioned where the cell terminals interface with the module casing. Furthermore, the specification of the application discloses isolation plugs as insulating components on the front and rear parts of the module configured to guarantee creepage between terminals and casing (Page 11). The array structures taught in Srinivasan are structurally equivalent. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the battery modules of Gallegos to incorporate the teachings of the insulating array structures positioned at the ends of the modules as taught by Srinivasan based on the motivation to provide electrical isolation at the modules extremities where cell terminals can be exposed to the modules casing. This modification would predictably result in isolation plugs on the front and rear parts of each module guaranteeing creepage between terminals and casings.
Regarding Claim 17, Gallegos remains as applied above in claim 1. Gallegos does not explicitly teach corner pieces (108) made of insulating material to separate the cells (101) with respect to conductive areas.
However, Srinivasan teaches a battery cell spacer with end walls that connect adjacent dividing walls at the transitions between cell rows, the corner of the cell array, where they form an insulating boundary between outermost cells and the module casings ([0044] [FIG. 2] [FIG. 3]). The array structures are molded as part of the battery cell spacer positioned at the corners of the cell arrangement ([0059]). These teachings are equivalent to the claimed limitation because the end walls are located at the transitions between the rows (corners of the cell array), that forms an insulating boundary. Furthermore, the specification of the application discloses corner pieces as insulating components that separate cells from conductive areas at the module corners (Page 11). It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the battery modules of Gallegos to incorporate the insulating corner elements as taught by Srinivasan based on the motivation to separate cells from the conductive areas at the corners of the cell arrangement. This modification would predictably result in corner pieces made of insulating material separating cells from conductive areas.
Claim(s) 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Gallegos et al. in view of Srinivasan, as applied in claim 13, and in further view of Moon et al. (US 20140044995 A1), and herein after will be referred to as Moon.
Regarding Claim 14, Gallegos and Srinivasan remains as applied above in claim 13. Gallegos further teaches a cold plate (104) located between the two parallel rows of cells (101) (Module housing provides cooling and is accomplished by aluminum heat sinks; [0134]).
Gallegos does not explicitly teach guarantee a creepage, greater than a predetermined threshold, between the terminals (103) of the module (100), and a cold plate (104) and a clearance, greater than another predetermined threshold, between the terminals (103) and a cover (105).
However, Srinivasan teaches that the battery cell spacer is a single-piece, unitary or molded part made of insulating material, flaps folding perpendicular, designed to increase electrical isolation and creepage distance ([0043] [0055]). The space further provides a dimension D1 that is greater than the width of the battery cells that provides clearance ([0058]), establishing creepage and clearance between cell terminals and surrounding module structures. These teachings are equivalent to the claimed limitations because the insulating spacer with creepage, increasing flaps and clearance, providing dimensions D1 serves the identical function of maintaining predetermined minimum isolation distances between cell terminals and adjacent conductive/enclosure surfaces within the battery module. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the battery modules of Gallegos to incorporate the teachings of insulating spacers with creepage and clearance guarantees as taught by Srinivasan based on the motivation to increase the electrical isolation and creepage distance and would predictably result in spacers guaranteeing minimum creepage and clearance distances between terminals and surrounding conductive structures within the module.
Gallegos and Srinivasan does not explicitly teach a first variant (102 a) of the spacer (102) comprising a T-shaped geometry, wherein this first variant (102 a) is configured to be arranged between two parallel rows of cells (101), wherein an upper branch of the “T” is arranged on the cells (101) and a lower branch of the “T” is arranged between the cells (101) of both rows.
However, Moon discloses battery cell spacers with a blocking unit that extend in the left and right direction so that the spacer may be T-shaped as a whole ([0049]). The blocking unit contacts rear surfaces of the battery cells located at both sides of the spacer ([0050]), positioning the T-shaped spacer between two adjected rows of battery cells. The spacers are made of insulation material such as plastic ([0043]), and the blocking unit contacts both the rear surfaces of battery cells on both sides “an inner surface of the lower case” ([0044]). These teachings are equivalent to the claimed limitation because the spacer is explicitly stated as a T-shaped as a whole and is arranged between two rows of cells with cells on both sides as shown in FIG. 4 and FIG. 5.
Gallegos, Srinivasan, and Moon are considered to be analogous to the claim invention because they are in the same field of battery pack design and pertain to the same issue of electrically insulating battery cells. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Gallegos and Srinivasan to incorporate the T-shaped spacers as taught by Moon based on the motivation to provide an insulating spacer that contacts rear surfaces of battery cells on both sides of the spacer, thereby maximizing the insulating contact area between neighboring cell rows. This modification would predictably result in a T-shaped spacer between two parallel cell rows guaranteeing creepage and clearance.
Regarding Claim 15, Gallegos and Srinivasan remains as applied above in claim 13. Gallegos further teaches a cold plate (104) located on each side of the module (100), between the casing (106) of the module (100) and the cells (Battery module with cells, module casing, and conductive thermal aluminum heat sinks positioned on each side of the module between the casing and cells; [0037] [0134]).
Gallegos does not explicitly teach the spacer (102) makes it possible to guarantee a creepage, greater than a predetermined threshold, between terminals (103) and the cold plate (104) located on each side of the module (100), as well as a clearance, greater than another predetermined threshold, between terminals (103) and cover (105) of the module (100).
However, Srinivasan teaches that the battery cell spacer is a single-piece, unitary or molded part made of insulating material, flaps folding perpendicular, designed to increase electrical isolation and creepage distance ([0043] [0055]). The space further provides a dimension D1 that is greater than the width of the battery cells that provides clearance ([0058]), establishing creepage and clearance between cell terminals and surrounding module structures. These teachings are equivalent to the claimed limitations because the insulating spacer with creepage, increasing flaps and clearance, providing dimensions D1 serves the identical function of maintaining predetermined minimum isolation distances between cell terminals and adjacent conductive/enclosure surfaces within the battery module. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the battery modules of Gallegos to incorporate the teachings of insulating spacers with creepage and clearance guarantees as taught by Srinivasan based on the motivation to increase the electrical isolation and creepage distance and would predictably result in spacers guaranteeing minimum creepage and clearance distances between terminals and surrounding conductive structures within the module.
Gallegos and Srinivasan does not explicitly teach the second variant (102 b) of the spacer comprising a gamma-shaped geometry, configured to be arranged between a casing (106) of the module (100) and the cells (101), wherein an upper branch of the “gamma” is arranged on the cells (101) and a lower branch of the “gamma” is arranged on a cold plate.
However, Moon teaches a spacer variant with a blocking unit that is “perpendicular to a length direction of the spacer while extending only in one direction” ([0051]), making the spacer “L-shaped as a whole” ([0055]) and made of “insulation material such as plastic” ([0043]). These teachings are equivalent to the claimed limitation of a second variant of the space comprising a gamma-shaped geometry because the gamma shape comprises a vertical member with a single horizontal extension at one end that is identical to an L-shape when rotated. Moon further teaches that the blocking units contacts “backs surfaces of the battery cells” on one surface and “contact an inner surface of the lower case” ([0044]), which positions the spacer between the cells and module casing (FIG. 1). The blocking unit of the spacer may contact the rear surface of the battery cells located at one side of the spacer ([0051]). This teaching is equivalent to the claimed limitation of “configured to be arranged between a casing of the module and the cells, wherein an upper branch of the “gamma” is arranged on the cells and a lower branch of the “gamma” is arranged on a cold plate.” because the spacer is physically positioned between the battery cells which contacts the back surfaces of the cells and inner surface of the lower case. The elongate spacer body contacts the rear surface of the battery cell and the blocking unit extends perpendicular in one direction contacting the inner surface of the lower case as the cold plate side. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the spacers of Gallegos and Srinivasan to incorporate the teachings of an L-shaped spacer geometry as taught by Moon based on the motivation to provide an insulating spacer that contracts the rear surface of a battery cell and the inner surface of the module casing, thereby maintaining isolation between cell terminals and the conductive case. Moon’s teaching of both the T-shaped and L-shaped spacers ([0049] [0055]) for the same battery pack, confirms that selecting an L-shaped variant for the casing side position is a predictable design choice.
Prior Art
The prior art made of record and not relied upon is considered pertinent, most relevant, to applicant's disclosure.
Sekizaki (US 20130234719 A1)
Kim (US 20160211493 A1)
Song (US 20190129369 A1)
Fishman (US 20190372361 A1)
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD ANDREW IZON DIZON whose telephone number is (571)272-4834. The examiner can normally be reached M-F 9AM-5PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Angela Ortiz can be reached at (571) 272-1206. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/EDWARD ANDREW IZON DIZON/Examiner, Art Unit 3663
/ANGELA Y ORTIZ/Supervisory Patent Examiner, Art Unit 3663
Prosecution Insights