Prosecution Insights
Last updated: April 19, 2026
Application No. 18/252,161

DATA RECEIVING APPARATUS TO ADJUST PHASE OF CLOCK SIGNAL

Final Rejection §102
Filed
May 08, 2023
Examiner
PATEL, CHANDRAHAS B
Art Unit
2464
Tech Center
2400 — Computer Networks
Assignee
Sony Semiconductor Solutions Corporation
OA Round
2 (Final)
88%
Grant Probability
Favorable
3-4
OA Rounds
2y 8m
To Grant
95%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
780 granted / 885 resolved
+30.1% vs TC avg
Moderate +7% lift
Without
With
+7.3%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
33 currently pending
Career history
918
Total Applications
across all art units

Statute-Specific Performance

§101
7.1%
-32.9% vs TC avg
§103
37.5%
-2.5% vs TC avg
§102
44.6%
+4.6% vs TC avg
§112
5.0%
-35.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 885 resolved cases

Office Action

§102
DETAILED ACTION Response to Arguments Applicant's arguments filed 9/22/2025 have been fully considered. Applicant argues that amended claims are not taught by Dally reference. Amended claims are discussed below in the office action. Claim Rejections - 35 USC § 102 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dally (USPN 7,627,069). Regarding claim 1, Dally teaches a data receiving apparatus comprising: a plurality of data signal lines configured to receive first data signals [Fig. 2a, plurality of data signals 110a-d]; a clock signal line configured to receive a clock signal [Fig. 2a, clock signals coming from the clock generator 112]; a first phase adjustment circuit configured to: perform a phase adjustment between the first data signals [Col. 2, lines 54-63, performs phase adjustment between multiple data signals]; and generate second data signals based on the phase adjustment between the first data signals, wherein a phase shift of each of the second data signals is less than or equal to a threshold value, and the second data signals are different from the first data signals [Col. 7, line 40 – Col. 8, line 14, phase shift of the signal is limited to an extent due to physical signal limitations]; and a second phase adjustment circuit configured to perform a phase adjustment of the clock signal with respect to the second data signals [Col. 3, lines 23-40, phase adjustment of clock is done based on the phase adjustment of the data signals]. Regarding claim 2, Dally teaches the second phase adjustment circuit is further configured to perform the phase adjustment of the clock signal with respect to the second data signals based on one of the second data signals [Col. 3, lines 23-40]. Regarding claim 3, Dally teaches the first phase adjustment circuit is further configured to: perform a logical operation on the each of the second data signals [Col. 3, lines 23-45]; and generate a specific signal based on the performed logical operation on the each of the second data signals, and the second phase adjustment circuit is further configured to perform the phase adjustment of the clock signal with respect to the second data signals based on the generated specific signal [Fig. 2a]. Regarding claim 4, Dally teaches the first phase adjustment circuit includes: a first delay circuit configured to: delay each of the first data signals to generate third data signals, wherein the third data signals are different from the first data signals and the second data signals [Col. 3, lines 46-63]; output the third data signals [Col. 3, lines 46-63]; and a phase comparator configured to perform a phase comparison between the third data signals [Col. 3, lines 46-63]. Regarding claim 5, Dally teaches the phase comparator is further configured to generate a specific signal based on the phase comparison between the third data signals, the first phase adjustment circuit further includes a first delay amount control circuit configured to control, based on the specific signal, an amount of delay of the each of the first data signals, and the first delay circuit is further configured to delay the each of the first data signals by the amount of delay [Col. 3, lines 46-63]. Allowable Subject Matter Claims 6-9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHANDRAHAS PATEL whose telephone number is (571)270-1211. The examiner can normally be reached Monday - Thursday 7:30 - 17:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ricky Ngo can be reached at 571-272-3139. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Chandrahas B Patel/ Primary Examiner, Art Unit 2464
Read full office action

Prosecution Timeline

May 08, 2023
Application Filed
Jun 30, 2025
Non-Final Rejection — §102
Sep 22, 2025
Response Filed
Nov 12, 2025
Final Rejection — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
88%
Grant Probability
95%
With Interview (+7.3%)
2y 8m
Median Time to Grant
Moderate
PTA Risk
Based on 885 resolved cases by this examiner. Grant probability derived from career allow rate.

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