CTFR 18/252,276 CTFR 90261 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Response to Arguments Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Applicant also argues that 20 and 60 are placed on different semiconductor chips. Examiner disagrees as what is called semiconductor chip is not defined as single layer substrate , and in addition even if we accept that it is correct simple modification of placing electronics of the 200 on 300 as additional element is just displacement of the position of the parts. For example 300 shows ADC , NVM and I/O, adding additionally Logic circuit to it will bot be difficult to one of ordinary skills in the art. Also in addition [0079] teaches that adding third layer is just in order to decrease the size and if size does not matter again it is just simple modification. Also Fig. 2 shows 2 layer stack. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1 is/are rejected under 35 U.S.C. 103 as being unpatentable over D1 US 20190363130 A1 . Regarding claims bellow D1 teaches 1.(Currently Amended) A light reception device, comprising: a stacked chip structure(fig. 7 and fig. 6) in which at least two semiconductor chips(100 and 200+300) including a first semiconductor chip(100) and a second semiconductor chip(200+300) are stacked a plurality of pixels(110) in an array on the first semiconductor chip(fig. 6), wherein each of the plurality of pixels includes a light-receiving element [0035] a readout circuit(300) in a first region of the second semiconductor chip(200+300), wherein the readout circuit is configured to read a signal outputted by [a pixel of the plurality of pixels(ADC , IO performs readout), the readout circuit includes a (three-dimensional) transistor(60), and the first region is directly below the pixel;(fig. 6 300 is bellow 110 and 100)and a circuit in a second region(200) of the second semiconductor chip(200+300), wherein the circuit includes two-dimensional transistor(20)[0041],and the second region is different from the first region.(fig. 6) It is important to note that D1 does not explicitly say transistor 60 is three-dimensional but rather say in [0098] that other configuration of transistors can be made, at the same time paragraph [0049] explicitly teaches that transistor can be three-dimensional as well as planar. And therefore It will be obvious to one of ordinary skills in the art to modify teachings taught by D1 to use other type of the transistors as the choice of the transistors is obvious replacement of the parts which in art considered complete alternatives of each other . [Claim 4] The light reception device according to claim 1, wherein the three-dimensional transistor comprises a Fin field-effect transistor. [0064] [Claim 5] The light reception device according to claim 1, wherein the two-dimensional transistor comprises a planar transistor.[0041] [Claim 6] The light reception device according to claim 1, wherein the circuit comprises a high-voltage circuit that needs a voltage exceeding an allowable voltage of the three-dimensional transistor.[0065] [Claim 7] The light reception device according to claim 6, wherein the high-voltage circuit comprises a voltage generation circuit that generates a voltage for the light-receiving element.[0065] [Claim 10] The light reception device according to claim 1, wherein, in a three-layer stacked chip structure in which the first semiconductor chip, the second semiconductor chip, and a third semiconductor chip are stacked, a desired signal processor is formed on the third semiconductor chip. (fig. 7) [Claim 11] The light reception device according to claim 10, wherein the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are stacked in this order from top.(fig. 7) Regarding claim 13, 15 D1 teaches layers of the semiconductor chip 100, 200, 300 [Claim 13] The light reception device according to claim 10, wherein the third semiconductor chip (499)is disposed between the first semiconductor chip and the second semiconductor chip. 15 (Currently Amended) The light reception device according to claim [[13]]10, wherein the first semiconductor chip(100) is in a first layer of the three-layer stacked chip structure(fig. 10 (100+400+300+200)), the second semiconductor chip is in a second layer of the three-layer stacked chip structure, and the second semiconductor chip includes a wiring layer on a side of the first semiconductor chip(fig. 11 with fig. 1) [0084] Although D1 does not explicitly shows 100+400+300+200 configuration adding analog circuit to the 100 It will be obvious to one of ordinary skills in the art to modify teachings taught by D1 with teachings by embodiment in fig. 10 in order to include communication platform with platforms 300 and 200[0084] 07-21-aia AIA Claim (s) 2, 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over D1 in view of D01 US 20160353084 A1 . Regarding claims 2, 3 D1 teaches image sensor and is not concerned with type of the image sensor But does not explicitly teach while D01 [Claim 2] The light reception device according to claim 1, wherein the light-receiving element includes an avalanche photodiode that operates in a Geiger mode.[0018] [Claim 3] The light reception device according to claim 2, wherein the light-receiving element includes a single-photon avalanche diode.[0018] Although D1 does not teach claims 2 and 3 it is just the matter of obvious modification in order to detect the light of desired intensity , for example APD in Geiger or spad mode can produce fast electrical pulse even with single photon. It will be obvious to one of ordinary skills in the art to modify teachings taught by D1 with teachings by D01 in order to produce a pulse of the same amplitude when struck by a photon[0018] 07-21-aia AIA Claim (s) 17, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over D2 US 20210325244 A1 in view of D1 . Regarding claims bellow D2 teaches [Claim 17] A distance measuring device comprising(title) a light source section(21) that emits light toward a distance measurement target(12); and a light reception device(41) that receives reflected light from the distance measurement target on a basis of the light emitted from the light source section, the light reception device including image sensor array[0002] but does not explicitly teach while D1 teaches a stacked chip structure(fig. 7 and fig. 6) in which at least two semiconductor chips(100 and 200+300) including a first semiconductor chip(100) and a second semiconductor chip(200+300) are stacked a plurality of pixels(110) in an array on the first semiconductor chip(fig. 6), wherein each of the plurality of pixels includes a light-receiving element [0035] a readout circuit(300) in a first region of the second semiconductor chip(200+300), wherein the readout circuit is configured to read a signal outputted by [a pixel of the plurality of pixels(ADC , IO performs readout), the readout circuit includes a (three-dimensional) transistor(60), and the first region is directly below the pixel;(fig. 6 300 is bellow 110 and 100)and a circuit in a second region(200) of the second semiconductor chip(200+300), wherein the circuit includes two-dimensional transistor(20)[0041],and the second region is different from the first region.(fig. 6) It is important to note that D1 does not explicitly say transistor 60 is three-dimensional but rather say in [0098] that other configuration of transistors can be made, at the same time paragraph [0049] explicitly teaches that transistor can be three-dimensional as well as planar. And therefore It will be obvious to one of ordinary skills in the art to modify teachings taught by D1 to use other type of the transistors as the choice of the transistors is obvious replacement of the parts which in art considered complete alternatives of each other . [Claim 18] The distance measuring device according to claim 17, wherein distance measurement is performed by a ToF method of measuring a time until the light emitted from the light source section toward the distance measurement target returns by being reflected by the distance measurement target.(D1 [0002]) 07-21-aia AIA Claim (s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over D1 in view of D2 . Regarding claim 8 D1 teaches high-voltage circuit but does not teach while D2 teaches a laser driver that drives a laser light source that emits laser light to be received by the light-receiving element.(fig. 1 implicit as laser source is driven) It would be obvious to one of ordinary skills in the art at the time of filing to modify teachings by D1 with teaching by D2 in order to use single high voltage device for powering receivers and transmitters in LIDAR device . 07-21-aia AIA Claim (s) 9, 12, 14, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over D1 in view of D3 WO/2020/170841(translation of CN 113287204 A as reference) . Regarding claim 9 D1 teaches but wherein, in a two-layer stacked chip structure in which the first semiconductor chip and the second semiconductor chip are stacked,(fig. 2-7) [Claim 12, 14] The light reception device according to claim 11, wherein the first semiconductor chip in a first layer and the second semiconductor chip in a second layer are electrically coupled by a silicon through electrode, and(fig. 7 bonding between 100 and 300 layer 12 [0068]) does not teach while D3 teaches the first semiconductor chip and the second semiconductor chip are electrically coupled by a junction section including a Cu-Cu direct junction or a bump ball, or a silicon through electrode.(page 10, 11) the second semiconductor chip in the second layer and the third semiconductor chip in a third layer are electrically coupled by a junction section including a Cu-Cu direct junction.(page 10, 11) or a bump ball. It would be obvious to one of ordinary skills in the art at the time of filing to modify teachings by D1 with teaching by D3 in order to provide bonding between two stacked structures. Combination of D1 and D2 teaches different bonding mechanisms(page 10, 11) but does not explicitly say [Claim 16] The light reception device according to claim 15, wherein the first semiconductor chip in a first layer and the second semiconductor chip in the second layer are electrically coupled by a junction section including a Cu-Cu direct junction or a bump ball, and the second semiconductor chip in the second layer and the third semiconductor chip in a third layer are electrically coupled by a silicon through electrode. Claim 16 is Obvious modification of claims 12, 14 and can be considered simple design choice of using different bonding mechanisms between the layers. It would be obvious to one of ordinary skills in the art at the time of filing to modify teachings by D1 and D2 in order to provide desired bonding between layers and conduct the current or signal. Conclusion 07-40 AIA Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL . See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to HOVHANNES BAGHDASARYAN whose telephone number is (571)272-7845. The examiner can normally be reached Mon-Fri 7am - 5 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yuqing Xiao can be reached at (571) 270-3603. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /HOVHANNES BAGHDASARYAN/Examiner, Art Unit 3645 Application/Control Number: 18/252,276 Page 2 Art Unit: 3645 Application/Control Number: 18/252,276 Page 3 Art Unit: 3645 Application/Control Number: 18/252,276 Page 4 Art Unit: 3645 Application/Control Number: 18/252,276 Page 5 Art Unit: 3645 Application/Control Number: 18/252,276 Page 6 Art Unit: 3645 Application/Control Number: 18/252,276 Page 7 Art Unit: 3645
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