DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 15 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Limitations “wherein the second semiconductor chip in a second layer has a configuration in which a top-bottom relationship is inverted” Are unclear, it is unclear what is the second layer, and what is considered top-bottom relationship inverted.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and claims bellow are rejected under 35 U.S.C. 102(a)(1) as being anticipated by D1 US 20190363130 A1.
Regarding claims bellow D1 teaches
[Claim 1] A light reception device comprising:
a stacked chip structure(fig. 1) in which at least two semiconductor chips(100+200) including a first semiconductor chip(100) and a second semiconductor chip(210) are stacked,(fig. 2) wherein
on the first semiconductor chip(100), pixels each including a light-receiving element are formed in an array, and[0003]
on the second semiconductor chip(210 or 300), a readout circuit that reads a signal to be outputted by the pixel is formed with use of a three-dimensional transistor[0037],[0063],[0064], and
a circuit using a two-dimensional transistor(20)[0041] is formed in a region other than a region where the readout circuit is formed.(fig. 7)
[Claim 4] The light reception device according to claim 1, wherein the three-dimensional transistor comprises a Fin field-effect transistor. [0064]
[Claim 5] The light reception device according to claim 1, wherein the two-dimensional transistor comprises a planar transistor.[0041]
[Claim 6] The light reception device according to claim 1, wherein the circuit using the two-dimensional transistor comprises a high-voltage circuit that needs a voltage exceeding an allowable voltage of the three-dimensional transistor.[0065]
[Claim 7] The light reception device according to claim 6, wherein the high-voltage circuit comprises a voltage generation circuit that generates a voltage for the light-receiving element.[0065]
[Claim 10] The light reception device according to claim 1, wherein, in a three-layer stacked chip structure in which the first semiconductor chip, the second semiconductor chip, and a third semiconductor chip are stacked, a desired signal processor is formed on the third semiconductor chip. (fig. 7)
[Claim 11] The light reception device according to claim 10, wherein the first semiconductor chip, the second semiconductor chip, and the third semiconductor chip are stacked in this order from top.(fig. 7)
[Claim 13] The light reception device according to claim 10, wherein the third semiconductor chip is disposed between the first semiconductor chip and the second semiconductor chip.(depending on what you call first second and third fig. 7 reads on it)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over D1.
Regarding claims 2, 3 D1 teaches image sensor and is not concerned with type of the image sensor
But does not explicitly teach
[Claim 2] The light reception device according to claim 1, wherein the light-receiving element includes an avalanche photodiode that operates in a Geiger mode.
[Claim 3] The light reception device according to claim 2, wherein the light-receiving element includes a single-photon avalanche diode.
Although D1 does not teach claims 2 and 3 it is just the matter of obvious modification in order to detect the light of desired intensity , for example APD in Geiger or spad mode can produce fast electrical pulse even with single photon.
Claim(s) 17, 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over D2 US 20210325244 A1 in view of D1.
Regarding claims bellow D2 teaches
[Claim 17] A distance measuring device comprising(title)
a light source section(21) that emits light toward a distance measurement target(12); and
a light reception device(41) that receives reflected light from the distance measurement target on a basis of the light emitted from the light source section,
the light reception device including
image sensor array[0002]
but does not explicitly teach while D1 teaches
a stacked chip structure in which at least two semiconductor chips including a first semiconductor chip and a second semiconductor chip are stacked, wherein
on the first semiconductor chip, a pixel array section in which pixels each including a light-receiving element are disposed is formed, and
on the second semiconductor chip, a readout circuit that reads a signal to be outputted by the pixel is formed with use of a three-dimensional transistor, and a circuit using a two-dimensional transistor is formed in a region around a region where the readout circuit is formed.(see rejection of claim 1 )
It would be obvious to one of ordinary skills in the art at the time of filing to modify teachings by D2 with teaching by D1 in order to provide compact image sensor for lidar device as required in D1.
[Claim 18] The distance measuring device according to claim 17, wherein distance measurement is performed by a ToF method of measuring a time until the light emitted from the light source section toward the distance measurement target returns by being reflected by the distance measurement target.(D1 [0002])
Claim(s) 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over D1 in view of D2.
Regarding claim 8 D1 teaches
high-voltage circuit
but does not teach while D2 teaches
a laser driver that drives a laser light source that emits laser light to be received by the light-receiving element.(fig. 1 implicit as laser source is driven)
It would be obvious to one of ordinary skills in the art at the time of filing to modify teachings by D1 with teaching by D2 in order to use single high voltage device for powering receivers and transmitters in LIDAR device.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over D1 in view of D3 WO/2020/170841(translation of CN 113287204 A as reference).
Regarding claim 9 D1 teaches but
wherein, in a two-layer stacked chip structure in which the first semiconductor chip and the second semiconductor chip are stacked,(fig. 2-7)
[Claim 12, 14] The light reception device according to claim 11, wherein
the first semiconductor chip in a first layer and the second semiconductor chip in a second layer are electrically coupled by a silicon through electrode, and(fig. 7 bonding between 100 and 300 layer 12 [0068])
does not teach while D3 teaches
the first semiconductor chip and the second semiconductor chip are electrically coupled by a junction section including a Cu-Cu direct junction or a bump ball, or a silicon through electrode.(page 10, 11)
the second semiconductor chip in the second layer and the third semiconductor chip in a third layer are electrically coupled by a junction section including a Cu-Cu direct junction.(page 10, 11)
or a bump ball.
It would be obvious to one of ordinary skills in the art at the time of filing to modify teachings by D1 with teaching by D3 in order to provide bonding between two stacked structures.
Combination of D1 and D2 teaches different bonding mechanisms but does not explicitly say
[Claim 16] The light reception device according to claim 15, wherein
the first semiconductor chip in a first layer and the second semiconductor chip in the second layer are electrically coupled by a junction section including a Cu-Cu direct junction or a bump ball, and
the second semiconductor chip in the second layer and the third semiconductor chip in a third layer are electrically coupled by a silicon through electrode.
Claim 16 is Obvious modification of claims 12, 14 and can be considered simple design choice of using different bonding mechanisms between the layers.
It would be obvious to one of ordinary skills in the art at the time of filing to modify teachings by D1 and D2 in order to provide desired bonding between layers.
Conclusion
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/HOVHANNES BAGHDASARYAN/Examiner, Art Unit 3645