DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed January 27, 2026 has been entered. Claims 1-18 remain pending in the application. Applicant’s amendments to the specification, drawings, and claims have overcome each and every objection and 35 U.S.C. § 112 rejection previously presented in the Non-Final Office Action mailed October 29, 2025.
Response to Arguments
Applicant’s arguments, see pages 8-10, filed January 27, 2026, with respect to the rejections of claims 1-18 under 35 U.S.C. § 102 and § 103 have been fully considered and are persuasive. Therefore, the rejections have been withdrawn. However, upon further consideration, a new grounds of rejection is made in view of newly found prior art references Gebeyehu et al. (Patent Publication Number TW 2017/22069 A), hereafter referred to as Gebeyehu, and Takagi (Patent Publication Number US 2018/0109245 A1), hereafter referred to as Takagi.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2, 7, 9-14, 16, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Khlat et al. (Patent Number US 9,379,667 B2), as cited by applicant, hereafter referred to as Khlat, in view of Gebeyehu and Takagi.
Regarding claim 1, Khlat discloses:
An envelope tracking (ET) integrated circuit (IC) (ETIC) (Khlat, Figs. 2B-C) comprising: an input configured to receive a vramp signal from a baseband transceiver (Fig. 2C, see “DIFFERENTIAL VRAMP SIGNAL”, see also Col. 5, lines 2-4); a first driver amplifier (Fig. 2C, 928) coupled to a first offset capacitor (Fig. 2C, see connection between 928 and capacitor 18A) a second driver amplifier (Fig. 2C, 930) coupled to a second offset capacitor (Fig. 2C, see connection between 930 and capacitor 19, see also Col. 21, lines 49-53), and a controller circuit (Fig. 2C, 50) configured to: switch between the first driver amplifier and the second driver amplifier (Col. 21, line 66-Col. 22, line 7); but fails to disclose and [the first driver amplifier coupled to] a first variable feedback circuit; [the second driver amplifier coupled to] the first variable feedback circuit, and [the second driver amplifier coupled to] a second variable delay circuit; and adjust a first delay for a first path that extends from a node to the second driver amplifier through the second variable delay circuit to match a second delay for a second path that extends from the node to the second driver amplifier through the controller circuit.
However, Gebeyehu teaches and [the first driver amplifier coupled to] a first variable feedback circuit (Gebeyehu, Fig. 6, see connection between variable feedback circuit 107 and amplifier 101); [the second driver amplifier coupled to] the first variable feedback circuit (Fig. 6, see connection between variable feedback circuit 107 and amplifier 112), but fails to teach and [the second driver amplifier coupled to] a second variable delay circuit; and adjust a first delay for a first path that extends from a node to the second driver amplifier through the second variable delay circuit to match a second delay for a second path that extends from the node to the second driver amplifier through the controller circuit.
However, Takagi teaches and [the second driver amplifier coupled to] a second variable delay circuit (Takagi, Fig. 2, 2); and adjust a first delay for a first path that extends from a node to the second driver amplifier through the second variable delay circuit (Paragraph 28, lines 1-4) to match a second delay for a second path that extends from the node to the second driver amplifier through the controller circuit (Paragraph 28, lines 4-10).
Khlat, Gebeyehu, and Takagi are all considered to be analogous to the claimed invention because they are in the same field of improving driver amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Khlat to incorporate the teachings of Gebeyehu and Takagi to include the variable feedback circuit of Gebeyehu in the circuit of Khlat, which would have the effect of enabling control over the ouput voltage of the amplifier of Khlat (Gebeyehu, Page 10, lines 20-22), and to include the variable delay circuit of Takagi in the circuit of Khlat, which would have the effect of optimizing the slew rate of the circuit of Khlat (Takagi, Paragraph 4, lines 1-9).
Regarding claim 2, Khlat further discloses:
wherein the first offset capacitor is coupled to an output node (Khlat, Fig. 2C, see connection between 18A and output node 876).
Regarding claim 7, Khlat further discloses:
wherein the controller circuit is configured to adjust the first delay by adjusting the second variable delay circuit to increase a delay (Khlat, Col. 15, lines 51-58).
Regarding claim 9, Khlat further discloses:
further comprising a switch (Khlat, Fig. 2C, 936) that selectively couples the first driver amplifier to ground (Fig. 2C, see connection between 928 and ground via 936), wherein the controller circuit is configured to operate the switch to switch between the first driver amplifier and the second driver amplifier (Col. 21, line 66-Col. 22, line 7).
Regarding claim 10, Khlat further discloses:
further comprising a scaling circuit coupled to the node (Col. 14, lines 36-43).
Regarding claim 11, Khlat discloses:
11. A wireless device (Khlat, Figs. 2B-C) comprising: a baseband transceiver configured to produce a vramp signal (Fig. 2C, see “DIFFERENTIAL VRAMP SIGNAL”, see also Col. 5, lines 2-4); an envelope tracking (ET) integrated circuit (IC) (ETIC) coupled to the baseband transceiver (Figs. 2B-C), the ETIC comprising: an input configured to receive the vramp signal (Fig. 2C, see “DIFFERENTIAL VRAMP SIGNAL”, see also Col. 5, lines 2-4); a first driver amplifier (Fig. 2C, 928) coupled to a first offset capacitor (Fig. 2C, see connection between 928 and capacitor 18A) a second driver amplifier (Fig. 2C, 930) coupled to a second offset capacitor (Fig. 2C, see connection between 930 and capacitor 19, see also Col. 21, lines 49-53), and a controller circuit (Fig. 2C, 50) configured to: switch between the first driver amplifier and the second driver amplifier (Col. 21, line 66-Col. 22, line 7); but fails to disclose and [the first driver amplifier coupled to] a first variable feedback circuit; [the second driver amplifier coupled to] the first variable feedback circuit, and [the second driver amplifier coupled to] a second variable delay circuit; and adjust a first delay for a first path that extends from a node to the second driver amplifier through the second variable delay circuit to match a second delay for a second path that extends from the node to the second driver amplifier through the controller circuit.
However, Gebeyehu teaches and [the first driver amplifier coupled to] a first variable feedback circuit (Gebeyehu, Fig. 6, see connection between variable feedback circuit 107 and amplifier 101); [the second driver amplifier coupled to] the first variable feedback circuit (Fig. 6, see connection between variable feedback circuit 107 and amplifier 112), but fails to teach and [the second driver amplifier coupled to] a second variable delay circuit; and adjust a first delay for a first path that extends from a node to the second driver amplifier through the second variable delay circuit to match a second delay for a second path that extends from the node to the second driver amplifier through the controller circuit.
However, Takagi teaches and [the second driver amplifier coupled to] a second variable delay circuit (Takagi, Fig. 2, 2); and adjust a first delay for a first path that extends from a node to the second driver amplifier through the second variable delay circuit (Paragraph 28, lines 1-4) to match a second delay for a second path that extends from the node to the second driver amplifier through the controller circuit (Paragraph 28, lines 4-10).
Khlat, Gebeyehu, and Takagi are all considered to be analogous to the claimed invention because they are in the same field of improving driver amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Khlat to incorporate the teachings of Gebeyehu and Takagi to include the variable feedback circuit of Gebeyehu in the circuit of Khlat, which would have the effect of enabling control over the ouput voltage of the amplifier of Khlat (Gebeyehu, Page 10, lines 20-22), and to include the variable delay circuit of Takagi in the circuit of Khlat, which would have the effect of optimizing the slew rate of the circuit of Khlat (Takagi, Paragraph 4, lines 1-9).
Regarding claim 12, Khlat further discloses:
wherein the first offset capacitor is coupled to an output node (Khlat, Fig. 2C, see connection between 18A and output node 876).
Regarding claim 13, Khlat further discloses:
wherein the second offset capacitor is coupled to the output node (Khlat, Fig. 2C, see connection between 19 and output node 876).
Regarding claim 14, Khlat further discloses:
further comprising a power amplifier (Khlat, Fig. 2C, 869) coupled to the output node (Fig. 2C, see connection between 869 and output node 876).
Regarding claim 16, Khlat further discloses:
wherein the controller circuit is configured to adjust the first delay by adjusting the second variable delay circuit to increase a delay (Khlat, Col. 15, lines 51-58).
Regarding claim 18, Khlat further discloses:
further comprising a switch (Khlat, Fig. 2C, 936) that selectively couples the first driver amplifier to ground (Fig. 2C, see connection between 928 and ground via 936), wherein the controller circuit is configured to operate the switch to switch between the first driver amplifier and the second driver amplifier (Col. 21, line 66-Col. 22, line 7).
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Khlat in view of Gebeyehu and Takagi as applied to claim 2 above, and further in view of Khlat (Patent Publication Number US 2019/0044480 A1), as cited by applicant, hereafter referred to as Khlat2019.
Regarding claim 3, Khlat further discloses:
wherein the second offset capacitor is coupled to the output node (Khlat, Fig. 2C, see connection between 19 and output node 876), but fails to disclose and wherein the second offset capacitor is serially positioned between the second driver amplifier and the output node.
However, Khlat2019 teaches and wherein the second offset capacitor is serially positioned between the second driver amplifier and the output node (Khlat2019, Fig. 4, see connection between driver 128 and output node 132 via offset capacitor COFFSET2).
Khlat, Gebeyehu, Tagaki, and Khlat2019 are all considered to be analogous to the claimed invention because they are in the same field of improving driver amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Khlat to incorporate the teachings of Khlat2019 to include the offset capacitor of Khlat2019 in the circuit of Khlat, which would have the effect of providing DC blocking for the circuit of Khlat (Khlat2019, Paragraph 62, lines 20-22).
Claims 4-5 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Khlat in view of Gebeyehu and Takagi as applied to claims 1 and 11, respectively, above, and further in view of Mead et al. (Patent Publication Number WO 9,828,943 A1), hereafter referred to as Mead.
Regarding claim 4, Khlat fails to disclose:
further comprising a bandpass filter coupled to the input and the node.
However, Mead teaches further comprising a bandpass filter (Mead, Fig. 9, 116-1) coupled to the input and the node (Fig. 9, see connection between bandpass filter 116-1, input 128, and node between 142-1 and 146).
Khlat, Gebeyehu, Takagi, and Mead are all considered to be analogous to the claimed invention because they are in the same field of improving driver amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Khlat to incorporate the teachings of Mead to include a bandpass filter at the input of Khlat, which would have the effect of removing undesired signal frequencies from the input signal of Khlat.
Regarding claim 5, Khlat fails to disclose:
further comprising an anti-aliasing filter (AAF) coupled to the node and the first driver amplifier.
However, Mead teaches further comprising an anti-aliasing filter (AAF) (Mead, Fig. 9, 146) coupled to the node and the first driver amplifier (Fig. 9, see connection between 146 and driver amplifier 144-1).
Khlat, Gebeyehu, Takagi, and Mead are all considered to be analogous to the claimed invention because they are in the same field of improving driver amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Khlat to incorporate the teachings of Mead to include an anti-aliasing filter in the circuit of Khlat, which would have the effect of ensuring proper signal sampling (Mead, Page 25, lines 2-4).
Regarding claim 15, Khlat fails to disclose:
further comprising an anti-aliasing filter (AAF) coupled to the node and the first driver amplifier.
However, Mead teaches further comprising an anti-aliasing filter (AAF) (Mead, Fig. 9, 146) coupled to the node and the first driver amplifier (Fig. 9, see connection between 146 and driver amplifier 144-1).
Khlat, Gebeyehu, Takagi, and Mead are all considered to be analogous to the claimed invention because they are in the same field of improving driver amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Khlat to incorporate the teachings of Mead to include an anti-aliasing filter in the circuit of Khlat, which would have the effect of ensuring proper signal sampling (Mead, Page 25, lines 2-4).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Khlat in view of Gebeyehu and Takagi as applied to claim 1 above, and further in view of Marques et al. (Patent Publication Number US 2019/0006991 A1), hereafter referred to as Marques.
Regarding claim 6, Khlat fails to disclose:
wherein the second offset capacitor is smaller than the first offset capacitor.
However, Marques teaches wherein the second offset capacitor is smaller than the first offset capacitor (Marques, Paragraph 42, lines 1-3).
Khlat, Gebeyehu, Takagi, and Marques are all considered to be analogous to the claimed invention because they are in the same field of improving driver amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Khlat to incorporate the teachings of Marques to make the offset capacitors of Khlat have different capacitance values, which would have the effect of providing proper frequency shifting for the capacitors of Khlat (Marques, Paragraph 42, lines 9-12).
Claims 8 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Khlat in view of Gebeyehu, Takagi, and Mead as applied to claims 5 and 15, respectively, above, and further in view of Takeuchi (Patent Number JP 3,941,107 B2), hereafter referred to as Takeuchi.
Regarding claim 8, Khlat and Mead fail to disclose:
wherein the controller circuit is configured to adjust the first delay by adjusting the AAF to increase a delay.
However, Takeuchi teaches wherein the controller circuit is configured to adjust the first delay by adjusting the AAF to increase a delay (Takeuchi, Paragraph 22, lines 1-3 and 13-19).
Khlat, Gebeyehu, Takagi, Mead, and Takeuchi are all considered to be analogous to the claimed invention because they are in the same field of improving driver amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Khlat to incorporate the teachings of Takeuchi to include an adjustable anti-aliasing filter in the circuit of Khlat, which would have the effect of enabling further control over the path delays of Khlat (Takeuchi, Paragraph 22, lines 1-7)
Regarding claim 17, Khlat and Mead fail to disclose:
wherein the controller circuit is configured to adjust the first delay by adjusting the AAF to increase a delay.
However, Takeuchi teaches wherein the controller circuit is configured to adjust the first delay by adjusting the AAF to increase a delay (Takeuchi, Paragraph 22, lines 1-3 and 13-19).
Khlat, Gebeyehu, Takagi, Mead, and Takeuchi are all considered to be analogous to the claimed invention because they are in the same field of improving driver amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Khlat to incorporate the teachings of Takeuchi to include an adjustable anti-aliasing filter in the circuit of Khlat, which would have the effect of enabling further control over the path delays of Khlat (Takeuchi, Paragraph 22, lines 1-7)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Eidson et al. (Patent Number US 6,255,906 B1) discloses an envelope tracking system for switchable power amplifiers including path delay compensation circuitry.
Khesbak et al. (Patent Publication Number US 2018/0076772 A1) discloses (Fig. 10) an envelope tracking system for a power amplifier.
Wimpenny (Patent Publication Number GB 2,510,396 A) discloses (Fig. 8) an envelope tracking system for a two power amplifier system including delay compensation circuitry.
Wessel et al. (Patent Publication Number JP 2000/216640 A) discloses (Figs. 6-7) an envelope tracking system including delay circuitry and an anti-aliasing filter.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00.
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/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843