Non-Final Rejection
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This application was filed with claims 1-32, and by preliminary amendment filed 5/10/2023 the specification and claims 6-9, 11, 13-16, 21, 25-27, 29-32 are amended. Claims 1-32 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 7 includes the term “the signal distribution circuit” but there is insufficient antecedent basis for this term. It was introduced in claim 5, but claim 7 is not related to claim 5. Note that claim 7 cannot merely be changed to depend from claim 5, as then there would not be antecedent basis for “the addressing circuit.”
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-9, 13, 15-17, 21-27, 29, and 31-32 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2021/0349188 (“Tabata”).
1. An illumination apparatus, comprising:
Tabata is a light source with emission section. [0001].
a first semiconductor layer comprising a plurality of emitters that are electrically interconnected in or on the first semiconductor layer; and
a second semiconductor layer bonded to the first semiconductor layer in a stacked arrangement, the second semiconductor layer comprising a plurality of transistors that are electrically connected to respective emitters or subsets of the plurality of emitters at a bonding interface between the first and second semiconductor layers.
Throughout, Tabata describes a chip Ch2 (i.e. first semiconductor layer, see discussion at [0139] et seq.) that comprises a plurality of emitters 2a in emission section 2, and a chip Ch3 or Ch4 (i.e. second semiconductor layer, the transistors are MOSFETs) that includes driver circuitry 3 including transistors Q1 and power supply circuitry 4 for the driver circuitry, respectively, and the latter two may be combined into one chip Ch34. [0124]-[0125]. The emitters are all electrically interconnected and the transistors are electrically connected to respective emitters for driving the emitters. See Fig. 3-5 and discussion starting at [0092]. Chip Ch2 is “mounted” on the chip Ch3 or Ch34. Figs. 7, 11, 12. Fig. 11 shows the lasers which are part of chip Ch2 are soldered to chip Ch3/Ch34, [0160], so they are bonded.
2. The illumination apparatus of claim 1, wherein the bonding interface comprises anode and/or cathode connections to the respective emitters or subsets, and wherein the transistors define respective control circuits that are electrically connected to the anode and/or cathode connections.
3. The illumination apparatus of claim 2, wherein the respective control circuits comprise driver circuits, and wherein each of the driver circuits is electrically connected to the anode or cathode connections of the respective emitters or subsets at the bonding interface.
The transistors are control circuits and are driver circuits, they are called driving transistors, and are connected to the anode/cathode of the emitters. [0098]-[0101], [0163]-[0164].
4. The illumination apparatus of claim 3, wherein the respective emitters or subsets are electrically interconnected by array interconnects to define a two-dimensional array of the respective emitters or subsets, and wherein the driver circuits define a two-dimensional array of the driver circuits that are electrically connected to the two-dimensional array of the respective emitters or subsets, respectively, at the bonding interface.
The emitters may be in a two dimensional array as shown in Fig. 9. As shown in Fig. 12B, there may be a driver under each emitter, so the driver circuits may likewise be a two dimensional array electrically connected to the emitters. It is also clear that all of the emitters may be electrically interconnected, see Fig. 4 where all are connected to Vd, in which case there will be interconnects electrically interconnecting them.
5. The illumination apparatus of claim 3, further comprising a signal distribution circuit that is electrically connected to the driver circuits and is configured to control timings of respective drive signals output from the driver circuits.
There is further a frame synchronization signal sent by image sensor 7 that controls the timings of the drive signals and the emitters. Fig. 5, [0108].
6. The illumination apparatus of claim 3, further comprising an addressing circuit that is configured to address the driver circuits to individually select one of the respective emitters or subsets at a time.
7. The illumination apparatus of claim 6, wherein the respective control circuits of the second semiconductor layer comprise the signal distribution circuit and/or the addressing circuit.
There is a driving control section 31, see Figs. 3 and 5, that may be considered the addressing circuit. It controls the switches SW to control whether the transistor driver circuits are conductive. [0105]-[0109]. This will allow individual control of the emitters, since each transistor has a separate controllable switch; we would not need each one to have its own switch if there was no individual control. Additionally, in Fig. 5, the driving control section may separately control respective subsets of emitters, the two separate groups 2a.
The addressing circuit 31 may be in the second semiconductor layer, since in Figs. 3 and 5 it is within the dashed line delineating the “driving section” 3/3A and the “driving section” is part of chip Ch3/Ch34, [0124].
8. The illumination apparatus of claim 1, further comprising: one or more additional circuits configured to provide localized decoupling capacitance, power supply routing, and/or other control of the respective emitters or subsets, wherein the one or more additional circuits is in the second semiconductor layer or is in a third semiconductor layer that is stacked on and bonded to the second semiconductor layer opposite the first semiconductor layer.
There is a power supply 4 including circuitry 40 that provides power supply routing, or alternatively there is driving control section 31 that provides “other control.” These may be in the second semiconductor layer Ch34. [0125].
9. The illumination apparatus of claim 2, wherein the bonding interface between the first and second semiconductor layers comprises hybrid bonding, through vias, and/or bump-bonds that electrically connect the anode and/or cathode connections to the control circuits and/or to an electrical ground.
The bonding interface is soldering, Fig. 11 Hb, [0160], which is bump bonding.
13. The illumination apparatus of claim 1, wherein the transistors are directly connected with the anodes and/or cathode connections of the respective emitters or subsets at the bonding interface.
It is apparent that the transistors are directly connected to the anode/cathode of the emitters. Fig. 3, 12B.
15. The illumination apparatus of claim 1, wherein the first semiconductor layer is between the emitters and the bonding interface, and the emitters comprise respective lasing apertures that are opposite the first semiconductor layer.
16. The illumination apparatus of claim 1, wherein the emitters are between the first semiconductor layer and the bonding interface, and the emitters comprise respective lasing apertures that are facing the first semiconductor layer.
Figs. 10 and 11 of Tabata show that either configuration can be used. Layer 20 between the bonding interface and the emitters 2a, with lasing aperture opposite the layer 20, or emitters 2a between the layer 20 and the bonding interface, with lasing aperture facing the layer 20. While Fig. 10 specifically shows chip Ch2 bonded to a substrate (and not chip Ch3), the discussion of Fig. 12 shows that this configuration is also usable when bonding to chip Ch3. [0163]-[0164].
Regarding claim 17, the claim is a method of fabricating an illumination device that is merely “providing” the elements that are in claim 1 and bonding together the semiconductor layers. The claim is therefore met for the same reasons as claim 1 discussed above.
Regarding claim 21, see rejection of claim 2 above.
Regarding claim 22, see rejection of claim 3 above.
Regarding claim 23, see rejection of claim 4 above.
Regarding claim 24, see rejection of claim 5 above.
Regarding claim 25, see rejection of claim 6 above.
Regarding claim 26, see rejection of claim 8 above.
Regarding claim 27, see rejection of claim 9 above.
Regarding claim 29, see rejection of claim 13 above.
Regarding claim 31, see rejection of claim 15 above.
Regarding claim 32, see rejection of claim 16 above.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 10, 14, 28, and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Tabata.
Regarding claims 10 and 28, Tabata teaches the limitations of the parent claims, and additionally the subsets of lasers are clearly in parallel, see Figs. 3-4. Tabata does not give any length between the lasers, i.e. interconnection lengths. It would have been obvious to a person of ordinary skill in the art at the time of the invention to provide with respective interconnection lengths of less than about 10 microns because when the general conditions of a claim are disclosed by the prior art it is generally not inventive to discover an optimum or workable range or value by routine experimentation. See MPEP 2144.05 II.A. Additionally, persons skilled in the art of semiconductor devices routinely recognize the value of making the devices smaller, as the device may fit inside a smaller footprint. A person skilled in the art would have reason to make the device to be as small as practical.
Regarding claims 14 and 30, Tabata teaches the limitations of the parent claims, but does not show the bonding interface includes one or more interposer or redistribution layers between the first and second semiconductor layers. The examiner takes official notice that redistribution layers are common to use at bonding locations in semiconductor device fabrication. It would have been obvious to a person of ordinary skill in the art to use them because they are an additional metal layer that allows the bonding location to be moved to a more convenient location on the chip.
Claims 11-12 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Tabata in view of US 2015/0214201 (“Schug”).
Regarding claims 11 and 18, in Tabata the transistors are native to Ch3 and the emitters are native to Ch2. It is not clear though that these are wafers bonded to each other. Shug teaches a similar device with an emitter wafer bonded to a transistor driver wafer. See Fig. 8, [0041]-[0042], [0052]. It would have been obvious to a person of ordinary skill in the art to do bonding at the wafer level because it only requires one alignment step between the two wafers, rather than aligning individual elements together, as taught by Schug. [0012].
Regarding claims 12 and 19, Tabata additionally does not show that the semiconductor layers comprise singulated portions that are bonded to one another and define respective integrated emitter-electronics structures. Schug shows a similar device, with light emitters on one wafer bonded to transistor drivers on another wafer. Fig. 8. Schug Fig. 8 also shows dicing lines, [0052], therefore it is apparent the bonded portions may be singulated into respective emitter-electronics structures. It would have been obvious to a person of ordinary skill in the art to dice the devices as claimed in the case where the user wishes to have individual emitters.
Note that the “optionally” language is not required claim 19, it is by definition optional and therefore the broadest reasonable interpretation does not have to include it. It is not indefinite, it is clear that it is optional (unlike exemplary type language, which may leave some doubt whether a limitation is a requirement, see MPEP 2173.05(d)).
Claim 20 is rejected under 35 U.S.C. 103 as being unpatentable over Tabata and Schug as applied to the parent claims, and further in view of US 2018/0301865 (“Burroughs”).
Tabata teaches the limitations of the parent claims, but does not show the features of claim 20. Burroughs teaches that laser arrays may be made by transfer printing on a third non-native substrate via epitaxial liftoff. [0068], [0075]. It would have been obvious to a person of ordinary skill in the art to use such a process as it allows greater control of the fabrication, for example the VCSELS might be thinner than conventional ([0081]), spacing may be controlled, or different types of lasers might be integrated together, and costs may be reduced ([0084]) as taught by Burroughs.
Note that the “optionally” language is not required in the claim, it is by definition optional and therefore the broadest reasonable interpretation does not have to include it. It is not indefinite, it is clear that it is optional (unlike exemplary type language, which may leave some doubt whether a limitation is a requirement, see MPEP 2173.05(d)).
It should also be noted that the examiner has a favorable opinion of the rejections presented in the EPO, Korea, and WIPO. See the Information Disclosure Statements filed by applicant.
Other art is cited which also appears to show the invention, a wafer of light emitters bonded to a wafer of drivers/transistors, and any of these could also likely be applied against at least the independent claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James Menefee whose telephone number is (571)272-1944. The examiner can normally be reached M-F 7-4.
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/JAMES A MENEFEE/ Primary Examiner, Art Unit 2828