CTNF 18/252,839 CTNF 84525 Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of Group I, reading on claims 1-14 and 20 in the reply filed on 9/29/25 is acknowledged. Priority 02-26 AIA Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Rejections - 35 USC § 103 07-23-aia AIA The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claim s 1, 3, 4, 6-8, 10, 14, 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mitsuhashi et al. (US 2013/0020468, Mitsuhashi herein after) in view of Seta (US 2014/0284745) . Regard to claim 1, Mitsuhashi teaches a solid-state imaging device comprising: a first semiconductor substrate (2 + 2a) including a first semiconductor layer (2) in which a photoelectric conversion unit (20) configured to perform photoelectric conversion is formed, and a first multilayer wiring layer (2a) including an interlayer insulating film (26) formed on a side of the first semiconductor layer remote from a light incident surface; a second semiconductor substrate (9 + 9a) including a second semiconductor layer (9) in which a circuit (i.e. multiple transistors with wiring connection) is formed and a second multilayer wiring layer (9a) including an interlayer insulating film (36) formed on a side of the second semiconductor layer adjacent to the light incident surface, the second multilayer wiring layer being bonded to the first multilayer wiring layer; an antioxidant layer (2b/9b) provided in at least one of the first multilayer wiring layer or the second multilayer wiring layer. Mitsuhashi, however, does not expressly teach a light shielding layer provided in at least one of the first multilayer wiring layer or the second multilayer wiring layer so as to be exposed to a bonding surface between the first multilayer wiring layer and the second multilayer wiring layer; and the antioxidant layer is provided at least either between the light shielding layer and the interlayer insulating film of the first multilayer wiring layer or between the light shielding layer and the interlayer insulating film of the second multilayer wiring layer. Nonetheless, these features are well known in the solid-state imaging device art and would have been an obvious modification of the device disclosed by Mitsuhashi, as evidenced by Seta. Seta discloses a solid-state imaging device (10, Fig. 2) with a light shielding layer (13, [0037]) provided in at least one of the first multilayer wiring layer (63/64) or the second multilayer wiring layer so as to be exposed to a bonding surface (Fig. 3) between the first multilayer wiring layer and the second multilayer wiring layer. Since Mitsuhashi and Seta are in the same field of endeavor, a person having ordinary skill in the art at the time of filing would have readily recognized the desirability and advantages of modifying Mitsuhashi, as suggested by Seta, by employing a light shielding layer at the first multilayer wiring layer exposing to the bonding surfaces. This shielding layer would reduce the noise disturbance which affects the imaging element pixel chip and the readout circuit, by shielding or reducing the radiation noise, or the electromagnetic waves which are created in the logic circuit (Seta [0040]). Furthermore, the combination of Mitsuhashi and Seta would teach the antioxidant layer (Mitsuhashi 2b) is provided at least between the light shielding layer (Seta 13) and the interlayer insulating film (Mitsuhashi 26) of the first multilayer wiring layer. As to claims 3 and 4, Mitsuhashi in view of Seta teach the device of claim 1, wherein the antioxidant layer is a substance that is lower in hygroscopicity than the interlayer insulating film and the antioxidant layer is silicon nitride (Mitsuhashi [0098]). As to claims 6 and 7, Mitsuhashi in view of Seta teach the device of claim 1, further comprising an insulating layer (Seta: organic silicon oxide, 13) provided in at least one of the first multilayer wiring layer or the second multilayer wiring layer so as to be exposed to the bonding surface, the insulating layer being different in material from the interlayer insulating film (Mitsuhashi 26) and wherein the insulating layer is an oxide that is identical in material to the light shielding layer (Seta: [0031]). As to claim 8, Mitsuhashi in view of Seta teach the device of claim 1, wherein the first semiconductor substrate includes a pixel region (Mitsuhashi 4) in which a plurality of the photoelectric conversion units (Mitsuhashi 18) is provided, and the antioxidant layer is aligned with the pixel region in plan view. As to claim 10, Mitsuhashi in view of Seta teach the device of claim 1, wherein the antioxidant layer is provided in both the first multilayer wiring layer and the second multilayer wiring layer, and the antioxidant layer (Mitsuhashi 2b) provided in the first multilayer wiring layer and the antioxidant layer (Mitsuhashi 9b) provided in the second multilayer wiring layer have portions aligned with each other in plan view. As to claim 14, Mitsuhashi in view of Seta teach the device of claim 1, further comprising: a first connecting pad (Mitsuhashi 27) provided in the first multilayer wiring layer of the first semiconductor substrate; a second connecting pad (Mitsuhashi 37) provided in the second multilayer wiring layer of the second semiconductor substrate, the second connecting pad being electrically connected to the first connecting pad; and a gap (i.e., gap provided by layers 2b and 9b, Mitsuhashi) in contact with both the first connecting pad and the second connecting pad. Regard to claim 20, Mitsuhashi teaches an electronic instrument comprising: A solid-state image device including a first semiconductor substrate (2 + 2a) including a first semiconductor layer (2) in which a photoelectric conversion unit (20) configured to perform photoelectric conversion is formed, and a first multilayer wiring layer (2a) including an interlayer insulating film (26) formed on a side of the first semiconductor layer remote from a light incident surface; a second semiconductor substrate (9 + 9a) including a second semiconductor layer (9) in which a circuit (i.e. multiple transistors with wiring connection) is formed and a second multilayer wiring layer (9a) including an interlayer insulating film (36) formed on a side of the second semiconductor layer adjacent to the light incident surface, the second multilayer wiring layer being bonded to the first multilayer wiring layer; an antioxidant layer (2b/9b) provided in at least one of the first multilayer wiring layer or the second multilayer wiring layer; an optical lens (19) configured to form an image of image light from a subject on an imaging surface of the solid-state imaging device; and a signal processing circuit (11) configured to perform signal processing on a signal output from the solid-state imaging device. Mitsuhashi, however, does not expressly teach a light shielding layer provided in at least one of the first multilayer wiring layer or the second multilayer wiring layer so as to be exposed to a bonding surface between the first multilayer wiring layer and the second multilayer wiring layer; and the antioxidant layer is provided at least either between the light shielding layer and the interlayer insulating film of the first multilayer wiring layer or between the light shielding layer and the interlayer insulating film of the second multilayer wiring layer. Nonetheless, these features are well known in the solid-state imaging device art and would have been an obvious modification of the device disclosed by Mitsuhashi, as evidenced by Seta. Seta discloses a solid-state imaging device (10, Fig. 2) with a light shielding layer (13, [0037]) provided in at least one of the first multilayer wiring layer (63/64) or the second multilayer wiring layer so as to be exposed to a bonding surface (Fig. 3) between the first multilayer wiring layer and the second multilayer wiring layer. Since Mitsuhashi and Seta are in the same field of endeavor, a person having ordinary skill in the art at the time of filing would have readily recognized the desirability and advantages of modifying Mitsuhashi, as suggested by Seta, by employing a light shielding layer at the first multilayer wiring layer exposing to the bonding surfaces. This shielding layer would reduce the noise disturbance which affects the imaging element pixel chip and the readout circuit, by shielding or reducing the radiation noise, or the electromagnetic waves which are created in the logic circuit (Seta [0040]). Furthermore, the combination of Mitsuhashi and Seta would teach the antioxidant layer (Mitsuhashi 2b) is provided at least between the light shielding layer (Seta 13) and the interlayer insulating film (Mitsuhashi 26) of the first multilayer wiring layer . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 2, 5, 9, 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion 07-96 AIA The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Eva Yan Montalvo whose telephone number is (571)270-3829. The examiner can normally be reached M-TH 9AM-7PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Fristoe can be reached at (571) 272-4926 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /EVA Y MONTALVO/ Supervisory Patent Examiner, Art Unit 2818 Application/Control Number: 18/252,839 Page 2 Art Unit: 2818 Application/Control Number: 18/252,839 Page 3 Art Unit: 2818 Application/Control Number: 18/252,839 Page 4 Art Unit: 2818 Application/Control Number: 18/252,839 Page 5 Art Unit: 2818 Application/Control Number: 18/252,839 Page 6 Art Unit: 2818 Application/Control Number: 18/252,839 Page 7 Art Unit: 2818 Application/Control Number: 18/252,839 Page 8 Art Unit: 2818
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