Prosecution Insights
Last updated: April 19, 2026
Application No. 18/253,203

SOLID-STATE IMAGING ELEMENT, IMAGING DEVICE, AND ELECTRONIC DEVICE

Non-Final OA §102§112
Filed
May 16, 2023
Examiner
ROLAND, CHRISTOPHER M
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Sony Semiconductor Solutions Corporation
OA Round
1 (Non-Final)
65%
Grant Probability
Moderate
1-2
OA Rounds
3y 2m
To Grant
86%
With Interview

Examiner Intelligence

Grants 65% of resolved cases
65%
Career Allow Rate
347 granted / 537 resolved
-3.4% vs TC avg
Strong +21% interview lift
Without
With
+21.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
33 currently pending
Career history
570
Total Applications
across all art units

Statute-Specific Performance

§103
50.1%
+10.1% vs TC avg
§102
21.3%
-18.7% vs TC avg
§112
24.1%
-15.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 537 resolved cases

Office Action

§102 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement Information disclosure statement filed 16 May 2023 has been fully considered. Specification The preliminary amendments to the specification were received on 16 May 2023. These preliminary amendments to the specification are acceptable. The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: SOLID-STATE IMAGING ELEMENT, IMAGING DEVICE, AND ELECTRONIC DEVICE COMPRISING ANNULAR SEMICONDUCTOR REGION. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 1, 11, and 12 recite the limitation, “at a subsequent stage of a position of the hole of the annular structure.” The term “at a subsequent stage” is indefinite. It is unclear whether this term refers to a spatial positioning, and if so, how or where a subsequent stage may be positioned. The disclosure does not appear to offer a special technical definition for this term. Claims 3-5 recite the limitation, “the semiconductor region of the second polarity is the cathode.” It is unclear how the semiconductor region of the second polarity may be connected to the cathode as require by claim 1, and also be the cathode as required by claims 3-5. Claim 9 recites the limitation, “at a preceding stage of the hole.” The term “at a preceding stage” is indefinite. It is unclear whether this term refers to a spatial positioning, and if so, how or where a subsequent stage may be positioned. The disclosure does not appear to offer a special technical definition for this term. Claims 2, 6-8, and 10 are rejected for merely containing the flaws of the parent claim. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sasago et al. (US Patent Application Publication 2020/0105958, hereinafter Sasago ‘958). With respect to claim 1, as best understood by Examiner, Sasago ‘958 teaches (FIGs. 18 and 19) a solid-state imaging element as claimed, comprising: an avalanche photodiode (object of FIGs. 18 and 19) including an avalanche region (central region) ([0198-0205]) including: a semiconductor region of a first polarity (13) connected to an anode (7) ([0198-0205]); and a semiconductor region of a second polarity (12) connected to a cathode (1) ([0198-0205]), wherein the semiconductor region of the first polarity (13) has an annular structure (see FIG. 19) with a hole (defined at element 3) at a center portion as seen in an incident direction of incident light ([0198-0205]), and the semiconductor region of the second polarity (12) is formed at a subsequent stage of a position of the hole (defined at element 3) of the annular structure in the incident direction of the incident light ([0198-0205]). With respect to claim 2, as best understood by Examiner, Sasago ‘958 teaches wherein the semiconductor region of the first polarity (13) is a P+ type semiconductor region or an N+ type semiconductor region, and the semiconductor region of the second polarity (12) is an N+ type semiconductor region or a P+ type semiconductor region (Examiner notes that modifiers “+,” “++,” “-,“ “--,“ etc. are merely signifiers of relative doping concentrations and do not have universal definition; because the semiconductor region of the first polarity 13 and the semiconductor region of the second polarity 12 have substantially the same relative doping concentration, this concentration can be interpreted as “+”) ([0198-0205]). With respect to claim 3, as best understood by Examiner, Sasago ‘958 teaches wherein the semiconductor region of the second polarity (12) is the cathode (1) including a semiconductor with excessive impurities ([0198-0205]). With respect to claim 4, as best understood by Examiner, Sasago ‘958 teaches wherein the semiconductor region of the second polarity (12) is the cathode (1) including an N++ type semiconductor region or a P++ type semiconductor region (Examiner notes that modifiers “+,” “++,” “-,“ “--,“ etc. are merely signifiers of relative doping concentrations and do not have universal definition; because the cathode 1 has a greater doping concentration than the semiconductor region of the second polarity 12, this concentration can be interpreted as “++”) ([0198-0205]). With respect to claim 5, as best understood by Examiner, Sasago ‘958 teaches wherein the semiconductor region of the first polarity (13) is a P+ type semiconductor region or an N+ type semiconductor region, and the semiconductor region of the second polarity (12) is a cathode including an N+ type semiconductor region and an N++ semiconductor region (1) or a cathode including a P+ type semiconductor region and a P++ semiconductor region (see comments above concerning relative doping concentrations) ([0198-0205]). With respect to claim 6, as best understood by Examiner, Sasago ‘958 teaches wherein in the semiconductor region of the second polarity (12), the N+ type semiconductor region is formed so as to surround the cathode (1) including the N++ semiconductor region, or the P+ type semiconductor region is formed so as to surround the cathode including the P++ semiconductor region (see comments above concerning relative doping concentrations) ([0198-0205]). With respect to claim 7, as best understood by Examiner, Sasago ‘958 teaches wherein a relationship between a diameter of the hole (defined at element 3) as seen in the incident direction and a diameter of the semiconductor region of the second polarity (12) as seen in the incident direction is a relationship in which there is one peak of an electric field intensity distribution in the avalanche region ([0198-0205]). It is noted that where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, claimed properties or functions are presumed to be inherent. In re Best, 195 USPQ 430, 433 (CCPA 1977). It has also been held that products of identical chemical composition cannot have mutually exclusive properties. A chemical composition and its properties are inseparable. Therefore, if the prior art teaches the identical chemical structure, the properties Applicant discloses and/or claims are necessarily present. In re Spada, 15 USQP2d 1655, 1658 (Fed. Cir. 1990). In this case, the relationship between a diameter of the hole as seen in the incident direction and a diameter of the semiconductor region of the second polarity as seen in the incident direction of Sasago ‘958 would inherently have the property of one peak of an electric field intensity distribution in the avalanche region because the avalanche photodiode of Sasago ‘958 is arranged in the same manner as disclosed. With respect to claim 8, as best understood by Examiner, Sasago ‘958 teaches wherein the semiconductor region of the first polarity (13) is a P+ type semiconductor region or an N+ type semiconductor region, the semiconductor region of the second polarity (12) is an N+ type semiconductor region or a P+ type semiconductor region, and a P- type semiconductor region (3) or an N- semiconductor region is further formed in the hole (defined at element 3) (see comments above concerning relative doping concentrations) ([0198-0205]). With respect to claim 9, as best understood by Examiner, Sasago ‘958 teaches wherein an N- type semiconductor region or a P- semiconductor region (3) is further formed at a preceding stage of the hole (defined at element 3) ([0198-0205]). With respect to claim 10, as best understood by Examiner, Sasago ‘958 teaches wherein the anode (7) is formed on a surface of a substrate (15), embedded in the substrate, or formed on a side surface of a pixel boundary ([0198-0205]). With respect to claim 11, Sasago ‘958 teaches (FIGs. 18 and 19) an imaging device as claimed, comprising: a solid-state imaging element (object of FIGs. 18 and 19) ([0198-0205]) including: an avalanche photodiode (object of FIGs. 18 and 19) including an avalanche region (central region) ([0198-0205]) including: a semiconductor region of a first polarity (13) connected to an anode (7) ([0198-0205]); and a semiconductor region of a second polarity (12) connected to a cathode (1) ([0198-0205]), wherein the semiconductor region of the first polarity (13) has an annular structure (see FIG. 19) with a hole (defined at element 3) at a center portion as seen in an incident direction of incident light ([0198-0205]), and the semiconductor region of the second polarity (12) is formed at a subsequent stage of a position of the hole (defined at element 3) of the annular structure in the incident direction of the incident light ([0198-0205]). With respect to claim 12, Sasago ‘958 teaches (FIGs. 18 and 19) an electronic device as claimed, comprising: a solid-state imaging element (object of FIGs. 18 and 19) ([0198-0205]) including: an avalanche photodiode (object of FIGs. 18 and 19) including an avalanche region (central region) ([0198-0205]) including: a semiconductor region of a first polarity (13) connected to an anode (7) ([0198-0205]); and a semiconductor region of a second polarity (12) connected to a cathode (1) ([0198-0205]), wherein the semiconductor region of the first polarity (13) has an annular structure (see FIG. 19) with a hole (defined at element 3) at a center portion as seen in an incident direction of incident light ([0198-0205]), and the semiconductor region of the second polarity (12) is formed at a subsequent stage of a position of the hole (defined at element 3) of the annular structure in the incident direction of the incident light ([0198-0205]). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Tochigi et al. (US Patent Application Publication 2022/0392944); Morimoto et al. (US Patent Application Publication 2023/0097091); and Shimada et al. (US Patent Application Publication 2024/0213281) teach annular avalanche photodiodes. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christopher M. Roland whose telephone number is (571)270-1271. The examiner can normally be reached Monday-Friday, 10:00AM-7:00PM Eastern. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at (571)270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /C.M.R./Examiner, Art Unit 2893 /YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
Read full office action

Prosecution Timeline

May 16, 2023
Application Filed
Sep 30, 2025
Non-Final Rejection — §102, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
65%
Grant Probability
86%
With Interview (+21.0%)
3y 2m
Median Time to Grant
Low
PTA Risk
Based on 537 resolved cases by this examiner. Grant probability derived from career allow rate.

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