Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 5, 16, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by U.S. Patent Application Publication No. 2011/0061232 Kawamura et al.
1. Referring to claim 1, Kawamura et al. teaches a wiring substrate, comprising: a substrate, (Figures 1 & 9 #30); at least one conductive layer, (Figures 1 & 9 connecting pad), located on a side of the substrate, (Figures 1 & 9 upper side of #30); wherein a conductive layer includes a plurality of pad groups, (Figures 1 & 9 connecting pad), and a pad group includes a plurality of conductive pads, (Figures 1 & 9 connecting pad); and a protective layer, (Figures 1 & 9 Solder Resist Layer (SR)), located on a side of the at least one conductive layer away from the substrate, (Figures 1 & 9 #30); wherein the protective layer includes a plurality of openings, (Figures 1 & 9 opening of the Solder Resist Layer (SR) above the conductive pad); a portion of the conductive layer, (Figures 1 & 9 connecting pad), exposed by an opening is a conductive pad, (Figures 1 & 9 connecting pad); wherein a maximum dimension, (L1), of the conductive pad, (Paragraph 0095 teaches the opening diameter to be 90µm =L1), in a direction parallel to the substrate is greater than or equal to 1.5 times a minimum distance, (L2), between an edge of the conductive pad and an edge of the conductive layer, (Paragraph 0095 teaches the conductive layer portion is 120µm, hence L2= 120 µm -90 µm =30 µm and 30 µm x 1.5=45 µm, and 90 µm > 45 µm), and less than or equal to 30 times the minimum distance between the edge of the conductive pad and the edge of the conductive layer, (Paragraph 0095 teaches the conductive layer portion is 120µm, hence L2= 120 µm -90 µm =30 µm and 30 µm x 30=900 µm, and 90 µm < 900 µm).
2. Referring to claim 2, Kawamura et al. teaches a wiring substrate according to claim 1, wherein the maximum dimension of the conductive pad in the direction parallel to the substrate is 0.5 to 5 times a distance between the conductive pad and a conductive pad adjacent thereto, (Paragraph 0095 teaches the pitch, (L3), is 150µm, hence L3/L1= 90/150=0.6, and 0.6 is between 0.5 to 5).
3. Referring to claim 4, Kawamura et al. teaches a wiring substrate according to claim 1, an area of the conductive pad is greater than or equal to 5000 µm2, and less than or equal to 55000 µm2 , (Paragraph 0095 teaches the opening diameter to be 90µm =L1, where the radius is 45 µm, A=π r2 , Area = 6362 µm2, and 6362 µm2 > 5000 µm2 ).
4. Referring to claim 5, Kawamura et al. teaches a wiring substrate according to claim 1, wherein of a same pad group, a distance between two adjacent conductive pads is greater than or equal to 70 µm, and less than or equal to 214 µm, (Paragraph 0095 teaches the pitch, (L3), is 150µm, and where the grouping is not defined the limitation is met by a uniform pitch of 150 µm).
5. Referring to claim 16, Kawamura et al. teaches a method of manufacturing a wiring substrate, (Figures 1 & 9 #30), comprising: forming a conductive layer on a substrate, (Figures 1 & 9 #30); wherein the conductive layer, (Figures 1 & 9 connecting pad), includes a plurality of pad groups, and a pad group includes a plurality of conductive pads; forming a protective layer, (Figures 1 & 9 Solder Resist Layer (SR)), on a side of the conductive layer, (Figures 1 & 9 connecting pad), away from the substrate, (Figures 1 & 9 upper side of #30), and forming openings, (Figures 1 & 9 opening of the Solder Resist Layer (SR) above the conductive pad), in the protective layer, (Figures 1 & 9 Solder Resist Layer (SR)); wherein a portion of the conductive layer, (Figures 1 & 9 connecting pad), exposed by an opening, (Figures 1 & 9 opening of the Solder Resist Layer (SR) above the conductive pad), is a conductive pad, (Figures 1 & 9 connecting pad); a maximum dimension of the conductive pad, (Paragraph 0095 teaches the opening diameter to be 90µm =L1), in a direction parallel to the substrate is less than or equal to 30 times a minimum distance between an edge of the conductive pad and an edge of the conductive layer, (Paragraph 0095 teaches the conductive layer portion is 120µm, hence L2= 120 µm -90 µm =30 µm and 30 µm x 30=900 µm, and 90 µm < 900 µm).
6. Referring to claim 20, Kawamura et al. teaches a method of manufacturing the wiring substrate according to claim 16, wherein the maximum dimension of the conductive pad, (L1), in the direction parallel to the substrate is greater than or equal to 1.5 times the minimum distance, (L2), between the edge of the conductive pad and the edge of the conductive layer, (Paragraph 0095 teaches the conductive layer portion is 120µm, hence L2= 120 µm -90 µm =30 µm and 30 µm x 1.5=45 µm, and 90 µm > 45 µm).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2011/0061232 Kawamura et al.
7. Referring to claim 3, Kawamura et al. teaches a wiring substrate according to claim 1, but is silent to wherein the maximum dimension of the conductive pad in the direction parallel to the substrate is greater than or equal to 105 µm, and less than or equal to 350 µm, (Paragraph 0095 teaches the conductive layer portion is 90 µm).
Kawamura et al. teaches in Paragraph 0095 the conductive pad is 90 µm.
The claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to know that a very small difference in distances between 105 µm and 90 µm would be obvious due to the fact that the semiconductor industry trends are based upon the miniaturization of known sizes, and also since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. Note that the specification contains no disclosure of either the critical nature of the claimed dimensions or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the Applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ2d 1934, 1936 (Fed. Cir. 1990).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2011/0061232 Kawamura et al. in view of U.S. Patent Application Publication No. 2016/0307862 Lin et al.
8. Referring to claim 18, Kawamura et al. teaches a method of manufacturing the wiring substrate according to claim 16, wherein in a step of forming the protective layer, (Figures 1 & 9 Solder Resist Layer (SR)), on the side of the conductive layer, (Figures 1 & 9 connecting pad), away from the substrate, (Figures 1 & 9 #30), but is silent to the protective layer is formed by chemical vapor deposition.
Lin et al. teaches a similar device where the solder resist is made by various different methods including CVD, (Paragraph 0058).
The claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to combine the teachings of Lin et al. with Kawamura et al. because it is well known in the art that the CVD method of depositing a solder resist is an obvious option from a selection of various more expensive alternatives, and also since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
9. Claims 6-15, 17, and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
10. The prior art teaches the claimed matter in the rejections above, but is silent with respect to the above teachings in combination with the wiring substrate according to claim 1, wherein the at least one conductive layer includes a plurality of conductive lines, and a portion of a conductive line exposed by the opening is the conductive pad; the conductive line includes a main surface and a side surface connected to the main surface, and the main surface is a surface of the conductive line away from the substrate; an included angle between the main surface and the side surface is greater than or equal to 105º and less than or equal to 145°, the wiring substrate according to claim 1, wherein the at least one conductive layer includes a plurality of conductive lines, and a portion of a conductive line exposed by the opening is the conductive pad; the conductive line includes a main surface, and a plurality of side surfaces that are each connected to the main surface, and the main surface is a surface of the conductive line away from the substrate; at least two side surfaces, that each have a small distance to the conductive pad of the conductive line, of the plurality of side surfaces are each a first side surface, and two first side surfaces are connected to each other via a curved surface; the wiring substrate according to claim 1, wherein the wiring substrate comprises a plurality of device regions; wherein the plurality of pad groups include a plurality of first pad groups and a single second pad group that are located in any device region, the first pad groups each include a first electrode pad and a second electrode pad that are spaced apart from each other, and the second pad group includes at least a power supply pad, a grounding pad, an address pad and an output pad that are arranged at intervals; the wiring substrate comprises a source voltage line and a driving voltage line; wherein the power supply pad is electrically connected to the source voltage line, and the address pad is electrically connected to an output pad in another device region; of the plurality of first pad groups, a first electrode pad of a first first pad group is electrically connected to the driving voltage line, a second electrode pad of a former first pad group is electrically connected to a first electrode pad of a latter first pad group, and a second electrode pad of a last first pad group is electrically connected to the output pad; wherein a maximum dimension, in the direction parallel to the substrate, of at least a pad of at least the first electrode pad of the first first pad group, the power supply pad and the grounding pad is less than or equal to 30 times a minimum distance between an edge of the pad and the edge of the conductive layer; the wiring substrate according to claim 1, the wiring substrate comprises a plurality of device sub-regions and a single control region; the plurality of pad groups include first pad groups located in any device sub-region, and the first pad groups each include a first electrode pad and a second electrode pad that are spaced apart from each other; the plurality of pad groups further include a second pad group located in the control region, and the second pad group includes a power supply pad, a grounding pad, an address pad and an output pad; the wiring substrate comprises a source voltage line and a driving voltage line; wherein the power supply pad is electrically connected to the source voltage line; of the first pad groups, a first electrode pad of a first first pad group is electrically connected to the driving voltage line, a second electrode pad of a former first pad group is electrically connected to a first electrode pad of a latter first pad group, and a second electrode pad of a last first pad group is electrically connected to the output pad; wherein a maximum dimension of at least the first electrode pad of the first first pad group in the direction parallel to the substrate is less than or equal to 30 times a minimum distance between an edge of the first electrode pad and the edge of the conductive layer; the wiring substrate according to claim 1, further comprising: an oxidation prevention layer covering a side of the conductive pad away from the substrate; and a conductive functional layer covering a side of the oxidation prevention layer away from the substrate; the backboard, comprising: a plurality of functional elements; at least one driving chip; and the wiring substrate according to claim l; wherein the plurality of pad groups in the wiring substrate include a first pad group and a second pad group, the first pad group is connected to a functional element, and the second pad group is connected to a driving chip; and/or the method of manufacturing the wiring substrate according to claim 16, wherein a step of forming the conductive layer on the substrate includes: depositing a conductive material on the substrate to form an initial conductive layer; forming a photoresist layer on a side of the initial conductive layer away from the substrate; baking the photoresist layer at a specified temperature; wherein the specified temperature is greater than or equal to 125
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and less than or equal to 135
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performing exposure and development on the photoresist layer to pattern the photoresist layer; and etching the initial conductive layer based on the patterned photoresist layer to form the conductive layer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VICTOR A MANDALA whose telephone number is (571)272-1918. The examiner can normally be reached on M-Th 8-6:30 EST.
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/VICTOR A MANDALA/Primary Examiner, Art Unit 2899 1/29/26