DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined
under the first inventor to file provisions of the AIA .
Response to Amendments
Applicant's response of 02/02/2026 has been acknowledged. Claims 1, 2-4, and 8 have been amended. No new matter has been added.
This office action considers claims 1-19 and 22 pending for prosecution and are examined on their merits.
Response to Arguments
Applicant’s arguments filed 02/02/2026 with respect to the rejection of claims 1, 2-4, and 8 have been fully considered but are moot in view of the new grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Notes: when present, hyphen separated fields within the hyphens (- -) represent, for example, as (30A - Fig 2B - [0128]) = (element 30A - Figure No. 2B - Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. The same conventions apply to Column and Sentence, for example (19:14-20) = (column19:sentences 14-20). These conventions are used throughout this document.
Claims 1-5 and 8 is rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 20160218155 A1 – hereinafter Park-155) in view of Tsuboi et al. (US 20200143741 A1 – hereinafter Tsuboi).
Regarding independent claim 1, Park-155 teaches:
(Currently Amended) An array substrate ([0046] – “the various
components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on one substrate”), comprising:
a plurality of pixel driving circuits (C – Fig. 5 – [0064] – “pixel circuit C”)
configured to drive light emission ([0064] – “a light emitting device E emitting light by receiving a driving current from the pixel circuit C” – this teaches configured to drive light emission) in a plurality of subpixels ([0064] – “The pixel P may emit monochromic light, and may emit one of red, blue, green, and white color light” – this teaches sub-pixels);
at least one dummy circuit (DC1 – Fig. 6 – [0104] – “dummy circuit DC1”) incapable of driving light emission ([0067] – “dummy pixel DP includes a dummy circuit DC but does not include a light emitting device” – if there isn’t a light emitting device present, the circuit is incapable of driving light emission); and
a plurality of voltage supply lines (ELVDD – Fig. 6 – [0089] – “driving voltage line ELVDDL”) configured to provide a voltage (ELVDD is a voltage line thus it’s configured to provide a voltage);
wherein (Fig. 6 annotated, see below, shows a capacitor in the dummy circuit with second capacitor electrode ‘Ce2’) of at least one pixel driving circuit (C) second capacitor electrode (Ce2) of the plurality of pixel driving circuits (C) is configured to have a same voltage level as the voltage of the plurality of voltage supply lines (ELVDD); and
a first capacitor electrode and a second capacitor electrode of the at least one dummy circuit are configured to have a same voltage level as the voltage of the plurality of voltage supply lines.
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Park-155 does not expressly disclose the other limitations of claim 1.
However, in an analogous art, Tsuboi teaches
a first capacitor electrode (Fig. 3 annotated, see below – [0038] – “capacitive element 206” – every capacitor has a first and second electrode, hereinafter ‘D-Ce1’) and a second capacitor electrode (Fig. 3 annotated, see below – [0038] – “capacitive element 206” – every capacitor has a first and second electrode, hereinafter ‘D-Ce2’) of the at least one dummy circuit ([0008] – “FIG. 3 is a view showing an example of the circuit of a dummy pixel according to the first embodiment”) are configured to have a same voltage level as the voltage of the plurality of voltage supply lines (208 – Fig. 3 – [0040] – “power supply potential 208 (to be referred to as a Vdd hereinafter)” – Fig. 3 shows D-Ce1 and D-Ce2 receive the same voltage due to the connecting line shown in Fig. 3 annotated, hereinafter ‘SRT’).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the dummy pixel circuit capacitor structure as taught by Tsuboi into Park-155.
An ordinary artisan would have been motivated to use the known technique of Tsuboi in the manner set forth above to produce the predictable result of [0004] – “a display device in which light emission of the dummy pixel is suppressed. The present invention provides a display device comprising a pixel area in which a plurality of pixels are arranged, and a dummy pixel area which is provided around the
pixel area and in which a plurality of dummy pixels are arranged, wherein each of the pixel and the dummy pixel includes a light-emitting element including a first electrode and a second electrode, and a driving transistor, wherein the first electrode of the light-emitting element is connected to the driving transistor in the pixel, and wherein in the dummy pixel, the light-emitting element is not connected to the driving transistor, a first potential is supplied to the first electrode, a second potential is supplied to the second electrode, and the light-emitting element does not emit light at a potential difference between the first potential and the second potential.”
Regarding claim 2, Park-155 as modified Tsuboi, by teaches claim 1 from which claim 2 depends. Park-155 further teaches
(Currently Amended) The array substrate of claim 1, wherein a
respective voltage supply line (ELVDD) of the plurality ([0010] – “The dummy circuit DC may be the same as the pixel circuit C” – each pixel is connected to a voltage supply line therefore there is a plurality of voltage supply lines) of voltage supply lines (ELVDD) is configured to provide the voltage to a storage capacitor (Cst1 – Fig. 5 – [0088] – “storage capacitor Cst1”) of the at least one pixel driving circuit (C), and provide the voltage to a second storage capacitor (Cst2 – Fig. 6 – [0104] – “storage capacitor Cst2”) of the at least one dummy circuit (DC1), so that the second capacitor electrode of the storage capacitor of the at least one pixel driving circuit, and the first capacitor electrode and a second capacitor electrode of the second storage capacitor of the at least one dummy circuit are configured to have a same voltage level as a voltage of the respective voltage supply line of the plurality of voltage supply lines.
Park-155 does not expressly disclose the other limitations of claim 2.
However, in an analogous art, Tsuboi teaches
so that the second capacitor electrode of the storage capacitor (Fig. 2 annotated, see below – [0038] – “capacitive element 206” – every capacitor has a first and second electrode, hereinafter ‘Ce2’) of the at least one pixel driving circuit (102 – Fig. 2 – [0035] – “plurality of pixels 102”), and the first capacitor electrode and a second capacitor electrode (D-Ce2) of the second storage capacitor of the at least one dummy circuit (301 – Fig. 3 – [0036] – “dummy pixels 301”) are configured to have a same voltage level as a voltage of the respective voltage supply line (208) of the plurality of voltage supply lines ({[0035] – “plurality of pixels 102”}, {[0036] – “plurality of dummy pixels 301”}).
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Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the pixel and dummy pixel circuit capacitor structure as taught by Tsuboi into Park-155.
An ordinary artisan would have been motivated to use the known technique of Tsuboi in the manner set forth above to produce the predictable result of as stated above in claim 1.
Regarding claim 3, Park-155 as modified Tsuboi, teaches claim 1 from which claim 3 depends. Park-155 does not expressly disclose the limitations of claim 3.
However, in an analogous art, Tsuboi teaches
(Currently Amended) The array substrate of claim 1, wherein
each of a control electrode, a first electrode, and a second electrode of at least one transistor (204 – Fig. 2 and Fig. 3 – [0040] – “light emission control transistor 204 is connected to a second power supply potential 208”) in the at least one dummy circuit (301) are configured to have a same voltage level as the voltage of the plurality of voltage supply lines (Fig. 3 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the dummy pixel circuit capacitor structure as taught by Tsuboi into Park-155.
An ordinary artisan would have been motivated to use the known technique of Tsuboi in the manner set forth above to produce the predictable result of as stated above in claim 1.
Regarding claim 4, Park-155 as modified Tsuboi, teaches claim 1 from which claim 4 depends. Park-155 does not expressly disclose the limitations of claim 4.
However, in an analogous art, Tsuboi teaches
(Currently Amended) The array substrate of claim 1, wherein the at least
one dummy circuit (301) comprises a second driving transistor (204) having a control electrode connected to a third capacitor electrode (D-Ce1) of the second storage capacitor (206 – Fig. 301 annotated shows this); and
each of a control electrode, a first electrode, and a second electrode of the second driving transistor (204) are configured to have a same voltage level as the voltage of the plurality of voltage supply lines (Fig. 3 shows this).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the dummy pixel circuit structure as taught by Tsuboi into Park-155.
An ordinary artisan would have been motivated to use the known technique of Tsuboi in the manner set forth above to produce the predictable result of as stated above in claim 1.
Regarding claim 5, Park-155 as modified Tsuboi, teaches claim 1 from which claim 5 depends. Park-155 further teaches
(Previously Presented) The array substrate of claim 1, further
comprising a plurality of data lines ([0051] – “a plurality of data lines DL1 through DLm” – hereinafter ‘DL’), a respective data line configured to provide a data voltage ([0158] – “data voltage”) to the at least one pixel driving circuit (C);
wherein the at least one dummy circuit (DC1) is disconnected from the plurality of data lines (DDL – Fig. 6 – [0051] – “a plurality of dummy pixels DP respectively coupled to a dummy data line DDL” – the dummy circuit is disconnected from the data line since it is connected to the dummy data line).
Regarding claim 8, Park-155 as modified Tsuboi, teaches claim 1 from which claim 8 depends. Park-155 does not expressly disclose the limitations of claim 8.
However, in an analogous art, Tsuboi teaches
(Currently Amended) The array substrate of claim 1, wherein each terminal
of each transistor and capacitor in the at least one dummy circuit (301) is configured to have a same voltage level as the voltage of the plurality of voltage supply lines (Fig. 3 shows this)
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the dummy pixel circuit structure as taught by Tsuboi into Park-155.
An ordinary artisan would have been motivated to use the known technique of Tsuboi in the manner set forth above to produce the predictable result of as stated above in claim 1.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Park-155 in view of Tsuboi, Ma et al. (US 20210313415 A1 – hereinafter Ma) and Park et al. (US 20200176551 A1 – hereinafter Park-551).
Regarding claim 6, Park-155 as modified Tsuboi, does not expressly disclose the limitations of claim 6.
However, in an analogous art, Ma teaches
(Previously Presented) The array substrate of claim 1, further comprising a plurality of second reset signal lines (1Ref – Fig. 8 – [0087] – “a second electrode of a first reset transistor T3 is electrically connected to a first reset signal line 1Ref”), a respective second reset signal line (1Ref) configured to provide a reset signal to a first electrode of a first transistor (T3 – Fig. 8 – [0087] – “reset transistor T3”) in the at least one pixel driving circuit (21 – Fig. 8 – [0092] – “pixel circuit 21”);
wherein the at least one dummy circuit is disconnected from the plurality of second reset signal (1REF).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the second reset signal line structure as taught by Ma into Park-155 and Tsuboi.
An ordinary artisan would have been motivated to use the known technique of Ma in the manner set forth above to produce the predictable result of resetting/initializing the transistor in the pixel drive circuit.
To do so would have merely been to apply a known technique to a known device ready for improvement to yield predictable results, KSR Int'l Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007), MPEP 2143 I. D.
Park-155, Tsuboi, and Ma do not expressly disclose the other limitations of claim 6.
However, in an analogous art, Park-551 teaches
wherein the at least one dummy circuit is disconnected (Park et al. (US 20200176551 A1 – hereinafter Park-551) (park-551 ([0182] – “In some exemplary embodiments, the dummy pixel PX-D may also have a pixel driving circuit CC different from that of the pixel PX. The number of the transistors constituting the pixel driving circuits CC may be different, or the transistors and a signal line (e.g., a scan line) may be disconnected”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the dummy circuit disconnect structure as taught by Park-551 into Park-155, Tsuboi and Ma.
An ordinary artisan would have been motivated to use the known technique of Park-551 in the manner set forth above to produce the predictable result [0006] – “of providing an electronic device including a display panel having a relatively large display region and a relatively small non-display region.”
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Park-155 in view of Tsuboi, Li (US 20210134223 A1 – hereinafter Li).
Regarding claim 22, Park-155 as modified Tsuboi, does not expressly disclose the limitations of claim 22.
However, in an analogous art, Li teaches
(Previously Presented) A display apparatus, comprising the array substrate
of claim 1, and an integrated circuit connected to the array substrate ([0092] – “one or more integrated circuits connected to the array substrate”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the integrated circuit structure as taught by Li into Park-155 and Tsuboi.
An ordinary artisan would have been motivated to use the known technique of Li in the manner set forth above to produce the predictable result [0092] – “the display apparatus includes the array substrate described herein, and one or more integrated circuits connected to the array substrate. Examples of appropriate display apparatuses include, but are not limited to, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital album, a GPS, OLEO display apparatus, etc.”
Allowable Subject Matter
Claims 7 and 9-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, prior art of record fails to teach or suggest “an orthographic projection of the plurality of second reset signal lines on a base substrate is non-overlapping with an orthographic projection of a plurality of data lines”.
Regarding claim 9, prior art of record fails to teach or suggest “the second node connecting line connects a first capacitor electrode of the at least one dummy circuit and a portion of a semiconductor material layer together”.
Regarding claim 10, prior art of record fails to teach or suggest “second node connecting line”.
Claims 11-15 are dependent on claim 10 and therefore would be allowable if claim 10 was rewritten in independent form.
Regarding claim 16, prior art of record fails to teach or suggest “second reset control signal line”.
Regarding claim 17, prior art of record fails to teach or suggest “second gate lines” and “second light emission control signal line”.
Claims 18 and 19 are dependent on claim 10 and therefore would be allowable if claim 10 was rewritten in independent form.
Pertinent Art
For the benefits of the Applicant, US 20150325593 A1 is cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitations including “at least one dummy circuit is disconnected from the plurality of second reset signal lines”.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the
examiner should be directed to GARY ABEL whose telephone number is (571) 272-0246. The examiner can normally be reached Monday - Friday 8:00 am - 5:00 pm (Eastern).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHAD M DICKE can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/GRA/
Examiner, Art Unit 2897
/CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897