DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 7, 11, 12, 14 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ichikoh (JP 2001287592).
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With respect to claim 1, Ichikoh discloses a passive timing circuit comprising: a rail (A1 or A2); a relay (circuit 2 in figure 1) operated by an octocoupler (Photocopler PC, for controlling Transistor Tr which controls the relay circuit 2 in figure 1), wherein the rail is connected to an input terminal of the relay; and a capacitive network (capacitor C2 for timer circuit in figure 4)(note: here network is interpreted as merely interconnected components) between the rail and ground, the capacitance of the capacitive network configured according to a timing period wherein the circuit is without a voltage source other than a leakage voltage applied by the input terminal which increases voltage of the rail over the timing period until the relay switches. (para [0008] “Is achieved by providing a timer circuit for delaying the cutoff of the supply of the holding current of the transistor to the relay coil from the time when the photocoupler is turned on by a predetermined lock time.”)
With respect to claim 2, Ichikoh discloses the passive timing circuit as claimed in claim 1, further comprising a reset switch (RS) which pulls the rail to ground.
With respect to claim 3, Ichikoh discloses the passive timing circuit as claimed in claim 2, wherein the reset switch comprises a manually operated switch (RS).
With respect to claim 7, Ichikoh discloses the passive timing circuit as claimed in claim 1, further comprising a current limiting resistor (R6) between the capacitive network and the output.
With respect to claim 11, Ichikoh produces a method of switching a relay (2) operated by an optocoupler (Photocopler PC, for controlling Transistor Tr which controls the relay circuit 2 in figure 1), the method comprising applying the passive timing circuit as claimed in claim 1 to the input terminal of the relay (2) so that voltage leaking from the input terminal of the relay increases the voltage of the rail over the time period across the capacitive network until the relay switches. (See para [0007]).
With respect to claim 12, Ichikoh produces the method as claimed in claim 11, wherein the capacitance of the capacitive network is selected according to a desirous timing period. (See [0032] “The lock time is set by the time constant (proportional to the product of R6 and C2) of the timer circuit formed by the resistor R6 and the capacitor C2. During the lock time, a current is supplied to the motor. Even if the movement is stopped by a slight catch, if the movement starts again within the lock time, the motor M can continue to move to the last standing position or the storage position. The length of the lock time is optimally designed by the values of the capacitor C2 and the resistor R6.”)
With respect to claim 14, Ichiroh produces the method as claimed in claim 12, further comprising the circuit as claimed in claim 2 (circuit with reset switch RS), the method comprising operating the reset switch to pull the rail to ground (second RS terminal in 2 is ostensibly connected to ground) to reset the relay. (See also fig. 2, “FIG. 2 shows the characteristics of the current flowing through the motor M. When the rotating motor M is stopped by an external force, a high lock current flows. By restarting the lock current by delaying the lock time determined by the product of the resistance values of RC, the restart can be performed.”)
With respect to claim 15, Ichikoh produces the method as claimed in claim 11, wherein the resistance of the circuit is selected according to a desirous timing period. (See para [0032] “The lock time is set by the time constant (proportional to the product of R6 and C2) of the timer circuit formed by the resistor R6 and the capacitor C2. During the lock time, a current is supplied to the motor. Even if the movement is stopped by a slight catch, if the movement starts again within the lock time, the motor M can continue to move to the last standing position or the storage position. The length of the lock time is optimally designed by the values of the capacitor C2 and the resistor R6.”)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 4-6, 8-10 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ichikoh (JP 2001287592).
With respect to claim 4, Ichikoh discloses the passive timing circuit as claimed in claim 1, but fails to disclose wherein the capacitive network comprises a plurality of capacitors in parallel. It is well known in the art to substitute a single transistor for multiple transistors in parallel. It would be obvious would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to replace a single transistor with multiple transistors in parallel for the purpose of achieving a particular value. Furthermore, this is considered an obvious expedient design choice.
With respect to claim 5, the circuit above produces the passive timing circuit as claimed in claim 1, but fails to disclose wherein the capacitive network comprises a capacitance of approximately 10,400 pF. This is considered an obvious expedient design choice.
With respect to claim 6, the circuit above produces the passive timing circuit as claimed in claim 5, but fails to disclose wherein the time period is between 1 and 11 minutes. This is deemed obvious expedient and would be achieved by routine experimentation.
With respect to claim 8, Ichikoh discloses the passive timing circuit as claimed in claim 7, but fails to disclose wherein the resistor comprises a resistance of approximately 56 kQ. This is deemed obvious expedient and would be achieved by routine experimentation.
With respect to claim 9, the circuit above produces the passive timing circuit as claimed in claim 8, but fails to disclose wherein the resistor comprises variable resistor so that the timing period can be dynamically adjusted accordingly. . It is well known in the art to substitute a single resistor for a variable resistor. It would be obvious would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to replace a single resistor with a variable for the purpose of achieving a particular value. Furthermore, this is considered an obvious expedient design choice and a particular value would be achieve by routine experimentation. (See, for example US 9220157; col 30 lines 48-57)
With respect to claim 10, the circuit above produces the passive timing circuit as claimed in claim 7, but fails to disclose wherein the resistor has a power rating of approximately 0.25 W. Selection of a particular resistor is seen as obvious expedient design choice and a particular value would be achieve by routine experimentation.
With respect to claim 13, Ichikoh produces the method as claimed in claim 12, but fials to disclose wherein a capacitance of approximately 10,000 pF is configured to provide a time period of approximately eight minutes. This is deemed obvious expedient and would be achieved by routine experimentation.
Response to Arguments
Applicant's arguments filed 8/13/2025 have been fully considered but they are not persuasive.
With respect to applicant’s argument that the relay is operated by the optocoupler, the Examiner points out the relay (2) is operated by the optocoupler (Photocopler PC, for controlling Transistor Tr which controls the relay circuit 2 in figure 1),
With respect to applicant’s argument in Ichikoh, power builds to charge C1 and activates RCoil 1, where the optocoupler drives the motor directly not via a relay as provided in the present invention, the Examiner points out that control is not limited to the initial control of the optocoupler. As such the coupling of the optocoupler to the switch of that controls the relay is sufficient to render control of the optocoupler.
With respect to applicant’s argument concerning a dedicated external voltage source, a dedicated external voltage source is not required by the claim language.
With respect to applicant’s argument Ichikoh is an active uses an active supplied voltage source, the examiner disagrees. The claim in Ichikoh shows no active voltage source as the voltage is supplied by the capacitor. Upon further reading of the claim, the applicant should distinctly define what is meant as a passive circuit as the examiner currently reads the circuit in Ichikoh as passive and therefore reading on the claim language. Furthermore, an RC circuit in series with an optocoupler is not considered inventive in light of the cited inventions.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Newman (US 9220157): (col. 30, lines 48-57) Teaching a timer circuit (820 in figure 17) for an optocoupler ( optocouplers U835A, U835B in figure 17), whereby the timing circuit includes a variable resistor (potentiometer R826) for dynamically adjusting the timing of the timing circuit. )
Song (CN 103887762)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAREEM E ALMO whose telephone number is (571)272-5524. The examiner can normally be reached M-F (8:00am-4:00pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached on M-F (8:00am-4:00pm). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KHAREEM E ALMO/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849