DETAILED ACTION
This office action is in response to the Amendments filed 29 April 2026. Claims 1-12 are pending in this application. Claims 8-10 are withdrawn from consideration and Claims 11 and 12 are newly added. Claims 1-7 and 11-12 are examined in this Office Action.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-4, 11-12 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by Lin et. al (US 6,355,960 B1) (newly cited).
Regarding Claim 1, Lin discloses (as shown in Figs. 5, 10) A protection element, comprising:
switching elements formed by n-type MOSFETs ([Col. 1 Lines 26-27] One familiar driver circuit is an inverter formed by two NMOS FETs) and arranged in a first direction (Col. 4 Lines 32-34] a driver and the protection FETs 40, 41 will ordinarily comprise an array of these cells, and FIG. 5 shows part of an adjacent cell) in a state connected in parallel to each other ([Col. 2 Lines 45-47] several driver FETs are formed in a row and column array and connected to conduct in parallel to provide a selected output current at the pad.);
and a back gate guard ring surrounding the switching elements, ([Col. 4 Line 50] A frame 27 surrounds the two FETs.) (See Fig. 10)
wherein: the switching elements include a first switching element (See An. Fig. 10; SE1), a second switching element (See An. Fig. 10; SE2), a third switching element (See An. Fig. 10; SE3), and a fourth switching element (See An. Fig. 10; SE4) that are arranged in this order; (See An. Fig. 10) ([Col. 4 Lines 34-36] The two cells are identical and the reference characters for the two cells are the same except for the subscript "a" in the partial cell.)
the back gate guard ring (27) includes a first portion (See An. Fig. 10; FP1) located adjacent to the first switching element (SE1) at an opposite side of the second switching element (SE2), (See An. Fig. 10, showing the first frame portion FP1 on the left of the first switching element SE1, and the second switching element SE2 on the right side of the first switching element SE1)
a second portion (See An. Fig. 10; FP2) located between the second switching element (SE2) and the third switching element (SE3), (See An. Fig. 10, showing the second frame portion FP2 between the second switching element SE2 and the third switching element SE3)
and a third portion (See An. Fig. 10; FP3) located adjacent to the fourth switching element (SE4) at an opposite side of the second switching element (SE2); (See An. Fig. 10, showing the third frame portion FP3 on the right of the fourth switching element SE4, and the second switching element SE2 on the left side of the fourth switching element SE4)
a source ([Col. 4 Lines 44-45] the two source diffusions 20 …) of the first switching element (SE1) is located closer to the first portion (FP1) than a gate ([Col. 4 Line 40] gates 15 …) of the first switching element (SE1); (See An. Fig. 10, showing the source 20 closer to the first portion FP1 than the gate 15)
and a source ([Col. 4 Lines 44-45] the two source diffusions … 22) of the second switching element (SE2) is located closer to the second portion (FP2) than a gate ([Col. 4 Line 40] gates … 16) of the second switching element (SE2); (See An. Fig. 10, showing the source 22 closer to the second portion FP2 than the gate 16)
and a source ([Col. 4 Lines 44-45] the two source diffusions 20 …) of the third switching element (SE3) is located closer to the second portion (FP2) than a gate ([Col. 4 Line 40] gates 15 …) of the third switching element (SE3); (See Fig. 5, showing the source 20a closer to the second portion FP2 than the gate 15a)
and a first element isolation zone ([Col. 4 Line 51] field oxide 28) is provided between the source of the second switching element (SE2) and the second portion (FP2), ([Col. 4 Lines 50-51] A frame 27 surrounds the two FETs. It is spaced from the components inside the frame by a field oxide 28)
and a second element isolation zone ([Col. 4 Line 51] field oxide 28) is provided between the source of the third switching element (SE3) and the second portion (FP2). ([Col. 4 Lines 50-51] A frame 27 surrounds the two FETs. It is spaced from the components inside the frame by a field oxide 28)
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Regarding Claim 2, Lin further discloses (as shown in Figs. 5, 10) wherein a source ([Col. 4 Lines 44-45] the two source diffusions … 22) of the fourth switching element (SE4) is located closer to the third portion (FP3) than a gate ([Col. 4 Line 40] gates … 16) of the fourth switching element (SE4). (See An. Fig. 10, showing the source 22 closer to the fourth portion FP4 than the gate 16)
Regarding Claim 3, Lin further discloses (as shown in Figs. 5-6, 10) wherein a distance between the source (20) of the first switching element (SE1) and the first portion (FP1), a distance between the source (22) of the second switching element (SE2) and the second portion (FP2), a distance between the source (20) of the third switching element (SE3) and the second portion (FP2), and a distance between the source (22) of the fourth switching element (SE4) and the third portion (FP3) are equal to one another. ([Col. 4 Lines 34-36] The two cells are identical) ([Col. 5 Lines 1-2] The frame 27 and the field oxide 28 are also formed as a mirror structure.)
Regarding Claim 4, Lin further discloses (as shown in Figs. 5-6, 10) wherein the second portion (FP2) has the form of a single strip extending in a direction orthogonal to the first direction of the switching elements, in plan view. (See An. Fig. 10, showing the second portion is a single strip extending from top to bottom, while the first direction extends left to right)
Regarding Claim 11, Lin further discloses (as shown in Figs. 5, 10) wherein: in the first direction, a length of the first element isolation zone is equal to a length of the second element isolation zone. ([Col. 5 Lines 1-2] The frame 27 and the field oxide 28 are also formed as a mirror structure.)
Regarding Claim 12, Lin further discloses (as shown in Figs. 5, 10) wherein a distance between the second switching element (SE2) and the third switching element (SE3) is greater than a distance between the first switching element (SE1) and the second switching element (SE2). ([Col. 2 Lines 31-34] The driver FET comprises two parallel FETs formed symmetrically about a common (shared) drain diffusion) (See An. Fig. 10, showing a shared drain between the first and second switching elements, but show the second and third switching elements separated from each other by the field oxides 28 and the frame 27)
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 5-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin as applied to claim 1 above, and further in view of Wu et. al (US 2005/0082619 A1) (of record)
Regarding Claim 5, Lin fails to disclose wherein the switching elements each include a separate drain ([Col. 4 Line 39] diffusion 21 that forms a common drain for the two FETs).
However, it would have been obvious before the effective filing date of the application to have the switching elements each have a separate drain based on the teachings of Lin and Wu. Lin further teaches that some of the transistors share common drains ([Col. 2 Lines 31-34] The driver FET comprises two parallel FETs formed symmetrically about a common (shared) drain diffusion)
Wu is similarly directed to an ESD device composed of multiple fingers. ([0037] In another yet embodiment, a multi-fingered deep submicron ESD protection structure includes at least two fingers.) Wu teaches that adding a small resistance to the in series with the drain can help to balance the current distribution during an ESD event, thereby producing a more balanced current distribution. ([0027] When the transistors are combined in parallel, the current flow across all of the transistors should be balanced. This balancing may be accomplished by providing a relatively small resistance in series with the drain 114 (of each transistor). This resistance helps balance the current through the device 100 during ESD events by preventing one area of the device 100 from absorbing all of the ESD energy.)
Wu further teaches that while the fingers share a common drain, it is understood that the fingers may have separate drains ([0037] In the present example, the fingers share a drain, but it is understood that the fingers may each have a separate drain.) It would have been obvious to a person having ordinary skill in the art before the effective filing date of the application to add a small resistance in series with the drains of the ESD device in order to balance the current flow, and that this can be accomplished with an arrangement featuring separate drains.
Regarding Claim 6, Lin in view of Wu further discloses (as shown in Fig. 5-6, 10) wherein the drain (21), the gate (15, 16), and the source (20, 22) of each of the switching elements are arranged in an arrangement direction of the switching elements. (See An. Fig. 10, showing the drain (20), the gate (15, 16), and the source (20, 22) arranged in the left-right direction, and also showing the transistors arranged in the left-right direction)
Regarding Claim 7, Lin in view of Wu further discloses (as shown in Fig. 5-6, 10) wherein: the source (20), the gate (15), and the drain (21) of the first switching element (SE1) are arranged in this order from the first portion (FP1) toward the second portion (FP2) in the arrangement direction of the switching elements; (See An. Fig. 10A, showing the source 20 of the first switching element SE1 is closer to the first portion of the frame FP1; and the drain 21 of the first switching element SE1 is closer to the second portion of the frame FP2)
the drain (21), the gate (16), and the source (22) of the second switching element (SE2) are arranged in this order from the first portion (FP1) toward the second portion FP2) in the arrangement direction of the switching elements; (See An. Fig. 10, showing the drain 21 of the second switching element SE2 is closer to the first portion of the frame FP1; and the source 22 of the second switching element SE2 is closer to the second portion of the frame FP2)
the source (20), the gate (15), and the drain (21) of the third switching element (SE3) are arranged in this order from the second portion (FP2) toward the third portion (FP3) in the arrangement direction of the switching elements; (See An. Fig. 10, showing the source 20 of the third switching element SE3 is closer to the second portion of the frame FP2; and the drain 21 of the third switching element SE3 is closer to the third portion of the frame FP3)
and the drain (21), the gate (16), and the source (22) of the fourth switching element (SE4) are arranged in this order from the second portion (FP2) toward the third portion (FP3) in the arrangement direction of the switching elements. (See An. Fig. 10, showing the drain 21 of the fourth switching element SE4 is closer to the second portion of the frame FP1; and the source 22 of the fourth switching element SE4 is closer to the third portion of the frame FP3)
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JASON JAMES GREAVING whose telephone number is (703)756-5653. The examiner can normally be reached 7:30am - 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571)270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JASON JAMES GREAVING/ Examiner, Art Unit 2893
/Britt Hanley/ Supervisory Patent Examiner, Art Unit 2893
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