DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for domestic benefit under 35 U.S.C. 365(c) with PCT/JP2021/040954 which in turn claims foreign priority under 35 U.S.C. 119 (a)-(d) with JP2020-207646. The certified copy of foreign priority has been filed with the Office on June 7, 2023.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on June 7, 2023 and June 12, 2024 were filed in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-6, 8-10 13-15, 18, 20 are rejected under 35 U.S.C. 102(a)(1) & (a)(2) as being anticipated by Mathai et al. US 20200343695.
Regarding Claim 1, Mathai teaches A surface emitting laser device (Fig. 1A) comprising:
a first wiring group (Fig. 1A, 120, 114 Paragraph 0018 “The optical module 100 includes a plurality of electrical conductors 114 (e.g., identified individually as electrical conductors 114a-114d)”) including a plurality of first wiring lines (Fig. 1A, 120a-120d, 114a-114d) insulated from each other (The plurality of first wiring lines are insulated from each other by the 132 Paragraph 0025 “In some examples, an optical underfill layer 132”);
a second wiring group (Fig. 1A, 120, 114 Paragraph 0022 “However, in other examples, the first pads 120 can include separate pads (e.g., two pads) configured to be coupled to the electrical conductors 114 and top-emitting VCSELS 108 respectively. The separate pads can be electrically coupled via conductive traces extending along or through the interposer 104.” The second wiring group are the conductive traces that extend along or through the interposer to the separate pads of 120) including a plurality of second wiring lines (As Paragraph 0022 above stated each of the separate pads has a conductive trace. Each one of these individual conductive traces are the plurality of second wiring lines) insulated from each other (The plurality of second wiring lines are insulated from each other due to the interposer 104);
a first board provided (Fig. 1, 102) with a plurality of light emitting units (Fig. 1A, 108a-108d) electrically connected to any one of the plurality of first wiring lines (Paragraph 0023 “The substrate 102 can also include conductive traces 128. The second pads 122 can be electrically coupled to an ASIC 130 or other suitable chip via the traces 128 (identified individually as traces 128a-128d) such that the ASIC 130 or other suitable chip can send electrical signals to respective top-emitting VCSELs 108 via the electrical paths between the substrate 102 and interposer 104 formed by the electrical conductors 114, pads (e.g., first and second pads 120 and 122, traces, and contacts 116.”) and electrically connected to any one of the plurality of second wiring lines (Paragraph 0022 “The first pads 120 can be single pads (e.g., continuous pads) extending along the interposer 104 and attached to both the electrical conductors 114 and the top-emitting VCSELs 108. However, in other examples, the first pads 120 can include separate pads (e.g., two pads) configured to be coupled to the electrical conductors 114 and top-emitting VCSELS 108 respectively. The separate pads can be electrically coupled via conductive traces extending along or through the interposer 104”.); and
a second board (Fig. 1A, 104) disposed to face the first board (Fig. 1A shows the second board facing the first board) and provided with the first wiring group and/or the second wiring group. (Fig. 1A shows the second board is provided with the first wiring group and the second wiring group)
Regarding Claim 2, Mathai teaches each of a plurality of the light emitting units is joined to a corresponding wiring line (Fig. 1A, 124a-124d) of one wiring group provided on the second board (Fig. 1A shows 124a-124d is provided on the second board) among the first wiring group and the second wiring group. (Fig. 1A shows the corresponding wiring line is among the first and second wiring group)
Regarding Claim 3, Mathai teaches both the first wiring group and the second wiring group are provided on the second board. (Fig. 1A shows that the first wiring group is on the second board, 120 is part of the first wiring group and is on 104. Paragraph 0022 “However, in other examples, the first pads 120 can include separate pads (e.g., two pads) configured to be coupled to the electrical conductors 114 and top-emitting VCSELS 108 respectively. The separate pads can be electrically coupled via conductive traces extending along or through the interposer 104.”)
Regarding Claim 4, Mathai teaches each of the plurality of light emitting units has a mesa protruding on the second board side, (Fig. 1A shows each of the plurality of light emitting units has a mesa, 108, protruding on the second board side, )
a first electrode (Fig. 1A, 116a-116d) provided at a top portion of the mesa of each light emitting unit (Paragraph 0018 “Each of the electrical conductors 114 forms a respective electrical path between electrical contacts 116 (e.g., identified individually as electrical contacts 116a-116d) of respective top-emitting VCSELs 108 and the substrate 102.”) among the plurality of light emitting units is joined via a first bump (Fig. 1A, 126) to each of the first wiring lines corresponding to the each light emitting unit (Paragraph 0024 “As illustrated, the top-emitting VCSELs 108 (or top-entry photodetectors) can be mechanically coupled to respective first pads 120 via soldering (e.g., solder bumps 126 and corresponding solder reflow techniques).”), and
a second electrode (Fig. 1A, 122a-d) provided in a peripheral portion of each light emitting unit among the plurality of light emitting units on the first board (Fig. 1A shows that 122 is provided in a peripheral portion of the light emitting units among the plurality of light emitting units on the first board) is joined via a second bump (Fig. 1A, 126 attached to 122) to each of the second wiring lines corresponding to each light emitting unit. (Fig. 1A shows that each of the second wiring lines corresponds to the light emitting unit is joined to the second electrode via a second bump.)
Regarding Claim 5, Mathai teaches the first wiring group or the second wiring group is provided on the second board. (Fig. 1A shows that the first wiring group is on the second board, 120 is part of the first wiring group and is on 104. Paragraph 0022 “However, in other examples, the first pads 120 can include separate pads (e.g., two pads) configured to be coupled to the electrical conductors 114 and top-emitting VCSELS 108 respectively. The separate pads can be electrically coupled via conductive traces extending along or through the interposer 104.”)
Regarding Claim 6, Mathai teaches each of the plurality of light emitting units has a mesa protruding on the second board side, (Fig. 1A shows each of the plurality of light emitting units has a mesa, 108, protruding on the second board side,)
the first wiring group is provided on the second board, (Fig. 1A shows that 120 of the first wiring group is provided on the second board) and the second wiring group is provided on the first board (Fig. 1A shows that 114 of the second wiring group is provided on the first board),
a first electrode (Fig. 1A, 116a-116d) provided at a top portion of the mesa of each light emitting unit (Paragraph 0018 “Each of the electrical conductors 114 forms a respective electrical path between electrical contacts 116 (e.g., identified individually as electrical contacts 116a-116d) of respective top-emitting VCSELs 108 and the substrate 102.”) among the plurality of light emitting units is joined via a first bump (Fig. 1A, 126) to each of the first wiring lines corresponding to the each light emitting unit (Paragraph 0024 “As illustrated, the top-emitting VCSELs 108 (or top-entry photodetectors) can be mechanically coupled to respective first pads 120 via soldering (e.g., solder bumps 126 and corresponding solder reflow techniques).”), and
each second wiring line among the plurality of second wiring lines is joined via a second bump to a wiring line (Fig. 1A, 114) provided on the second board (Fig. 1A shows that 114 is on the second board) and corresponding to each second wiring line. (Paragraph 0022 “However, in other examples, the first pads 120 can include separate pads (e.g., two pads) configured to be coupled to the electrical conductors 114 and top-emitting VCSELS 108 respectively. The separate pads can be electrically coupled via conductive traces extending along or through the interposer 104.”)
Regarding Claim 8, Mathai teaches a conductor (Fig. 1A, 116 Paragraph 0021 “are electrically coupled to one of the electrical contacts 116”) that is disposed along at least a part of the first wiring group and/or the second wiring group and insulated from both the first wiring group and the second wiring group. (Fig. 1A shows that 116a-116d are disposed along the first and second wiring group and are insulated from both groups.)
Regarding Claim 9, Mathai teaches the conductor is provided on the first board and/or the second board. (Fig. 1A shows 116 is on the VCSEL which is provided on the first board)
Regarding Claim 10, Mathai teaches the conductor is connected to a reference potential. (Paragraph 0021 “The pads as described herein (e.g., the first and second pads 120 and 122) can be, for example, solder attachment pads. Each of the first pads 120 are electrically coupled to one of the electrical contacts 116 (e.g., one of the anode or cathode contacts) of a respective top-emitting VCSEL 108 (e.g., via corresponding or matching pads or traces of the top-emitting VCSEL 108). The electrical metal pillars 118 thus form electrical paths between the respective electrical contacts 116 on top sides of the top-emitting VCSELs 108 and the substrate 102 thereunder. As discussed above, the optical module 100 includes other electrical contacts 116 (e.g., the other of the anode or cathode contacts) of the pair of electrical contacts (not shown in FIG. 1A-1C or 2A-2C). These electrical contacts 116 are also electrically coupled to the substrate 102 via separate electrical conductors 114 extending between the substrate 102 and interposer 104.” There are two 116 on the VCSEL one that is the cathode and one is the anode. The cathode is attached to the reference potential)
Regarding Claim 13, Mathai teaches a third wiring line (Fig. 1A, 124) that is provided on the second board and insulated from both the first wiring group and the second wiring group, (Fig. 1A shows that 124 is insulated from both the first and second wiring group) wherein the conductor is provided on the first board, (Fig. 1A shows the conductor is on the first board through the VCSEL) and the conductor and the third wiring line are joined via a bump. (Fig. 1A shows that 124 connects to the VCSEL via a bump 126 and the VCSEL is connected to the conductor 116 so the conductor is connected to the third wiring line via a bump)
Regarding Claim 14, Mathai teaches the third wiring line is provided along at least a part of the first wiring group and/or the second wiring group. (Fig. 1A shows that the third wiring line is provided along part of the first and/or second wiring group.)
Regarding Claim 15, Mathai teaches a third wiring line (Fig. 1A 128 Paragraph 0023 “The substrate 102 can also include conductive traces 128.”) that is provided on the first board and/or the second board (Fig. 1A shows 128 is provided on the first board) and insulated from both the first wiring group and the second wiring group, (Fig. 1A shows that 128 is insulated from the first and second wiring group) wherein the third wiring line is provided along at least a part of the first wiring group and/or the second wiring group. (Fig. 1A shows the third wiring line is provided along the first and second wiring group)
Regarding Claim 18, Mathai teaches both the first wiring group and the second wiring group are connected to an electronic circuit. (Paragraph 0023 “The substrate 102 can also include conductive traces 128. The second pads 122 can be electrically coupled to an ASIC 130 or other suitable chip via the traces 128 (identified individually as traces 128a-128d) such that the ASIC 130 or other suitable chip can send electrical signals to respective top-emitting VCSELs 108 via the electrical paths between the substrate 102 and interposer 104 formed by the electrical conductors 114, pads (e.g., first and second pads 120 and 122, traces, and contacts 116. When the optical module 100 includes top-entry photodetectors, electrical signals converted from optical signals by the top-entry photodetectors can be sent to the ASIC 130 or other suitable chip via the electrical paths between the substrate 102 and interposer 104 for further processing.”)
Regarding Claim 20, Mathai teaches a conductor that is disposed along at least a part of the first wiring group and/or the second wiring group and insulated from both the first wiring group and the second wiring group.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 11, 17 are rejected as being unpatentable over 35 U.S.C. 103 over Mathai in view of US 20150340841.
Regarding Claim 11, Mathai does not teach the conductor is metal or an alloy.
However,
Joseph teaches the conductor is metal or an alloy (Paragraph 0058 “The p-metal contact layer 120 ”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the conductor as taught by Mathai by having it be made of a metal or an alloy as disclosed by Han. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) MPEP 2144.07. The reference has demonstrated a metal is suitable to be a contact layer on a VCSEL.
Regarding Claim 17, Mathai teaches each of the light emitting units includes a layered structure in which a first reflector, an active layer, and a film reflector are layered in this order on the first board. (Paragraph 0018 “Typically, top-emitting VCSELs include one or more active layers sandwiched between upper and lower mirror layers built or otherwise formed on the support substrate.”)
Mathai does not teach that the reflectors are made of a multilayer film.
However,
Joseph teaches the reflectors are made of a multilayer film (Paragraph 0032 “As is understood by those skilled in the art, the wavelength of emission is substantially determined according to the choice of materials used to create lower DBR 104 and upper DBR 108,”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the reflectors as taught by Mathai by having the reflectors be made of a multilayer film as disclosed by Joseph. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) MPEP 2144.07. The reference has demonstrated a multilayer reflector is suitable to be a reflector in a VCSEL.
Claims 12, 16 are rejected as being unpatentable over 35 U.S.C. 103 over Mathai in view of Han et al. US 20200067278.
Regarding Claim 12, Mathai does not teach the conductor is a semiconductor containing impurities.
However,
Han teaches the conductor is a semiconductor containing impurities. (Paragraph 0073 “or example, the first contact layer 25 may be an n contact layer”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the conductor as taught by Mathai by having it be made of a semiconductor containing impurities as disclosed by Han. The selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sinclair & Carroll Co. v. Interchemical Corp., 325 U.S. 327, 65 USPQ 297 (1945) MPEP 2144.07. The reference has demonstrated a semiconductor containing impurities is suitable to be a contact layer on a VCSEL.
Regarding Claim 16, Mathai does not teach a total of a number of the plurality of first wiring lines and a number of the plurality of second wiring lines is less than twice a number of the light emitting units.
However,
Han teaches a total of a number of the plurality of first wiring lines and a number of the plurality of second wiring lines is less than twice a number of the light emitting units (Fig. 13 shows 20 first and second wires and 100 light emitting units. 20 is less than 200)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the surface emitting laser device as taught by Mathai by having the number of the first and second wiring lines total be less than twice the number of light emitting units as disclosed by Han. One of ordinary skill in the art would have been motivated to make this modification in order to give control of which light emitting units to illuminate. (Han Paragraph 0103 “When a voltage is applied to any one of the first wires W10 by the first driving unit D10 and a voltage is applied to any one of the second wires W20 by the second driving unit D20, light may be emitted by a VCSEL at a point where a first wire W10 and a second wire W20 to which voltages are applied.”)
Claims 12, 16 are rejected as being unpatentable over 35 U.S.C. 103 over Mathai in view of another embodiment of Mathai.
Regarding Claim 19, Mathai teaches the second board contains an insulating material, (Paragraph 0014 “The interposer 104 can be formed out of glass or other suitable material(s) with a relatively high-index of refraction.”)
Mathai does not teach an electronic circuit is disposed on the second board or in the second board, and the first wiring group and the second wiring group are connected to the electronic circuit.
However,
Another embodiment of Mathai teaches an electronic circuit is disposed on the second board or in the second board, and the first wiring group and the second wiring group are connected to the electronic circuit. (Paragraph 0035 “The separate pads can be electrically coupled via conductive traces extending along or through the interposer 204.”)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the second board as taught by Mathai by adding the electronic circuit disposed on or in the second board as disclosed by another embodiment of Mathai. One of ordinary skill in the art would have been motivated to make this modification in order to provide additional locations where the light emitting units can connect to power.
Mathai teaches a conductor (Fig. 1A, 116 Paragraph 0021 “are electrically coupled to one of the electrical contacts 116”) that is disposed along at least a part of the first wiring group and/or the second wiring group and insulated from both the first wiring group and the second wiring group. (Fig. 1A shows that 116a-116d are disposed along the first and second wiring group and are insulated from both groups.)
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Mathai does not teach each of the plurality of second wiring lines includes: a first portion provided along the first board; and a second portion provided along a pedestal portion provided on the first board, and the second portion of each of the second wiring lines is joined via the second bump to the wiring line that is corresponding.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Yu et al. US 20200014169 teaches many features found in Claim 1.
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/STEPHEN SUTTON KOTTER/ Examiner, Art Unit 2828 /MINSUN O HARVEY/Supervisory Patent Examiner, Art Unit 2828