Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/26/2026 has been entered.
Response to Amendments
This Non-Final Office Action is in response to the amendments filed on 02/04/2026. In which, claims 1, 12, and 15 have been amended, no claims have been cancelled, claims 16 and 17 have been added, and claims 1 – 17 remain pending in the application.
Response to Amendment
The amended filed 02/04/2026 has been entered. See above in response to the amendments.
Response to Arguments
Remarks regarding rejections under 35 U.S.C § 103 filed 02/04/2026 Applicant’s
amendment to claims 1, 12, and 15 arguments are carefully considered and are persuasive. However, upon further consideration, arguments are moot in view of new found prior art.
With respect to applicant’s argument to the remaining dependent claims 2 -10, 13-14 and 16-17 of the remark, the applicant is relying on the newly added amendments of the independent claim 1, 12, and 15. Please see examiner’s response above and the detail of the rejection below.
Claims objections
Regarding claim 11 is objected to the claim in line 4 recites limitations “the system according to claim 1…” it should be written in it independent form. Appropriate correction is required.
Claim Rejections - 35 USC § 102
The factual inquiries for establishing a background for determining obviousness
under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating
obviousness or nonobviousness.
Claims 1, 11-12, and 15-17 are rejected under 35 U.S.C. 102 (a)(1) as
being anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Areno et al. (US-20200084229-A1 hereafter Areno).
Regarding claim 1 Areno disclose a system for actively monitoring and securing a compute- and data-intensive electronic device (CDI) (see Areno par. 0034-0037: “security system 100 may include a first host device 120 (CDI).. the HRoT device 110 may monitor the security of the first and second devices 120, 130 over the second connection 114. The HRoT device 110 may load and execute a security monitoring application to monitor the host devices regarding its hardware and software for any security concerns.”), said system comprising:
a trusted execution environment electronic module (TEE) including first processing circuitry, implementing at least one monitoring policy rule for controlling the active monitoring of the CDI, the CDI including second processing circuitry different from the first processing circuitry; (see Areno par.0037: “The trusted element 150 (TEE) may provide a new security policy to the HRoT device 110. Then, the HRoT device 110 may revise the security policy stored in the HRoT device 110 with the new security policy from the trusted element 15”.) )
an interceptor electronic module (IC) separate from and outside of the TEE, the IC comprising at least one monitoring device configured to monitor said CDI at a corresponding hardware level tapping point of the CDI to obtain a corresponding monitoring information element from the CDI (see Areno par.0037 : “the HRoT device 110 (IC) may monitor the security of the first and second devices 120…the HRoT device 110 may load and execute a process to work with applications executing on the first and second host devices 120, 130 to perform monitoring functions. The monitoring functions may be implemented through a ‘tamper detection mechanism’ by intercepting events including, but not limited to, voltage changes, clock skewing, and Joint Test Action Group (JTAG) connection events (hardware level tapping point)… the security monitoring application may receive inputs or events from a voltage sensor of the first and second host devices 120,”), said IC being configured to provide, to said TEE monitoring information based on the obtained monitoring information element (see Areno par.0038: “the HRoT device 110 may send the captured current snapshot to the trusted element 150 where the snapshot is analyzed. The trusted element 150 may determine a cause of the security attack and develop a counter-attack measure to address the security attack.”,),
wherein the lC is subordinated to said TEE, and the TEE configures said at least one monitoring device of the IC based on the at least one monitoring policy rule implemented by the TEE. (See Areno par.0038: “the trusted element 150 may distribute the counter-attack measure to any devices in the network to which the trusted element 150 is connected. For example, the trusted element 150 may apply the counter-attack measure to the first and second devices 120, 130 through the HRoT device 110.”).
Regarding claim 11 Areno discloses a system for secure compute- and data- intensive computing, said system comprising:
the compute- and data-intensive computing electronic device, (see Areno par. 0034: “security system 100 may include a first host device 120”.),
and the system according to claim 1, for actively monitoring and securing the compute- and data-intensive electronic device. (“See Areno par.0034-38: ““The trusted element 150 (TEE) may provide a new security policy to the HRoT device 110. Then, the HRoT device 110 may revise the security policy stored in the HRoT device 110 with the new security policy from the trusted element 15… the HRoT device 110 (IC) may monitor the security of the first and second devices 120…the HRoT device 110 may load and execute a process to work with applications executing on the first and second host devices 120, 130 to perform monitoring functions. The monitoring functions may be implemented through a ‘tamper detection mechanism’ by intercepting events including, but not limited to, voltage changes, clock skewing, and Joint Test Action Group (JTAG) connection events (hardware level tapping point)… the security monitoring application may receive inputs or events from a voltage sensor of the first and second host devices 120,.. the HRoT device 110 may send the captured current snapshot to the trusted element 150 where the snapshot is analyzed. The trusted element 150 may determine a cause of the security attack and develop a counter-attack measure to address the security attack.”).
Regarding claim 12, is a method claim that recites similar limitations as the system claim 1 and is rejected based on the same rational as claim 1.
Regarding claim 15, is directed to a computer-readable medium, reciting the same reasons as set forth in the rejections of claim 1, respectively. Therefore, claim 15 is rejected for the same reasons as set forth in the rejections of claim 1 above, respectively. A non-transitory computer-readable medium storing program code instructions for implementing a method, when said program is executed by processing circuitry (See Areno par.0049: “The system may be implemented, at least in part, via a computer program product, (e.g., in a non-transitory machine-readable storage medium such as, for example, a non-transitory computer-readable medium), for execution by, or to control the operation of, data processing apparatus (e.g., a programmable processor, a computer, or multiple computers). Each such program may be implemented in a high level procedural or object-oriented programming language to work with the rest of the computer-based system… A computer program may be stored on a non-transitory machine-readable medium that is readable by a general or special purpose programmable computer for configuring and operating the computer when the non-transitory machine-readable medium is read by the computer to perform the processes described herein. For example, the processes described herein may also be implemented as a non-transitory machine-readable storage medium, configured with a computer program, where upon execution, instructions in the computer program cause the computer to operate in accordance with the processes.”).
Regarding claim 16 Areno disclose the system of claim 1, Areno further disclose wherein the IC further comprises a sensor to obtain a sensor value from the tapping point of the CDI. (See Areno par.0037: “The monitoring functions may be implemented through a ‘tamper detection mechanism’ by intercepting events including, but not limited to, voltage changes, clock skewing, and Joint Test Action Group (JTAG) connection events. In some embodiments, the security monitoring application may receive inputs or events from a voltage sensor of the first and second host devices 120,”)
Regarding claim 17 Areno disclose the system of claim 1, Areno further teaches wherein the at least one monitoring device is configured to monitor a supply voltage of a CPU of the CDI. (See Areno par.0034: “The host devices 120, 130 may include respective central processing units (CPUs) 122,” par.0037: “The monitoring functions may be implemented through a ‘tamper detection mechanism’ by intercepting events including, but not limited to, voltage changes, clock skewing, and Joint Test Action Group (JTAG) connection events. In some embodiments, the security monitoring application may receive inputs or events from a voltage sensor of the first and second host devices 120,”).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Areno et al. (US-20200084229-A1 hereafter Areno), in view of Goss et al. (US-20160180093-A1 hereafter Goss).
Regarding claim 2 Areno disclose the system according to claim 1 Areno do not explicitly teach however Goss teaches wherein said TEE implements at least one securing policy rule for controlling said active securing, (see Goss par.0051: “the TEE may be implemented using Intel® SGX technology, Intel® TXT technology, or an ARM TrustZone. To this end, implementations may include various hardware, both general-purpose and specialized security hardware, to create a TEE and perform location-based security policy assignment, updating and enforcement operations in such environments.”, par.0052: “security engine 525, which may be configured to create a TEE and execute in such trusted environment, includes a policy and analytics engine 527 and a monitor logic 529.”, and
wherein said IC comprises at least one securing device for acting on said CDI at a corresponding securing point, said at least one securing device being configured by said TEE responsive to said implementing of said at least one securing policy rule and based on said monitoring information. (See Goss par.0052: “monitor logic 529 (interpreted as IC) may be configured to monitor various system contexts, including user behavior, location and environmental information and so forth, and provide such information to PAE 527 to determine whether one or more changes or updates to a given security policy may be appropriate and to be recommended.”).
Therefore, it would have been obvious to one or ordinary skill in the art before the effective filing date of the claim invention to combine the teaching of Areno of claim 1 with Goss teaching “a monitoring logic can observe user behaviors, environmental factors and other contextual factors. This data may then be used to determine whether a security policy for the device is to be updated. In an embodiment, sensor and input device data can be collected passed to be classified via one or more context classifiers. In tum, a policy and analytics engine (PAE) receives classified information and uses it to determine whether a current policy is to be manipulated in a given manner.", (see Goss par.0018).
Regarding claim 13, is directed to a method, reciting the same reasons as set forth in the rejections of claim 2, respectively. Therefore, claim 13 is rejected for the same reasons as set forth in the rejections of claim 2 above, respectively.
Claims 3 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Areno et al. (US-20200084229-A1 hereafter Areno), in view of Goss et al. (US-20160180093-A1 hereafter Goss), in further view of Lal et al. (US-20200134180-A1 hereafter Lal).
Regarding claim 3 Areno disclose the system according to claim 1. Areno further teaches and
configure said at least one monitoring device responsive to said implementing said at least one updated monitoring policy rule and/or configure said at least one securing device responsive to said implementing of said at least one updated securing policy rule and based on said monitoring information (See Areno par.0038: “the HRoT device 110 may use a pre-defined interface, such as Web Services, provided by the first and second devices 120, 130 to capture the snapshots. When a security attack is detected at the first or second device 120, 130, the HRoT device 110 may capture a current snapshot of the devices 120, 130. Depending on the location and/or characteristics of the security attack, HRoT device 110 may send the captured current snapshot to the trusted element 150 where the snapshot is analyzed. The trusted element 150 may determine a cause of the security attack and develop a counter-attack measure to address the security attack. In addition, the trusted element 150 may distribute the counter-attack measure to any devices in the network to which the trusted element 150 is connected. For example, the trusted element 150 may apply the counter-attack measure to the first and second devices 120, 130 through the HRoT device 110. Furthermore, in response to the security attack, the HRoT device 110 may overwrite the first and/or second devices 120, 130 with the respective stable snapshot captured during their stable state such that the first and/or second devices 120, 130 are resumed to their respective stable state.”).
Areno do not explicitly teach however Goss teaches wherein said TEE is configured to update said at least one monitoring policy rule based on said monitoring information delivering at least one updated monitoring policy rule and/or to update said at least one securing policy rule based on said monitoring information delivering at least one updated securing policy rule, (see Goss par. 0050: “the TEE may be implemented using Intel® SGX technology, implementations may include various hardware, both general-purpose and specialized security hardware, to create a TEE and perform location-based security policy assignment, updating and enforcement operations in such environments.”.),
It would have been obvious to someone of ordinary skill in the art before the
effective filing date of the claimed invention to have combined Areno teaching of the system of claim 1, with Goss teaching “the TEE may be implemented using Intel® SGX technology, implementations may include various hardware”. (see Goss par.0042)
Areno in view Goss fail to explicitly teach however Lal teaches and
wherein said TEE is further configured to:
implement said at least one updated monitoring policy rule and/or said at least one updated securing policy rule (see Lal par.0042: “monitoring software is to run inside a TEE. The monitoring software is to receive
statistics from the hardware accelerator for analysis of patterns. In some embodiments, the monitoring software is to apply a policy that is model specific. In implementation,
each model owner is not required to write their own detector. A generic software may be applied, wherein the model owner may specify a policy for software monitor, and thus the model owner is not burdened with providing data other than the policy to be implemented and enforced.”);
It would have been obvious to someone of ordinary skill in the art before the
effective filing date of the claimed invention to have combined Areno in view of Goss teaching describe above with Lal teaching “While a white list of authorized users or a trusted channel between input source and CPU may not implemented, data patterns can be monitored for anomalous input requiring further analysis, a TEE can be provided for policy enforcement and advance analysis, and a trusted channel between the CPU and TEE can be implemented such that a hardware monitoring stack can be sampled with integrity.”
Regarding claims 14 is directed to a method, reciting the same reasons as set forth in the rejections of claim 3, respectively. Therefore, claim 14 is rejected for the same reasons as set forth in the rejections of claim 3 above, respectively.
Claims 4, 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Areno et al. (US-20200084229-A1 hereafter Areno), in view of Avetisov et al. (US-10764752-B1 hereafter Avetisov).
Regarding claim 4 Areno disclose the system according to claim 1, Areno fail to disclose however Avetisov teaches further comprising a first bidirectional interface between said TEE and said IC,
said TEE being configured to send instructions to said IC through said first bidirectional interface to configure said at least one monitoring device and/or said at least one securing device (see Avetisov Col. 25 lines 8-14: “some embodiments may include the API 104 within the CEE 113, within the TEE 103, within an element having a physical interface with the TEE 103 or 10 CEE 113, in firmware of the mobile device 101 (e.g., in a BIOS), or combination thereof. Some embodiments of the TEE 103 may include a monitor to monitor a system bus for requests from an API 104 (or driver), and
said IC being configured for sending said monitoring information to said TEE through said first bidirectional interface. (See Avetisov Col. 25 lines 16-25: “However, regardless of the specific implementation, an API 104 may be configured to provide an interface by which at least some data or results determined within the TEE 103 may be passed to the CEE 113 and by which at least some functions performed within the TEE 103 may be requested by the CEE 113. Further, requests for at least some of those functions may include data or arguments for performing at least some of those functions on the data.”).
It would have been obvious to someone of ordinary skill in the art before the
effective filing date of the claimed invention to have combined Areno teaching of the system of claim 1 with Avetisov teaching “API 104, may be configured to receive requests from elements ( e.g., a given application, module or interface) within the CEE 113 and communicate those requests to an appropriate element ( e.g., a given application, module, or interface) within the TEE 103.”, (see Avetisov Col. 25 lines 26-30).
Regarding claim 9 Areno in view of Avetisov disclose the system according to claim 4, Areno further teaches wherein said IC comprises a data flow engine front-end module configured to intercept at least part of the monitoring information element delivering at least one intercepted monitoring information element (see Areno par.0037: “the HRoT device 110 may load and execute a process to work with applications executing on the first and second host devices 120, 130 to perform monitoring functions. The monitoring functions may be implemented through a 'tamper detection mechanism' by intercepting events including, but not limited to, voltage changes, clock skewing, and Joint Test Action Group (JTAG) connection events.,
wherein said system comprises a second bidirectional interface between said data flow engine front-end module and a data flow engine back-end module of said TEE (see Areno fig 1and par.0037: “The classified communication channel 114 is coupled to an HRoT device 110. In embodiments, the HRoT device 110 and the host devices 120, 130 are required to be authenticated by each other before starting communications. For example, the host devices 120, 130 may need to provide an encrypted key to the HRoT device 110, and the HRoT device 110 may decrypt the key and validate the key by comparing a hash value of the key that is stored in the HRoT device 110…Once authenticated, information can be transferred between the host devices 120, 130 and the HRoT device 110 via the second connection 114.”,
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said data flow engine front-end module being configured to forward, to said data flow engine back-end and through said second bidirectional interface, said at least one intercepted monitoring information element. (See Areno par. 0039: “the second connection 114 may be used to pass secure information between the host devices 120, 130. One example of such a secure exchange is the distribution of keys.”).
Regarding claim 10 Areno in view of Avetisov disclose the system according to claim 9 Areno further teaches wherein said third bidirectional interface is configured to send data at a data rate lower than said data rate of said monitored traffic (see Areno par.0038: “The trusted element 150 may provide a new security policy to the HRoT device 110. Then, the HRoT device 110 may revise the security policy stored in the HRoT device 110 with the new security policy from the trusted element 150. the HRoT device 110 may use a pre-defined interface, such as Web Services, provided by the first and second devices 120,”.), Examiner interpret that the third bidirectional interface send data at a lower than the monitored data because the monitor data is analyzed in real-time which is faster than web services. Examiner interpretation is consistent with applicant instant application par.0040: “IC l00IC requires looping a data path of the CDI 11 OCDI into e.g. the middle of a fiber heads and let the data payload and traffic flow through while it gets analyzed in real-time with no impact on latency or bandwidth for the CDI llOCDI”, and
wherein said second bidirectional interface is configured to send data at a data rate higher than said data rate of said first bidirectional interface. (See Areno par. 0038: “classified or high-security communication channel 114, such as a Peripheral Component Interconnect Express (PCie) bus, connects the devices 120, 130.”, The communication channel 114 function is consistent with applicant’s instant application definition of second bidirectional interface, par.0057: “the second bidirectional interface 100BI2 is a medium speed interface that can be an interface e.g. of the type Ethernet, Media-Independent Interface (MII), Serial Advanced Technology Attachment (SATA), Universal Serial Bus (USB), Peripheral Component Interconnect express (PCI-e)”.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Areno et al. (US-20200084229-A1 hereafter Areno), in view of Avetisov et al. (US-10764752-B1 hereafter Avetisov), in further view of Sweeney et al. (US-20170366476-A1 hereafter Sweeney).
Regarding claim 5 Areno in view of Avetisov teach the system according to claim 4 but fail to explicitly teach However Sweeney teaches wherein said first bidirectional interface is configured to send data at a data rate lower than a data rate of a monitored traffic of said CDI. (See Sweeney par.0065: “switch component 300 can operate without a dedicated flow control channel if the traffic from the packet storage unit 304 to the packet switch unit 302 for any interface I is shaped to an aggregate rate that is lower than the transmission rate of interface I on the packet switch unit 302.”).
It would have been obvious to someone of ordinary skill in the art before the
effective filing date of the claimed invention to have combined Areno in view of Avetisov teaching of the system of claim 4 with Sweeney teaching “by having a smaller number of higher-speed storage pin interfaces between packet switch unit 302 and packet storage unit 304 and mapping each of EQ pin interfaces to one of these higher-speed storage pin interfaces, reduces or eliminates the change of congestion between packet switch unit 302 and packet storage unit 304.”, (see Sweeney par.0042).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Areno et al. (US-20200084229-A1 hereafter Areno), in view of Avetisov et al. (US-10764752-B1 hereafter Avetisov), in further view of Goss et al. (US-20160180093-A1 hereafter Goss).
Regarding claim 6 Areno in view of Avetisov teach the system according to claim 4, Areno in view of Avetisov do not explicitly teach however Goss teaches wherein said IC comprises an analysis module configured to implement a processing of said monitoring information element delivering said monitoring information. (See Goss par.0052: “analytics engine 527 and a monitor logic 529(IC). PAE 527 may generally include one or more classifiers, including multiple sub-classifiers and a master classifier. In tum, monitor logic 529 may be configured to monitor various system contexts, including user behavior, location and environmental information and so forth, and provide such information to PAE 527 to determine whether one or more changes or updates to a given security policy may be appropriate.” par.104: “In Example 23, the processor of one or more of the above Examples comprises a monitor logic to update a first security policy associated with a first location responsive to analysis of user interaction with the system at the first location.”).
It would have been obvious to someone of ordinary skill in the art before the
effective filing date of the claimed invention to have combined Areno in view of Avetisov teaching of the system of claim 4 with Goss teaching “a monitoring logic can observe user behaviors, environmental factors and other contextual factors. This data may then be used to determine whether a security policy for the device is to be updated.”, (see Goss par.0018).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Areno et al. (US-20200084229-A1 hereafter Areno), in view of Avetisov et al. (US-10764752-B1 hereafter Avetisov), in view of Goss et al. (US-20160180093-A1 hereafter Goss), in further view of Xie et al. (US20200274898-A1hereafter Xie).
Regarding claim 7 Areno in view of Avetisov, and Goss disclose the system according to claim 6 but fail to explicitly disclose however Xie teaches further comprising a second bidirectional interface between said analysis module and a message front-end module (see Xie fig 1 and fig 2 par. 0052: “The TEE external interface 125 in FIG. 1 may specifically include a TEE functional interface (TEE functional API) 127 and a TEE client interface (TEE client API) 126. The TEE functional interface 127 provides a set of application programming interfaces (API) to a CA 113 in the REE 120.”)
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said message front-end module being configured to forward, to said analysis module and through said second bidirectional interface, said instructions received from said TEE, said analysis module being configured to configure said at least one monitoring device and/or said at least one securing device based on said instructions, (see Xie par.0052: “The TEE functional interface 127 provides a set of application programming interfaces (API) to a CA 113 in the REE 120. The CA 113 can invoke some TEE services, such as encryption and decryption operations or secure storage, by using the TEE functional interface 127.”
said analysis module being configured to send, to said message front-end
module and through said second bidirectional interface, said monitoring information for further transmission by said message front-end module to said TEE through said first bidirectional interface. (See Xie par. 0052: “An REE communications agent 129 and a TEE communications agent 146 are respectively
deployed in the REE 120 and the TEE 140, to support message exchange between the CA 113 and the TA 115. The REE communications agent 129 and the TEE communications agent 145 work together and secure, by using an underlying message routing mechanism, the message exchange between the CA 113 and the TA 115.”.).
It would have been obvious to someone of ordinary skill in the art before the
effective filing date of the claimed invention to have combined Areno in view of Avetisov, and Goss teaching of the system of claim 6 with the teaching of Xie “determining, by the defense module according to a control policy, whether to grant the access request, where the control policy is determined based on an access behavior model, the access behavior model is obtained through training with an access behavior dataset by using a statistical method or a machine learning algorithm and is used to represent a behavioral feature of accessing the service/interface by at least one CA, and the access behavior dataset includes an access behavior log, collected in the TEE, of accessing the service/interface by the at least one CA.”, (see Xie par.0007).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Areno et al. (US-20200084229-A1 hereafter Areno), in view of Avetisov et al. (US-10764752-B1 hereafter Avetisov), in view of Goss et al. (US-20160180093-A1 hereafter Goss), in view of Xie et al. (US20200274898-A1hereafter Xie), further view of Nam et al. (US-20200034318-A1hereafter Nam).
Regarding claim 8 Areno in view of Avetisov, Goss, and Xie disclose the system according to claim 7. Xie further teaches wherein said second bidirectional interface is configured to send data at a data rate lower than said data rate of said monitored traffic, (see Xie par.0052: “The TEE functional interface 127(second bidirectional interface) provides a set of application programming interfaces (API) to a CA 113 in the REE 120. The CA 113 can invoke some TEE services, such as encryption and decryption operations or secure storage, by using the TEE functional interface 127.”), and
Areno in view of Avetisov, Goss, and Xie fail to explicitly disclose however Nam teaches wherein said second bidirectional interface is configured to send data at a data rate higher than said data rate of said first bidirectional interface. (See Nam par.0048: “the second interface INF2 is configured for handling data having a relatively small size at a high operation speed and uses a protocol suitable for processing a smaller unit of data at a time (e.g., 64 bits or less) than that of the first interface INF1. For example, the second interface INF2 may be a 32-bit data bus operating at double data rate. Smaller channel interface of the second interface INF2 enables it to more efficiently handle data having a smaller size with a shorter latency compared to the first interface INF1 while consuming less power.
It would have been obvious to someone of ordinary skill in the art before the
effective filing date of the claimed invention to have combined Areno in view of Avetisov, Goss, and Xie teaching of the system of claim 7 with the teaching of Nam “The first interface INFl is configured for transmitting data between the first memory 230 and the processing unit 211 and uses a protocol suitable for a relatively large unit of data, e.g., 128-bit data bus operating at double data rate. Because data to be stored in the scratch pad memory 115 are relatively small in size, the data payload transmitted over the first interface INFl may include unnecessary portions that have been read from the first memory 230, which would waste power in reading and transferring unnecessary information and result in inefficient use of the system resources. second interface INF2 is configured for handling smaller data and has a smaller bus width (e.g., 32-bit or 64-bit) than that of the first interface INFl. Data having a relatively small size are transmitted more efficiently with a relatively short latency over the second interface INF2. As a result, the processing system 200 according to an embodiment may consume less power for transferring the data”, (see Nam par.0051-0052)
Conclusion
The prior art made of record and not relied upon is considered pertinent to
applicant's disclosure:
KHOSRAVI et al. (US-20190014113-A1) The sensor circuitry may be to generate sensor data. The memory circuitry may include at least a TEE having access control circuitry therein to control access to the secured resources based on the sensor data. The processing circuitry may be to cause execution in the device to be temporarily suspended and to transfer the sensor data from a memory location in the memory circuitry associated with the at least one sensor to a memory location within the TEE during the temporary suspension.
Smith et al. (US-20160248809-A1) a trusted execution environment (TEE) manager 216. The TEE manager 216 receives requests to instantiate trusted execution environments 202a, 202b and services requests to provision the trusted execution environments 202a, 202b with applicable environment keys 204 to process data while enforcing the applicable security level. the hardware/firmware 208 communicates with a policy manager 224 (e.g., via a communications network, a hardware interface, etc.). The policy manager 224 stores a security policy (e.g., the security policy 114, including the security environment definitions 116 and the security level definitions 118) that is referenced and/or otherwise used by the hardware/firmware 208 to enforce the security policy 114. The example policy manager 224 further includes the environment to security level lookup table 128. The example environment identifier 112 and/or the key manager 206 communicate with the policy manager 224 to obtain updated security environment information and/or security level information.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUILIO MUNGUIA whose telephone number is (571)270-5277. The examiner can normally be reached M-F 9:30AM - 5:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eleni A. Shiferaw can be reached at (571) 272-3867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DUILIO MUNGUIA/Examiner, Art Unit 2497 /ELENI A SHIFERAW/ Supervisory Patent Examiner, Art Unit 2497
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