DETAILED ACTION
This Office Action is in response to the application 18/256,532 filed on June 08th, 2023.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 4, 8, 11-13, 17, 21, 24-26 & 31-32 have been canceled. Claims 1-3, 5-7, 9-10, 14-16, 18-20, 22-23 & 27-30 is pending and herein considered.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS), submitted on 07/17/2023, is in compliance with the provisions of 37 CRR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Acknowledgement is made of Applicant’s claim for foreign priority under 35 U.S.C. 119(a)-(d) to Application No. 10202012419Q, the signed copy having been filed on December 11th, 2020.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claim 1 is rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter.
Regarding claim 1; claim 1 calls for a device; however, the body of the claim does not positively recite any hardware element. As recited in the body of the claim, the claimed system contains “a first electrode layer,” “a second electrode layer” and “an array of memory elements.” In light of the specification (pg. [28]), the first electrode layer, the second electrode layer, and the array of memory elements can be all construed as software per se since they do not embody any hardware. Because the elements of claim 1 is interpreted as merely software and the claim lacks any physical device or machine, the claim is directed to non-statutory subject matter. It is suggested that the claim be further amended to positively recite at least one hardware element within the body of the claim to make the claim statutory under 35 U.S.C. 101.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 5, 7, 9-10, 14, 16, 18, 20, 22-23, 27 and 29-30 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Muzzetto et al. (Muzzetto), U.S. Pub. Number 2023/0104314.
Regarding claim 1; Muzzetto discloses a memory device (par. 0029; a memory device.) for deep neural network, DNN, accelerators, the memory device comprising:
a first electrode layer (par. 0023; electrodes 108.) comprising a plurality of bit-lines (pars. 0023 & 0031; access lines 104, 106; word-lines 206 and bit-lines 204.);
a second electrode layer (par. 0023; electrodes 108.) comprising a plurality of word-lines (pars. 0023 & 0031; access lines 104, 106; word-lines 206 and bit-lines 204.); and
an array of memory elements (pars. 0018 & 0028; a memory cell array 100 & a memory cell array 200.) disposed at respective cross-points (par. 0028; a three-dimensional cross-point memory structure (3D X point) between the plurality of word-lines and the plurality of bit-lines (par. 0028; a plurality of access lines 204, 206; access lines can be referred to as bit-lines and word-lines.);
wherein at least a portion of the bit-lines are staggered such that a location of a cross-point between the bit-line and a first word-line is displaced along a direction of the word-lines compared to a cross-point between said bit-line and a second word-line adjacent the first word-line (par. 0050; a pair of connected word-lines of one level can be staggered with respect to a pair of connected word-lines of an adjacent level; word-lines are staggered so that adjacent pairs of connected word-lines are shifted with respect to one another along their axis of elongation; all drivers are fitted under the array, sharing the same footprint as memory cells in a densely packed manner.); or wherein at least a portion of the word-lines are staggered such that a location of a cross-point between the word-line and a first bit-line is displaced along a direction of the bit-lines compared to a cross-point between said word-line and a second bit-line adjacent the first bit-line (par. 0045; the memory device comprises bit-lines 304 oriented according to a direction that is orthogonal to the direction of the world-lines 305a and 306b and lying on a substantially parallel plane; each bit-line 304 provides access to a respective pair of decks connected to its opposite side, i.e., to both deck1 and deck2 (for bit-lines in a level between access lines level L1 and L3) or deck3 and deck4 (for bit-lines in a level between access lines level L3 and L2); bit-lines are also driven by bit-line drivers.).
Regarding claim 3; Muzzetto discloses the memory device of claim 1, configured to have a digital to analog converter, DAC, circuit coupled to the bit-lines for inference processing, and preferably comprising a connection layer separate from the first and second electrode layers for connecting intermediate bit-line inputs disposed between adjacent ones of the word-lines to the DAC circuit for inference processing (par. 0052; the pairs of connected word-lines 406b of the third level L3 are staggered with respect to adjacent pairs of connected word-lines of adjacent levels so that gaps for housing the connection element 405 are created in the first level L1; the word-lines 406b of the third level L3 are then connected to driver 408b; the connection element 405 passes through the gap G’ defined between two consecutives and terminated (i.e., non-connected) word-lines 406a of the first level L1, forming an alternated arrangement of connections of the word-line levels to the drivers 408a and 408b; the space region G’ may also be called as socket region.).
Regarding claim 5; Muzzetto discloses the memory device of claim 1, configured to have an analog to digital converter and sense amplifier, ADC/SA, circuit coupled to the word-lines for inference processing (par. 0024; the circuitry 142 includes access circuitry 143 and sense circuitry 145; circuitry includes electronic components that are electronically coupled to perform analog or logic operations on received or stored information, output information and store information.).
Regarding claim 7; Muzzetto discloses the memory device of claim 1claims 1 or 6, configured to have a digital to analog converter, DAC, circuit coupled to the word-lines for inference processing, and preferably comprising a connection layer separate from the first and second electrode layers for connecting intermediate word-line inputs disposed between adjacent ones of the bit-lines to the DAC circuit for inference processing (par. 0049; word-line drivers 408a and 408b are coupled to the respective word-lines 406a and 406b; the connection point C’ between the world-lines and their drivers is positioned substantially centrally between two consecutive word-lines of a same row of a given level; for instance, the connection point C’ can be formed in gaps between the ends of terminated consecutive word-lines in the same level, connecting said word-lines; in a given row of a given level, there are pairs of connected word-lines which are separated by the other pairs by gaps or spaces G’, the word-lines of each pair being connected to the same driver at the connection point C’.).
Regarding claim 9; Muzzetto discloses the memory device of claim 1 configured to have an analog to digital converter and sense amplifier, ADC/SA, circuit coupled to the bit-lines for inference processing (par. 0024; the circuitry 142 includes access circuitry 143 and sense circuitry 145; circuitry includes electronic components that are electronically coupled to perform analog or logic operations on received or stored information, output information and store information.).
Regarding claim 10; Muzzetto discloses the memory device of claim 1, wherein each memory element comprises a switching layer sandwiched between the bottom and top electrode layers, and optionally wherein the switching layer comprises A’2Q3, SiO2, HfO2, MoS2, TaOx, TiO2, ZrO2, ZnO, GeSbTe, Cu-GeSex etc, preferably wherein at least one of the bottom and top electrode layers comprises an inert metal such as Platinum, Palladium, Gold, Silver, Copper, Tungsten etc, preferably wherein at least one of the bottom and top electrode layers comprises a reactive metal such as Titanium, TiN, TaN, Tantalum etc (par. 0023; electrodes 108 are disposed between storage material 102 and access lines 104, 106; electrodes 108 electronically couple access lines 104, 106 with storage material 102; electrodes 108 can be made of one or more conductive and semiconductive materials such as carbon (C), carbon nitride (CxNy); n-doped polysilicon and p-doped polysilicon; metals including, Al, Cu, Ni, Cr, Co, Ru, Rh, Pd, Ag, Pt, Au, Ir, Ta, and W; conductive metal nitrides including TiN, TaN, WN, and TaCN; conductive metal silicides, cobalt silicides and titanium silicides; conductive metal silicides nitrides including TiSiN and WSiN; conductive metal carbide nitrides including TiCN and WCN; conductive metal oxides including RuO2, or other suitable conductive materials.).
Regarding claim 14; Claim 14 is directed to a method which has similar scope as claim 1. Therefore, claim 14 remains un-patentable for the same reasons.
Regarding claim 16; Claim 16 is directed to the method of claim 14 which has similar scope as claim 3. Therefore, claim 16 remains un-patentable for the same reasons.
Regarding claim 18; Claim 18 is directed to the method of claim 14 which has similar scope as claim 5. Therefore, claim 18 remains un-patentable for the same reasons.
Regarding claim 20; Claim 20 is directed to the method of claim 14 which has similar scope as claim 7. Therefore, claim 20 remains un-patentable for the same reasons.
Regarding claim 22; Claim 22 is directed to the method of claim 14 which has similar scope as claim 9. Therefore, claim 22 remains un-patentable for the same reasons.
Regarding claim 23; Claim 23 is directed to the method of claim 14 which has similar scope as claim 10. Therefore, claim 23 remains un-patentable for the same reasons.
Regarding claim 27; Claim 27 is directed to a method which has similar scope as claim 1. Therefore, claim 27 remains un-patentable for the same reasons.
Regarding claim 29; Claim 29 is directed to the method of claim 27 which has similar scope as claim 3. Therefore, claim 29 remains un-patentable for the same reasons.
Regarding claim 30; Claim 30 is directed to the method of claim 27 which has similar scope as claim 5. Therefore, claim 30 remains un-patentable for the same reasons.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 6, 15, 19 and 28 are rejected under 35 U.S.C. 103 as being unpatentable over Muzzetto et al. (Muzzetto), U.S. Pub. Number 2023/0104314, in view of Lin et al. (Lin), U.S. Pub. Number 2020/0175363.
Regarding claim 2; Muzzetto discloses the memory device of claim 1.
Muzzetto fails to explicitly disclose at least a portion of the bit-lines are staggered and the array of memory elements comprises a plurality of array-structures, ASs, each AS comprising a set of adjacent word-lines, wherein each AS comprises a plurality of sub-arrays, wherein each sub-array is configured to take inputs from a row of an input matrix and to have the elements of a row of a kernel applied in the DNN accelerator contributing to the output.
However, in the same field of endeavor, Lin discloses convolution accelerator using in-memory computation wherein at least a portion of the bit-lines are staggered and the array of memory elements comprises a plurality of array-structures, ASs, each AS comprising a set of adjacent word-lines, wherein each AS comprises a plurality of sub-arrays, wherein each sub-array is configured to take inputs from a row of an input matrix and to have the elements of a row of a kernel applied in the DNN accelerator contributing to the output (Lin: par. 0039; the kernel matrix includes nice vectors; in a convolution of horizontal and vertical stride 1 over an input matrix, each vector of the input matrix can be combined with each of the 9 vectors for the purposes of computing different values in the output matrix; some input vectors on the edges, for instance, may be combined with different numbers of the vectors, depending on the particular convolution being computed.).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lin into the memory device of Muzzetto wherein each AS comprises a plurality of sub-arrays, wherein each sub-array is configured to take inputs from a row of an input matrix and to have the elements of a row of a kernel applied in the DNN accelerator contributing to reduce the cost and computational resources needed to compute convolutions, including convolutions in CNNs (Lin: par. 0005).
Regarding claim 6; Muzzetto discloses the memory device of claim 1.
Muzzetto fails to explicitly disclose at least a portion of the word-lines are staggered and the array of memory elements comprises a plurality of array-structures, ASs, each AS comprising a set of adjacent bit-lines, wherein each AS comprises a plurality of sub-arrays, wherein each sub-array is configured to take inputs from a row of an input matrix and to have the elements of a row of a kernel applied in the DNN accelerator contributing to the output.
However, in the same field of endeavor, Lin discloses convolution accelerator using in-memory computation wherein at least a portion of the word-lines are staggered and the array of memory elements comprises a plurality of array-structures, ASs, each AS comprising a set of adjacent bit-lines, wherein each AS comprises a plurality of sub-arrays, wherein each sub-array is configured to take inputs from a row of an input matrix and to have the elements of a row of a kernel applied in the DNN accelerator contributing to the output (Lin: par. 0066; accelerating a convolution of a kernel matrix over an input matrix in which input vectors from the input matrix are combined with various combinations of elements of the kernel matrix for computation of an output matrix; different sets of cells in the array can be used to implement various combinations of elements; in preparation for the computation, the method includes storing the vectors of one or more kernels in different sets of cells in the array, where each of the vectors of the kernels comprises a different combination of elements of a kernel matrix (801); to execute computation, input vectors from an input matrix are read from memory in sequence (802); the sequence of input vectors is provided to the input drivers for the array (803); this results in applying elements of each input vector from the input matrix in parallel to the different sets of cells in the array (804); next, the outputs from each of the different sets of cells is sensed to produce for each input vector a set of data representing contributions to multiple elements of the output matrix (805); finally, the sets of data for each of the input vectors in the sequence are combined to produce the output matrix (806).).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teaching of Lin into the memory device of Muzzetto wherein at least a portion of the word-lines are staggered and the array of memory elements comprises a plurality of array-structures, ASs, each AS comprising a set of adjacent bit-lines, wherein each AS comprises a plurality of sub-arrays, wherein each sub-array is configured to take inputs from a row of an input matrix and to have the elements of a row of a kernel applied in the DNN accelerator contributing to the output to reduce the cost and computational resources needed to compute convolutions, including convolutions in CNNs (Lin: par. 0005).
Regarding claim 15; Claim 15 is directed to the method of claim 14 which has similar scope as claim 2. Therefore, claim 15 remains un-patentable for the same reasons.
Regarding claim 19; Claim 19 is directed to the method of claim 14 which has similar scope as claim 6. Therefore, claim 19 remains un-patentable for the same reasons.
Regarding claim 28; Claim 28 is directed to the method of claim 27 which has similar scope as claim 2. Therefore, claim 28 remains un-patentable for the same reasons.
Conclusion
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/KHOI V LE/
Primary Examiner, Art Unit 2436