DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed January 15, 2026 has been entered. Claims 1 and 3-12 remain pending in the application. Applicant’s amendments to the specification and claims have overcome each and every objection and 35 U.S.C. § 112 rejection previously presented in the Non-Final Office Action mailed November 13, 2025.
Response to Arguments
Applicant's arguments filed January 15, 2026 have been fully considered but they are not persuasive. Applicant argues, see pages 10-14, that previously presented prior art reference Cetin et al. (Patent Number US 7,884,672 B1), as cited by applicant, hereafter referred to as Cetin, fails to disclose multiple aspects of the claimed invention. Examiner respectfully disagrees.
First, applicant argues that Cetin fails to disclose the input signals being provided to a circuit that provides a difference between the first and second input signals. However, as disclosed in Fig. 3, Differential Feedback Circuit 345 functions based on a difference between the first and second input signals (see Col. 5, lines 23-36 and Col. 8, lines 28-32). Therefore, Cetin does disclose the input signals being provided to a circuit that provides a difference between the first and second input signals.
Second, applicant argues that Cetin does not disclose newly added limitation “the common mode reference signal is represented by an average of the first and the second input signal”. This argument has been considered, but is moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Third, applicant argues the Cetin does not disclose resistors connected to the differential inputs. However, as disclosed in Fig. 3, resistors 151 and 152 form a voltage divider connected to the differential inputs via the differential feedback circuit 345, and therefore Cetin does disclose the claimed features of “wherein the first voltage divider has a serial connection of a first resistor and a second resistor, wherein the serial connection is connected between the first input and the second input of the amplifier arrangement, wherein a connection point between the first and the second resistor forms a node at which the common mode reference signal is provided”. While Cetin does fail to disclose “wherein the first input terminal of the first differential amplifier is connected to the first input via a third resistor and the second input terminal of the first differential amplifier is connected to the second input via a fourth resistor”, previously presented prior art reference Garbarino et al. (Patent Publication Number US 2017/0170795 A1), hereafter referred to as Garbarino, does disclose this feature (Garbarino, Fig. 3, see resistors R1). Therefore, applicant’s arguments are unconvincing and the rejections of claims 1 and 3-12 are maintained.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 and 3-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 1 recites the limitation "the amplifier arrangement" in line 28. There is insufficient antecedent basis for this limitation in the claim. Amending the limitation to “the differential amplifier arrangement” is sufficient to overcome this rejection, which is how the limitation will be treated for examination purposes. Claims 3-12 are likewise rejected under this logic by virtue of their dependency on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Cetin in view of Garbarino and Hurwitz (Patent Publication Number EP 3,413,462 A1), hereafter referred to as Hurwitz.
Regarding claim 1, Cetin discloses:
A differential amplifier arrangement (Cetin, Fig. 3, 300) comprising: a first input configured to receive a first input signal (Fig. 3, Vip), a second input configured to receive a second input signal (Fig. 3, Vin), a first output configured to provide a first output signal (Fig. 3, Von), a second output configured to provide a second output signal (Fig. 3, Vop), a common mode loop (Fig. 3, 350) configured to regulate a common mode output of the differential amplifier arrangement depending on a difference between a common mode reference signal and an average of the first and the second output signal (Col. 5, lines 42-48), and a differential mode loop (Fig. 3, 34) configured to regulate a differential mode output of the differential amplifier arrangement depending on a difference between a difference between the first and the second input signal and a difference between the first and the second output signal (Col. 5, lines 23-36), wherein the difference between the first and the second output signal is substantially constant (Col. 5, lines 23-36, consider continuous operation of the described differential mode feedback loop), wherein the differential amplifier arrangement further comprises: a first amplifying stage (Fig. 3, 115 and 125); a first voltage divider (Fig. 3, 151 and 152); wherein the first amplifying stage comprises a first differential amplifier (Fig. 3, 115 and 125) having a first input terminal (Fig. 3, Vip) and a second input terminal (Fig. 3, Vin), wherein the first voltage divider has a serial connection of a first resistor and a second resistor (Fig. 3, see connection between 151 and 152), wherein the serial connection is connected between the first input and the second input of the amplifier arrangement (Fig. 3, see connection between 151 and Vip via differential feedback circuit 345 and connection between 152 and Vin via differential feedback circuit 345), wherein a connection point between the first resistor and the second resistor forms a node at which the common mode reference signal is provided (Fig. 3, see Vocm at node coupling 151 and 152), but fails to disclose wherein the common mode loop is further configured to implement at least one low frequency pole by means of which the common mode loop is slowed down, wherein the common mode reference signal is represented by an average of the first input signal and the second input signal, a third resistor; and a fourth resistor, and wherein the first input terminal of the first differential amplifier is connected to the first input via the third resistor and the second input terminal of the first differential amplifier is connected to the second input via the fourth resistor,
However, Garbarino teaches wherein the common mode loop is further configured to implement at least one low frequency pole by means of which the common mode loop is slowed down (Garbarino, Paragraph 60, lines 1-5), a third resistor (Fig. 3, see top instance of R1); and a fourth resistor (Fig. 3, see bottom instance of R1), and wherein the first input terminal of the first differential amplifier is connected to the first input via the third resistor (Fig. 3, see connection between top instance of R1 and 1a) and the second input terminal of the first differential amplifier is connected to the second input via the fourth resistor (Fig. 3, see connection between bottom instance of R1 and 1b), but fails to teach wherein the common mode reference signal is represented by an average of the first input signal and the second input signal.
However, Hurwitz teaches wherein the common mode reference signal is represented by an average of the first input signal and the second input signal (Hurwitz, Paragraph 62, lines 1-6).
Cetin, Garbarino, and Hurwitz are all considered to be analogous to the claimed invention because they are in the same field of improving common mode loop compensation in differential amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cetin to incorporate the teachings of Garbarino and Hurwitz to include the common mode compensation loop of Garbarino in the amplifier of Cetin, which would have the effect of providing increased frequency compensation for the amplifier of Cetin (Garbarino, Paragraph 61, lines 1-3) and to include the common mode reference signal of Hurwitz in the circuit of Cetin, which would have the effect of improving the common mode rejection ratio (Hurwitz, Paragraph 63, lines 4-5).
Regarding claim 3, Cetin fails to disclose:
wherein a unity gain frequency of the common mode loop is higher than a unity gain frequency of the differential mode loop.
However, Garbarino further teaches wherein a unity gain frequency of the common mode loop is higher than a unity gain frequency of the differential mode loop (Garbarino, Fig. 7, see that gain of common mode loop is always higher than gain of differential mode loop).
Cetin, Garbarino, and Hurwitz are all considered to be analogous to the claimed invention because they are in the same field of improving common mode loop compensation in differential amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cetin to incorporate the teachings of Garbarino to include the common mode compensation loop of Garbarino in the amplifier of Cetin, which would have the effect of providing increased frequency compensation for the amplifier of Cetin (Garbarino, Paragraph 61, lines 1-3).
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Cetin in view of Garbarino and Hurwitz as applied to claim 1 above, and further in view of Namekawa (Patent Publication Number US 2020/0304034 A1), hereafter referred to as Namekawa.
Regarding claim 4, Cetin fails to disclose:
wherein an overall common mode loop of the differential amplifier arrangement is configured to implement at least two sets of poles and zeros by means of which a gain of said overall common mode loop has a 20 decibel per decade zero crossing.
However, Garbarino further teaches wherein an overall common mode loop of the differential amplifier arrangement is configured to implement [a set of poles and zeroes] (Garbarino, Fig. 7, see pole fp1 and zero fz1) by means of which a gain of said overall common mode loop has a 20 decibel per decade zero crossing (Paragraph 60, lines 13-16), but fails to teach [implementing] at least two sets of poles and zeros.
However, Namekawa teaches [implementing] at least two sets of poles and zeros (Namekawa, Fig. 3C, see poles fp1 and fp2, and see zeroes fz1 and fz2).
Cetin, Garbarino, Hurwitz, and Namekawa are all considered to be analogous to the claimed invention because they are in the same field of improving differential amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cetin to incorporate the teachings of Garbarino and Namekawa to include the common mode compensation loop of Garbarino in the amplifier of Cetin, which would have the effect of providing increased frequency compensation for the amplifier of Cetin (Garbarino, Paragraph 61, lines 1-3) and to include the frequency response circuitry of Namekawa in the amplifier of Cetin, which would have the effect of providing a desired frequency response resistant to variations in temperature or supply voltage (Namekawa, Paragraph 58, lines 13-17).
Claims 5 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Cetin in view of Garbarino and Hurwitz as applied to claim 1 above, and further in view of Giotta et al. (Patent Publication Number US 2009/0251216 A1), as cited by applicant, hereafter referred to as Giotta.
Regarding claim 5, Cetin further discloses:
wherein the differential amplifier arrangement comprises at least a first amplifying stage (Cetin, Fig. 3, see first stage transistors 115 and 125), wherein the first amplifying stage comprises a first differential amplifier (Fig. 3, 115 and 125) having a first pair of differential input terminals (Fig. 3, Vip and Vin), a first pair of differential output terminals (Fig. 3, Von and Vop) and a control terminal (Fig. 3, see connection between 115 and 125 and current sink 130), the first pair of differential input terminals being connected to the first and the second input (Fig. 3, see connection between 115 and Vip and 125 and Vin), but fails to disclose and a second [amplifying stage], and wherein the second amplifying stage comprises a second differential amplifier having a second pair of differential input terminals and a second pair of differential output terminals, the second pair of differential input terminals being connected to the first pair of differential output terminals of the first differential amplifier, the second pair of differential output terminals being connected to the first and the second output.
However, Giotta teaches and a second [amplifying stage] (Giotta, Fig. 2, 210), and wherein the second amplifying stage comprises a second differential amplifier (Fig. 2, 210) having a second pair of differential input terminals (Fig. 2, see differential inputs of 210) and a second pair of differential output terminals (Fig. 2, see differential outputs of 210), the second pair of differential input terminals being connected to the first pair of differential output terminals of the first differential amplifier (Fig. 2, see connection between inputs of 210 and outputs of 204), the second pair of differential output terminals being connected to the first and the second output (Fig. 2, see connection between outputs of 210 and outputs 216 and 218).
Cetin, Garbarino, Hurwitz, and Giotta are all considered to be analogous to the claimed invention because they are in the same field of improving common mode loop compensation in differential amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cetin to incorporate the teachings of Giotta to include a second stage amplifier in the amplifier of Cetin, which would have the effect of providing multiple amplifying stages to increase overall amplification of the input signal of Cetin (Giotta, Paragraph 16, lines 1-10).
Regarding claim 7, Cetin and Garbarino fail to disclose:
wherein the differential mode loop comprises at least the first and the second amplifying stage, a first and a second transimpedance element, wherein the first transimpedance element is connected in a feedback loop between a first terminal of the second pair of differential input terminals and a first terminal of the second pair of differential output terminals of the second differential amplifier thereby forming a first branch of the differential mode loop, and wherein the second transimpedance element is connected in an additional feedback loop between a second terminal of the second pair of differential input terminals and a second terminal of the second pair of differential output terminals of the second differential amplifier, thereby forming a second branch of the differential mode loop.
However, Giotta further teaches wherein the differential mode loop comprises at least the first and the second amplifying stage (Giotta, Fig. 2, see amplifying stages 204 and 210), a first and a second transimpedance element (Fig. 2, see transimpedance elements 214(1) and 214(20), wherein the first transimpedance element is connected in a feedback loop between a first terminal of the second pair of differential input terminals and a first terminal of the second pair of differential output terminals of the second differential amplifier thereby forming a first branch of the differential mode loop (Fig. 2, see connection between positive output of 210 and negative input of 210 via third amplifying stage 212 and transimpedance element 214(1)), and wherein the second transimpedance element is connected in an additional feedback loop between a second terminal of the second pair of differential input terminals and a second terminal of the second pair of differential output terminals of the second differential amplifier, thereby forming a second branch of the differential mode loop (Fig. 2, see connection between negative output of 210 and positive input of 210 via third amplifying stage 212 and transimpedance element 214(2)).
Cetin, Garbarino, Hurwitz, and Giotta are all considered to be analogous to the claimed invention because they are in the same field of improving common mode loop compensation in differential amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cetin to incorporate the teachings of Giotta to include the common mode feedback circuitry of Giotta in the amplifier of Cetin, which would have the effect of providing an increased bandwidth for the common mode loop of Cetin (Giotta, Paragraph 14, lines 1-9).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Cetin in view of Garbarino, Hurwitz, and Giotta as applied to claim 5 above, and further in view of Awny et al. (Patent Publication Number EP 3,439,175 A1), as cited by applicant, hereafter referred to as Awny.
Regarding claim 6, Cetin and Garbarino fail to disclose:
wherein the common mode loop comprises at least the first and the second amplifying stage, a common mode feedback amplifier, and a filter component, wherein the common mode feedback amplifier has a first and a second feedback input terminal and a feedback output terminal, wherein the first feedback input terminal is configured to receive the common mode reference signal and the feedback output terminal is connected to the control terminal of the first differential amplifier, wherein the filter component comprises a filter capacitor and a filter resistor, wherein the filter capacitor is connected to the second feedback input terminal and to a reference potential terminal and wherein the filter resistor is connected with one terminal to the second feedback input terminal, another terminal of the filter resistor being configured to receive the average of the first and the second output signal.
However, Giotta further teaches wherein the common mode loop comprises at least the first and the second amplifying stage (Giotta, Fig. 2, see feedback loop from 204 through 210, 212, 222, 230, 226, back to 204), a common mode feedback amplifier (Fig. 2, 226) wherein the common mode feedback amplifier has a first (Fig. 2, see positive input of 226) and a second feedback input terminal (Fig. 2, see negative input of 226) and a feedback output terminal (Fig. 2, see positive output of 226), wherein the first feedback input terminal is configured to receive the common mode reference signal (Fig. 2, see connection between positive input of 226 and reference signal VCM) and the feedback output terminal is connected to the control terminal of the first differential amplifier (Fig. 2, see connection between 204 and 226 via control signal 228), but fails to disclose and a filter component, wherein the filter component comprises a filter capacitor and a filter resistor, wherein the filter capacitor is connected to the second feedback input terminal and to a reference potential terminal and wherein the filter resistor is connected with one terminal to the second feedback input terminal, another terminal of the filter resistor being configured to receive the average of the first and the second output signal.
However, Awny teaches and a filter component (Awny, Fig. 4, see RC filter between 170 and 111), wherein the filter component comprises a filter capacitor and a filter resistor (Fig. 4, see RC filter between 170 and 111), wherein the filter capacitor is connected to the second feedback input terminal (Fig. 4, see connection between RC filter capacitor and 111) and to a reference potential terminal (Fig. 4, see connection between RC filter capacitor and ground) and wherein the filter resistor is connected with one terminal to the second feedback input terminal (Fig. 4, see connection between RC filter resistor and 111), another terminal of the filter resistor being configured to receive the average of the first and the second output signal (Fig. 4, see connection between RC filter resistor and the node coupling the resistors 170, and consider implementing the RC filter at the negative input of common mode feedback amplifier 226 of Fig. 2 of Giotta).
Cetin, Garbarino, Hurwitz, Giotta, and Awny are all considered to be analogous to the claimed invention because they are in the same field of improving common mode loop compensation in differential amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cetin to incorporate the teachings of Giotta and Awny to include the common mode feedback loop of Giotta in the amplifier of Cetin, which would have the effect of providing an increased bandwidth for the common mode loop of Cetin (Giotta, Paragraph 14, lines 1-9), and to include the RC filter of Awny in the common mode feedback loop of Giotta, which would have the effect of removing undesired high frequency signals from the common mode feedback loop of Giotta (Awny, Paragraph 35, lines 5-8).
Claims 8-9 are rejected under 35 U.S.C. 103 as being unpatentable over Cetin in view of Garbarino, Hurwitz, and Giotta as applied to claim 7 above, and further in view of Nakashima (Patent Number US 10,474,173 B2), hereafter referred to as Nakashima.
Regarding claim 8, Cetin, Garbarino, and Giotta fail to disclose:
wherein each of the first and the second transimpedance elements comprises a first and a second resistor and a first and a second capacitor, wherein the first resistor and the first capacitor are connected in parallel forming a parallel connection, the second resistor is connected in series to the parallel connection, thereby forming a serial connection, and the second capacitor is connected in parallel to the serial connection.
However, Nakashima teaches wherein each of the first and the second transimpedance elements comprises a first (Nakashima, Fig. 1, 22) and a second resistor (Fig. 1, 21) and a first (Fig. 1, 23) and a second capacitor (Fig. 1, 24), wherein the first resistor and the first capacitor are connected in parallel forming a parallel connection (Fig. 1, see parallel connection of 22 and 23), the second resistor is connected in series to the parallel connection (Fig. 1, see series connection of 21 with 22/23), thereby forming a serial connection (Fig. 1, see series connection of 21 with 22/23), and the second capacitor is connected in parallel to the serial connection (Fig. 1, see parallel connection of 24 and 21/22/23).
Cetin, Garbarino, Hurwitz, Giotta, and Nakashima are all considered to be analogous to the claimed invention because they are in the same field of improving differential amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cetin to incorporate the teachings of Nakashima to include the feedback network of Nakashima in the circuit of Cetin, which would have the effect of increasing the stability of the system of Cetin (Nakashima, Col. 1, lines 64-67).
Regarding claim 9, Cetin, Garbarino, and Giotta fail to disclose:
wherein a capacitance of the first capacitor is dimensioned to be larger than a capacitance of the second capacitor.
However, Nakashima further teaches wherein a capacitance of the first capacitor is dimensioned to be larger than a capacitance of the second capacitor (Nakashima, Col. 3, lines 58-62, consider that the second capacitor [capacitor 24] is dimensioned to be small).
Cetin, Garbarino, Hurwitz, Giotta, and Nakashima are all considered to be analogous to the claimed invention because they are in the same field of improving differential amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cetin to incorporate the teachings of Nakashima to include the feedback network of Nakashima in the circuit of Cetin, which would have the effect of increasing the stability of the system of Cetin (Nakashima, Col. 1, lines 64-67).
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Cetin in view of Garbarino and Hurwitz as applied to claim 1 above, and further in view of Awny.
Regarding claim 10, Cetin and Garbarino fail to disclose:
wherein the common mode reference signal is represented by an average of the first and the second input signal.
However, Awny teaches wherein the common mode reference signal is represented by an average of the first and the second input signal (Awny, Paragraph 13, lines 23-27).
Cetin, Garbarino, Hurwitz, and Awny are all considered to be analogous to the claimed invention because they are in the same field of improving common mode loop compensation in differential amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cetin to incorporate the teachings of Awny to include the RC filter of Awny in the common mode feedback loop of Giotta, which would have the effect of removing undesired high frequency signals from the common mode feedback loop of Giotta (Awny, Paragraph 35, lines 5-8).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Cetin in view of Garbarino and Hurwitz as applied to claim 1 above, and further in view of Konishi et al. (Patent Publication Number JP 2002/358582 A), hereafter referred to as Konishi.
Regarding claim 11, Cetin and Garbarino fail to disclose:
(according to claim 1) wherein the first output of the differential amplifier arrangement is configured to be connected to a first terminal of a connectable load capacitor and the second output of the differential amplifier arrangement is configured to be connected to a second terminal of the connectable load capacitor, and wherein the connectable load capacitor has a capacitance in a micro Farad range.
However, Konishi teaches wherein the first output of the differential amplifier arrangement is configured to be connected to a first terminal of a connectable load capacitor (Konishi, Fig. 1, see connection between 7 and C0, see also Paragraph 8, lines 3-5) and the second output of the differential amplifier arrangement is configured to be connected to a second terminal of the connectable load capacitor (Fig. 1, see connection between 7 and C0, see also Paragraph 8, lines 3-5), and wherein the connectable load capacitor has a capacitance in a micro Farad range (Paragraph 8, lines 3-5).
Cetin, Garbarino, Hurwitz, and Konishi are all considered to be analogous to the claimed invention because they are in the same field of improving differential amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cetin to incorporate the teachings of Konishi to include the capacitor of Konishi in the circuit of Cetin, which would have the effect of reducing fluctuations in the output of Cetin (Konishi, Paragraph 8, lines 3-5).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Cetin in view of Garbarino Hurwitz, and Awny as applied to claim 10 above, and further in view of Konishi and Tang et al. (Patent Publication Number TW 2013/07875 A), hereafter referred to as Tang.
Regarding claim 12, Cetin in view of Garbarino and Awny further disclose:
A converter arrangement comprising the differential amplifier arrangement according to claim 10 (see above), but fail to disclose the connectable load capacitor which is connected between the first and the second output of the differential amplifier arrangement and an analog-to-digital converter which is connected between the first and the second output of the differential amplifier arrangement.
However, Konishi teaches the connectable load capacitor which is connected between the first and the second output of the differential amplifier arrangement (Konishi, Fig. 1, see connection between 7 and C0, see also Paragraph 8, lines 3-5), but fails to teach and an analog-to-digital converter which is connected between the first and the second output of the differential amplifier arrangement.
However, Tang teaches and an analog-to-digital converter (Tang, Fig. 2, 160) which is connected between the first and the second output of the differential amplifier arrangement (Fig. 2, see connection between ADC 160 and outputs of differential amplifier arrangement 150).
Cetin, Garbarino, Hurwitz, Awny, Konishi, and Tang are all considered to be analogous to the claimed invention because they are in the same field of improving differential amplifiers. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified Cetin to incorporate the teachings of Konishi and Tang to include the capacitor of Konishi in the circuit of Cetin, which would have the effect of reducing fluctuations in the output of Cetin (Konishi, Paragraph 8, lines 3-5), and to include the analog-to-digital converter of Tang in the circuit of Cetin, which would have the effect of providing a digitized output signal for the circuit of Cetin (Tang, Page 3, Paragraph 3, lines 1-3).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Kumar (Patent Publication Number US 2018/0069513 A1) discloses (Fig. 8) a differential amplifier with a common mode feedback loop.
Huang (Patent Publication Number US 2015/0035598 A1) discloses (Fig. 3) a differential amplifier with a common mode loop measuring the input common mode signal.
Chang (Patent Publication Number US 2008/0284513 A1) discloses (Fig. 1) a differential amplifier with a common mode feedback loop.
Haila et al. (Patent Publication Number US 2008/0278234 A1) discloses (Fig. 10) a differential amplifier with an RC network corresponding to the claimed transimpedance elements.
Sano et al. (Patent Publication Number JP 2004/274,434 A) discloses (Fig. 4) a differential amplifier with a feedback RC network corresponding to the claimed transimpedance elements.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Lance T Bartol whose telephone number is (703)756-1267. The examiner can normally be reached Monday - Thursday 6:30 a.m. - 4:00 p.m. CT, Alternating Fridays 6:30 - 3:00.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached at 571-272-5918. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/LANCE TORBJORN BARTOL/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843