DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-10 and 13-14 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ogi (US 2019/0157323).
Regarding Claims 1 and 14, Ogi discloses a distance measurement apparatus [Fig 20-22]; comprising: an optical system [#2100 of Fig 20; 0096], a light detection device comprising: a semiconductor substrate that includes a first surface and a second surface opposed to each other [#400 of Fig 2; 0109-13], and includes a pixel array in which a plurality of pixels is disposed in an array [0092-93]; a semiconductor layer that is provided on a side of the first surface of the semiconductor substrate [#406 of Fig 2; 0113-14]; a light receiver that is provided inside the semiconductor substrate for each of the pixels [#160 of Fig 21; 0101; 0105], and generates carriers corresponding to a received light amount by photoelectric conversion; a multiplier that includes a first conduction-type region and a second conduction-type region sequentially stacked on the side of the first surface [#730, #740 of Fig 21; 0102-0106], at least the second conduction-type region being provided in the semiconductor layer, and that performs avalanche multiplication on the carriers generated by the light receiver [#720 of Fig 21; 0102]; a first electrode that is provided on the side of the first surface, and is electrically coupled to the light receiver [#152 of Fig 21; 0086-87; 0090; 0092]; and a second electrode that is provided on the side of the first surface, and is electrically coupled to the multiplier [#102 of Fig 21; 0103].
Regarding Claim 2, Ogi also discloses wherein the multiplier includes the first conduction-type region and the second conduction-type region both of which are provided in the semiconductor layer [Fig 20-22; 0102-06].
Regarding Claim 3, Ogi also discloses an insulating layer on the side of the first surface of the semiconductor substrate, wherein the semiconductor layer is embedded and formed in the insulating layer for each of the pixels [#200 of Fig 18, 19; 0092; 0094-95].
Regarding Claim 4, Ogi also discloses wherein the multiplier formed in the semiconductor layer has an end surface on an inner side relative to a side surface of the semiconductor layer [#720 of Fig 21; 0102-06].
Regarding Claim 5, Ogi also discloses wherein a side surface of the semiconductor layer is inclined with respect to the first surface [#200 of Fig 18, 19; #556 of Fig 41; 0092; 0094-95; 0167].
Regarding Claim 6, Ogi also discloses wherein the semiconductor substrate further includes a pixel separator that separates the plurality of pixels from each other and penetrates the semiconductor substrate between the first surface and the second surface [#150 of Fig 21; 0084; 0088; 0092; 0094-95; 0102; 0104; 0139].
Regarding Claim 7, Ogi also discloses wherein the pixel separator further penetrates the semiconductor layer [#150 of Fig 21; 0084; 0088; 0092; 0094-95; 0102; 0104; 0139].
Regarding Claim 8, Ogi also discloses wherein the pixel separator includes a conductive film and an insulation film, the conductive film having a light-shielding property [#558 of Fig 41; 0168], the insulation film being provided between the conductive film and the semiconductor substrate [#200 of Fig 18, 19; #556 of Fig 41; 0092; 0094-95; 0167].
Regarding Claim 9, Ogi also discloses a first conduction-type impurity region around the pixel separator, wherein the light receiver and the first electrode are electrically coupled to each other via the first conduction-type impurity region [#700, #760 of Fig 21 ; 0102-06].
Regarding Claim 10, Ogi also discloses a second conduction-type impurity region in the semiconductor layer, wherein the multiplier and the second electrode are electrically coupled to each other via the second conduction-type impurity region [#750 of Fig 21 ; 0102-06].
Regarding Claim 13, Ogi also discloses wherein the semiconductor substrate and the semiconductor layer each include silicon [#400 of Fig 22; 0112-14]
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ogi (US 2019/0157323), as applied to claims 1 and 3 above, and further in view of Bandara (US 6,184,538)
Regarding Claims 11 and 12, Ogi does not explicitly teach – but Bandara does teach a reflection layer that is provided in the insulating layer and surrounds the semiconductor layer [Claims 5, 7] and wherein the reflection layer is split, one end is coupled to the second electrode, and another end is coupled to a readout circuit that reads out the carriers multiplied by the multiplier [Claims 5, 7]. It would have been obvious to modify the device of Ogi to include a reflective insulating layer and it coupled to a readout circuit so that plural stacks can be simultaneously read out by the corresponding readout pixels in the multiplexer.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES R HULKA whose telephone number is (571)270-7553. The examiner can normally be reached M-R: 9am-6pm, F: 10am-2pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Helal Algahaim can be reached at 5712705227. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
JAMES R. HULKA
Primary Examiner
Art Unit 3645
/JAMES R HULKA/Primary Examiner, Art Unit 3645