Prosecution Insights
Last updated: April 19, 2026
Application No. 18/258,075

CIRCUITS INCLUDING HIGH POWER TRANSISTORS

Final Rejection §102§103
Filed
Jun 16, 2023
Examiner
DHAKAL, BICKEY
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Search For The Next Ltd.
OA Round
2 (Final)
84%
Grant Probability
Favorable
3-4
OA Rounds
2y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allow Rate
616 granted / 732 resolved
+16.2% vs TC avg
Strong +16% interview lift
Without
With
+16.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
43 currently pending
Career history
775
Total Applications
across all art units

Statute-Specific Performance

§101
2.4%
-37.6% vs TC avg
§103
41.8%
+1.8% vs TC avg
§102
28.0%
-12.0% vs TC avg
§112
24.5%
-15.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 732 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Applicant's submission filed on 02/16/2026 has been entered. Response to Arguments Applicant's arguments filed 02/16/2026 have been fully considered but they are not persuasive. Applicant argues on pages 5 and 6 that GARNER fails to teach “the ON state and the OFF state”. The examiner respectively disagrees because GARNER fig. 5 clearly shows lower base current duration (OFF period) is also shorter than the hold-on period (see updated rejection below). Therefore, the rejection is maintained. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 and 3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by GARNER WO 2008/132509 A2. Regarding claim 1, GARNER discloses A circuit (Figs. 2a and 4) comprising: a bipolar junction transistor (BJT) (Item 208) having a collector drift region (Collector is lightly-doped which is equivalent to a collector drift region); PNG media_image1.png 290 672 media_image1.png Greyscale a controller (Item 214); a driver circuit (Item 218) having an input (Signal 216 is inputted to item 218) adapted to receive a control signal (Signal 216) from the controller, and an output (An output is connected to a base of item 208) connected to a base terminal (A terminal where signal 220 is inputted) of the BJT; the driver circuit adapted to switch the state at the output in response to the received control signal between: an ON state that switches the transistor into an ON state; an OFF state that switches the transistor into an OFF state (Signal 220 is a modulated signal which comprises of ON and OFF pulses); and a floating state (At the end of the force-on period, the switch S1 is opened to initiate to start floating period); and wherein the controller is adapted to operate the driver circuit such that within a ON-OFF switching cycle of the BJT, the output of the driver circuit is in the floating state for longer than it is in the ON state and the OFF state (It is clear from fig. 5 that the hold-on period where the floating happens is longer than ON period (Force-on period) and OFF period. It is clear from Figure 5 that lower collector current (OFF period) is also shorter than the hold-on period (see annotated fig. below)). PNG media_image2.png 415 606 media_image2.png Greyscale PNG media_image3.png 329 703 media_image3.png Greyscale PNG media_image4.png 601 678 media_image4.png Greyscale PNG media_image5.png 731 681 media_image5.png Greyscale Regarding claim 3, GARNER discloses wherein the controller is adapted to operate the driver circuit such that the output of the driver circuit is in the floating state for equal or over 50% of a complete ON-OFF cycle of the BJT (Fig. 5 shows hod-on period (Floating state) is longer than force-on (ON) period, which indicates over 50%. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over GARNER in a view of Brajder US 4,239,989. Regarding claim 2, GARNER does not disclose but Brajder discloses a bypass connection (Via item 16 in Fig. 1) between the base terminal (Item 10) of the BJT (Item 7) and an emitter terminal (Item 4) of the BJT, the bypass connection including a load with a resistance sufficient that, when in operation, current through the bypass connection when the BJT is OFF is small compared with the current through the base terminal when the BJT is ON (See column 6, lines 51-68, column 7, lines 1-8). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a bypass connection between the base and an emitter terminal as disclosed by Brajder in GARNER’s teachings to accelerate the switching-off process to reduce the switching-off losses (See Brajder’s column 7, lines 1-8). Claims 4 and 6 are rejected under 35 U.S.C. 103 as being unpatentable over King et al. US 4,926,104 in a view of GARNER. Regarding claim 4, King et al. disclose A motor driver for a multi-phase electric-motor comprising: a switching circuit (Item 10) comprising multiple bipolar junction transistors (BJTs) for switching current through windings (Stator windings) of the multi-phase electric-motor (Item 18) (Column 7, lines 39-54), a separate driver circuit (Items 38a-38c) associated with each BJT, each driver circuit comprising an input (Items 38a-38c each having an input to get signal from item 34) adapted to receive a control signal (Output from item 34) from a controller (Item 34), and an output (Fig. 1 shows output from items 38a-38c connected to base of BJT) connected to a base terminal of its respective BJT (Outputs from items 38a-38c are couples to BJTs 20-25) (Column 3, lines 49-68, column 4, lines 1-68, column 5, lines 1-8); King et al. do not disclose but GARNER discloses each BJT comprising a collector drift region (Collector is lightly-doped which is equivalent to a collector drift region), PNG media_image6.png 421 975 media_image6.png Greyscale the driver circuit adapted to switch the state at its output in response to the received control signal between: an ON state that switches the transistor into an ON state; an OFF state that switches the transistor into an OFF state; and a floating state; and wherein the controller is adapted to operate the separate driver circuits such that during a complete ON-OFF switching cycle of each BJT, the output of the driver circuit is in the floating state for longer than it is in the ON state and the OFF state. (See claim 1 rejection for details) Therefore, it would have been obvious to use the driver circuit to switch the state at its output in response to the received control signal between: an ON state that switches the transistor into an ON state; an OFF state that switches the transistor into an OFF state; and a floating state; and wherein the controller is adapted to operate the separate driver circuits such that during a complete ON-OFF switching cycle of each BJT, the output of the driver circuit is in the floating state for longer than it is in the ON state and/or the OFF state as disclosed by GARNER in King’s teachings to control the degree of saturation when the device is on and hence improve turn-off times. PNG media_image7.png 200 723 media_image7.png Greyscale Regarding claim 6, a combination of King and GARNER discloses wherein the controller is adapted to operate the driver circuit such that the output of the driver circuit is in the floating state for equal or over 50% of a complete ON-OFF cycle of the BJT (GARNER’s fig. 5 shows hod-on period (Floating state) is longer than force-on (ON) period, which indicates over 50%. Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over King et al. US 4,926,104 in a view of GARNER and further in a view of Brajder US 4,239,989. Regarding claim 5, a combination of King and GARNER does not disclose but Brajder discloses a bypass connection (Via item 16 in Fig. 1) between the base terminal (Item 10) of the BJT (Item 7) and an emitter terminal (Item 4) of the BJT, the bypass connection including a load with a resistance sufficient that, when in operation, current through the bypass connection when the BJT is OFF is small compared with the current through the base terminal when the BJT is ON (See column 6, lines 51-68, column 7, lines 1-8). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a bypass connection between the base and an emitter terminal as disclosed by Brajder in King’s and GARNER’s teachings to accelerate the switching-off process to reduce the switching-off losses (See Brajder’s column 7, lines 1-8). Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BICKEY DHAKAL whose telephone number is (571)272-3577. The examiner can normally be reached 8:30-4:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at 5712722078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BICKEY DHAKAL/Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Jun 16, 2023
Application Filed
Nov 13, 2025
Non-Final Rejection — §102, §103
Feb 16, 2026
Response Filed
Mar 06, 2026
Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
84%
Grant Probability
99%
With Interview (+16.5%)
2y 5m
Median Time to Grant
Moderate
PTA Risk
Based on 732 resolved cases by this examiner. Grant probability derived from career allow rate.

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