Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 19 June 2023 and 25 March 2024 were filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-7, 9 and 10 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claim 9 recites “A data processing method comprising: repeatedly acquiring from a device, operation data of the device; determining whether or not the acquired operation data satisfies an application condition for applying the operation data to an inference model for inferring status of the device, every time when the operation data is acquired from the device; and performing to the device, a countermeasure process which is a process for the operation data to satisfy the application condition, in a case where a period during which it is continuously determined that the operation data does not satisfy the application condition is equal to or more than a threshold value.”
Claim 9, in view of the claim limitations, recites the abstract idea of “repeatedly acquiring from a device, operation data of the device; determining whether or not the acquired operation data satisfies an application condition for applying the operation data to an inference model for inferring status of the device, every time when the operation data is acquired from the device; and performing to the device, a countermeasure process which is a process for the operation data to satisfy the application condition, in a case where a period during which it is continuously determined that the operation data does not satisfy the application condition is equal to or more than a threshold value.”
As a whole, in view of the claim limitations, but for the computer components and systems performing the claimed functions, the broadest reasonable interpretation of the recited “repeatedly acquiring from a device, operation data of the device; determining whether or not the acquired operation data satisfies an application condition for applying the operation data to an inference model for inferring status of the device, every time when the operation data is acquired from the device; and performing to the device, a countermeasure process which is a process for the operation data to satisfy the application condition, in a case where a period during which it is continuously determined that the operation data does not satisfy the application condition is equal to or more than a threshold value.”; therefore, the claims recite mental processes. Accordingly, the claim recites a mental process, and thus, the claim recites an abstract idea under the first prong of Step 2A.
This judicial exception is not integrated into a practical application under the second prong of Step 2A. In particular, the claims recite the additional elements beyond the recited abstract idea of“[a] computer- implemented method” and “the method is carried out by one or more physical processors configured by machine-readable instructions” as recited in claim 1, individually and when viewed as an ordered combination, and pursuant to the broadest reasonable interpretation, each of the additional elements are computing elements recited at high level of generality implementing the abstract idea on a computer (i.e. apply it), and thus, are no more than applying the abstract idea with generic computer components. Moreover, aside from the aforementioned additional elements, the remaining elements of dependent claims 2-7 and 10 do not integrate the abstract idea into a practical application because these claims merely recite further limitations that provide no more than simply narrowing the recited abstract idea.
The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception under Step 2B. As noted above, the aforementioned additional elements beyond the recited abstract idea, as an order combination, are no more than mere instructions to implement the idea using generic computer components (i.e. apply it), and further, generally link the abstract idea to a field of use, which is not sufficient to amount to significantly more than an abstract idea; therefore, the additional elements are not sufficient to amount to significantly more than an abstract idea. Additionally, these recitations as an ordered combination, simply append the abstract idea to recitations of generic computer structure performing generic computer functions that are well-understood, routine, and conventional in the field as evinced by Applicant’s Specification at [0187] (describing that the disclosure is not limited to the disclosed implementations, but, on the contrary, is intended to cover modifications and equivalent arrangements that are within the spirit and scope of the appended claims). Furthermore, as an ordered combination, these elements amount to generic computer components performing repetitive calculations, receiving or transmitting data over a network, which, as held by the courts, are well-understood, routine, and conventional. See MPEP 2106.05(d); July 2015 Update, p. 7. Moreover, aside from the aforementioned additional elements, the remaining elements of dependent claims 2-7 and 10 do not transform the recited abstract idea into a patent eligible invention because these claims merely recite further limitations that provide no more than simply narrowing the recited abstract idea. Looking at these limitations as an ordered combination adds nothing additional that is sufficient to amount to significantly more than the recited abstract idea because they simply provide instructions to use a generic arrangement of generic computer components and recitations of generic computer structure that perform well-understood, routine, and conventional computer functions that are used to “apply” the recited abstract idea. Thus, the elements of the claims, considered both individually and as an ordered combination, are not sufficient to ensure that the claim as a whole amounts to significantly more than the abstract idea itself. Since there are no limitations in these claims that transform the exception into a patent eligible application such that these claims amount to significantly more than the exception itself, claims 1-7, 9 and 10 are rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-7, 9 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yoshida et al (US 2017/0337525).
Yoshida et al disclose the following claimed features:
Regarding claim 1, a data processing apparatus (Figures 1 and 2) comprising: processing circuitry (102) to: repeatedly acquire (121) from a device (101), operation data (111) of the device (paragraph [0065]); determine (127) whether or not the acquired operation data satisfies an application condition for applying the operation data to an inference model for inferring status of the device, every time when the operation data is acquired from the device (paragraphs [0073]-[0074]); and perform to the device, a countermeasure process (129) which is a process for the operation data to satisfy the application condition, in a case where a period during which it is continuously determined that the operation data does not satisfy the application condition is equal to or more than a threshold value (paragraphs [0093]-[0094]).
Regarding claim 2, wherein as determination of whether or not the pending operation data is the operation data suitable for the update of the inference model, the processing circuitry determines whether or not subsequent operation data which is operation data acquired from the device after the pending operation data is stored into the storage area, is applied to the inference model, and whether or not the device is inferred to be in normal status, and when the subsequent operation data is applied to the inference model and the device is inferred to be in the normal status, the processing circuitry determines that the pending operation data is the operation data suitable for the update of the inference model and updates the inference model using the pending operation data (paragraphs [0104]-[0106]).
Regarding claim 3, wherein as determination of whether or not the pending operation data is the operation data suitable for the update of the inference model, the processing circuitry determines whether or not the update of the inference model using the pending operation data is instructed, and when the update of the inference model using the pending operation data is instructed, the processing circuitry determines that the pending operation data is the operation data suitable for the update of the inference model and updates the inference model using the pending operation data (paragraphs [0107]-[0109]).
Regarding claim 4, wherein when the update of the inference model is instructed, the processing circuitry updates the inference model using one or more pieces of operation data acquired (paragraph [0110]).
Regarding claim 5, wherein the processing circuitry updates an application condition of the inference model together with the update of the inference model (paragraph [0110]).
Regarding claim 6, wherein the inference model is generated through learning using learning data, and when attribute of the operation data deviates from attribute of the learning data, the processing circuitry determines that the operation data does not satisfy the application condition (paragraph [0116]).
Regarding claim 7, wherein the processing circuitry updates the inference model by performing learning using the pending operation data (paragraph [0116]).
Regarding claim 9, a data processing method (Figures 1 and 2) comprising: repeatedly acquiring (121) from a device (101), operation data (111) of the device (paragraph [0065]); determining (127) whether or not the acquired operation data satisfies an application condition for applying the operation data to an inference model for inferring status of the device, every time when the operation data is acquired from the device (paragraphs [0073]-[0074]); and performing to the device, a countermeasure process (129) which is a process for the operation data to satisfy the application condition, in a case where a period during which it is continuously determined that the operation data does not satisfy the application condition is equal to or more than a threshold value (paragraphs [0093]-[0094]).
Regarding claim 10, wherein the processing circuitry stores the operation data into a predetermined storage area (128) as pending operation data, when it is determined that the operation data does not satisfy the application condition; and the processing circuitry determines whether or not the pending operation data is operation data suitable for an update of the inference model, and updates the inference model using the pending device data, when it is determined that the pending operation data is the operation data suitable for the update of the inference model (paragraphs [0110]-[0115]).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AN H DO whose telephone number is (571)272-2143. The examiner can normally be reached on M-F 7:5:30pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Stephen Meier can be reached on 571-272-2149. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/AN H DO/Primary Examiner, Art Unit 2853