DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Applicant’s preliminary amendment filed June 19, 2023 has been entered and considered.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 25-31, 34 and 36 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zitzlsperger et al. (DE 102015102785 A1).
Regarding claim 25, Zitzlsperger et al. teaches:
A semiconductor device [1201, paragraph [0085], Fig. 12] comprising:
a semiconductor component [107, paragraph [0059], Fig. 12] having a first electrical contact surface on a top side of the component and a second electrical contact surface on a bottom side of the component opposite the top side; [Inherent]
a filler material [201, paragraph [0062], Fig. 12] enclosing the semiconductor component [107, Fig. 12] as seen in a circumferential direction [Fig. 4], the filler material [201, Fig. 12] covering at least a partial region of a side surface of the component [107, Fig. 12] connecting the top side and the bottom side;
at least one conductor track [1003, paragraph [0089], Fig. 12] arranged on a top side of the filler material [201, Fig. 12], the at least one conductor track [1003, Fig. 12] being electrically connected to the first electrical contact surface; and
a first connection point and a second connection point arranged adjacent to a bottom side of the filler material [201, Fig. 12] opposite the top side of the filler material [201, Fig. 12], the first connection point being electrically connected to the at least one conductor track [1003, Fig. 12] via a through-plating [103/1205, paragraph [0089], Fig. 12] through the filler material [201, Fig. 12] and the second connection point being electrically connected to the second electrical contact surface,
wherein the through-plating [103, Fig. 12] has a layered structure and at least one undercut in order to fix the filler material.
Regarding claim 26, Zitzlsperger et al. teaches:
The semiconductor device [16, Fig. 1-8] according to claim 25, further comprising a further contact [105, paragraph [0059-0060], Fig. 2, 12] formed through the filler material [201, paragraph [0062], [0065], Fig. 2, 12] and electrically connecting the second connection point to the second electrical contact surface.
Regarding claim 27, Zitzlsperger et al. teaches:
The semiconductor device [16, Fig. 1-8] according to claim 26, wherein the further contact [105, Fig. 12] has a layered structure and/or has at least one undercut [See Fig. 12] in order to fix the filler material [201, Fig. 12].
Regarding claim 28, Zitzlsperger et al. teaches:
The semiconductor device [16, Fig. 1-8] according to claim 27, wherein a layer of the layered structure of the through-plating [103, paragraph [0059-0060], Fig. 12] and a corresponding layer of the further contact [105, Fig. 12] have substantially the same thickness.
Regarding claim 29, Zitzlsperger et al. teaches:
The semiconductor device [16, Fig. 1-8] according to claim 26, wherein the further contact [105, Fig. 2, 12] substantially comprises a recess [paragraph [0088-0089]] in which the semiconductor component [107, Fig. 2, 12] is arranged.
Regarding claim 30, Zitzlsperger et al. teaches:
The semiconductor device [16, Fig. 1-8] according to claim 29, wherein the further contact [105, Fig. 2, 12] comprises an opening through which the through-plating [103, Fig. 2, 12] extends, and wherein the further contact [105, Fig. 2, 12] and the through-plating [103, Fig. 2, 12] are electrically insulated from one another by the filler material [201, Fig. 2, 12].
Regarding claim 31, Zitzlsperger et al. teaches:
The semiconductor device [16, Fig. 1-8] according to claim 29, wherein at least an inner region of the recess facing the semiconductor component [107, Fig. 2, 12] is a reflector [203, paragraph [0089], Fig. 2, 12].
Regarding claim 34, Zitzlsperger et al. teaches:
The semiconductor device [16, Fig. 1-8] according to claim 25, wherein at least one side surface of the semiconductor component [107, Fig. 2, 12] extends substantially perpendicular to the top side of the filler material [201, Fig. 2, 12] and is substantially formed by the filler material [201, Fig. 2, 12].
Regarding claim 36, Zitzlsperger et al. teaches:
The semiconductor device [16, Fig. 1-8] according to claim 25, wherein the semiconductor component [107, paragraph [0059-0060], Fig. 2, 12] is bonded to the further contact [105, Fig. 2, 12].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 32 is rejected under 35 U.S.C. 103 as being unpatentable over Zitzlsperger et al. (DE 102015102785 A1), in view of Plössl (DE 102015109333 A1).
Regarding claim 32, Zitzlsperger et al. teaches the semiconductor device [16, Fig. 1-8] according to claim 25.
Zitzlsperger et al. does not teach:
further comprising an at least partially transparent layer arranged on the top side of the filler material, wherein the at least partially transparent layer has light-scattering or light-shaping properties, or, wherein the at least partially transparent layer protects underlying elements or elements of the semiconductor component embedded therein against corrosion.
Plössl teaches:
further comprising an at least partially transparent layer [15, paragraph [0041], [0044], Fig. 6-8] arranged on the top side of the filler material [4/5, Fig. 2-8], wherein the at least partially transparent layer [15, Fig. 6-8] has light-scattering or light-shaping properties, or, wherein the at least partially transparent layer [15, Fig. 6-8] protects underlying elements or elements of the semiconductor component [2, Fig. 1-8] embedded therein against corrosion.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Plössl into the teachings of Zitzlsperger et al. to include further comprising an at least partially transparent layer arranged on the top side of the filler material, wherein the at least partially transparent layer has light-scattering or light-shaping properties, or, wherein the at least partially transparent layer protects underlying elements or elements of the semiconductor component embedded therein against corrosion. The ordinary artisan would have been motivated to modify Zitzlsperger et al. in the above manner for the purpose of protecting features within, improving optical performance, light distribution and utilization, and reducing optical loss.
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Zitzlsperger et al. (DE 102015102785 A1), in view of Choi et al. (US 20170103966 A1).
Regarding claim 33, Zitzlsperger et al. teaches the semiconductor device [16, Fig. 1-8] according to claim 25.
Zitzlsperger et al. does not teach:
further comprising solder pads arranged on the connection points.
Choi et al. teaches:
further comprising solder pads [250, paragraph [0036], Fig. 2-3] arranged on the connection points.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Choi et al. into the teachings of Zitzlsperger et al. to include further comprising solder pads arranged on the connection points. The ordinary artisan would have been motivated to modify Zitzlsperger et al. in the above manner for the purpose of including external connections for subsequent processing and mechanical stability, and improving thermal management.
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Zitzlsperger et al. (DE 102015102785 A1), in view of Hussell et al. (US 20130328070 A1).
Regarding claim 35, Zitzlsperger et al. teaches:
the semiconductor device [16, Fig. 1-8] according to claim 25, wherein at least one of the at least one conductor track [1003, paragraph [0032], [0099], [0108], Claim 10, Fig. 12], comprises printed and/or sintered copper or silver layers.
Zitzlsperger et al. does not teach:
at least one of the through-plating and the further contact comprises printed and/or sintered copper or silver layers.
Hussell et al. teaches:
at least one of the through-plating [33/34, paragraph [0033-0034], Fig. 5] and the further contact [30, paragraph [0033-0034], Fig. 5] comprises printed and/or sintered copper or silver layers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Hussell et al. into the teachings of Zitzlsperger et al. to include the at least one of the through-plating and the further contact comprises printed and/or sintered copper or silver layers. The ordinary artisan would have been motivated to modify Zitzlsperger et al. in the above manner for the purpose of improving conductivity and adhesion.
Claims 37-42 are rejected under 35 U.S.C. 103 as being unpatentable over Zitzlsperger et al. (DE 102015102785 A1), in view of Medendorp et al. (US 20150021628 A1).
Regarding claim 37, Zitzlsperger et al. teaches:
A method for manufacturing a semiconductor device [1201, paragraph [0085], Fig. 12], the method comprising: depositing an electrically conductive material to form a through-plating [103, paragraph [0089], Fig. 12] on an auxiliary carrier [101, paragraph [0059], [0061], Fig. 2, 12];
arranging a semiconductor component [107, paragraph [0059], Fig. 2, 12] at a distance from the through-plating [103, Fig. 2, 12], the component [107, Fig. 2, 12] having a first electrical contact surface on a top side of the component [107, Fig. 2, 12] and a second electrical contact surface on a bottom side of the component [107, Fig. 2, 12] opposite the top side; [Inherent]
introducing a filler material [201, paragraph [0062], Fig. 2, 12] in such a way that the through-plating [103, Fig. 2, 12] is enclosed by the filler material [201, Fig. 2, 12], as seen from a circumferential direction, and in such a way that the semiconductor component [107, Fig. 2, 12] is enclosed by the filler material [201, Fig. 2, 12] in the circumferential direction,
wherein the filler material [201, Fig. 2, 12] covers at least a partial region of a side surface of the component [107, Fig. 2, 12] which connects the top side and the bottom side of the component [107, Fig. 2, 12]; and
electrically connecting the first electrical contact surface and the through-plating [103, Fig. 2, 12] by at least one conductor track [1003, paragraph [0089], Fig. 12].
Zitzlsperger et al. does not teach:
depositing an electrically conductive material layer by layer.
Medendorp et al. teaches:
depositing an electrically conductive material layer by layer [paragraph [0112], Fig. 8].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Medendorp et al. into the teachings of Zitzlsperger et al. to include depositing an electrically conductive material layer by layer. The ordinary artisan would have been motivated to modify Zitzlsperger et al. in the above manner for the purpose of omitting wire bonds, creating better connections, and lowering cost of production.
Regarding claim 38, Zitzlsperger et al. and Medendorp et al. teach the method according to claim 37.
Zitzlsperger et al. further teaches:
wherein depositing the electrically conductive material to form the through-plating [103, paragraph [0063], Fig. 2, 12] and depositing an electrically conductive material to form a further contact [105, paragraph [0063], Fig. 2, 12] on the auxiliary carrier [101, paragraph [0059], [0061], Fig. 2, 12] at a distance from the through-plating [103, Fig. 2, 12] is performed.
Zitzlsperger et al. does not teach:
depositing an electrically conductive material layer by layer and depositing an electrically conductive material layer by layer substantially simultaneously.
Medendorp et al. teaches:
depositing an electrically conductive material layer by layer [paragraph [0112], Fig. 8], and depositing an electrically conductive material layer by layer [paragraph [0112], Fig. 8] substantially simultaneously [paragraph [0009], [0082], Fig. 8].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Medendorp et al. into the teachings of Zitzlsperger et al. and Medendorp et al. to include depositing an electrically conductive material layer by layer and depositing an electrically conductive material layer by layer substantially simultaneously. The ordinary artisan would have been motivated to modify Zitzlsperger et al. and Medendorp et al. in the above manner for the purpose of omitting wire bonds, creating better connections, and lowering cost of production.
Regarding claim 39, Zitzlsperger et al. and Medendorp et al. teach the method according to claim 37.
Zitzlsperger et al. does not teach:
wherein at least one of depositing the electrically conductive material layer-by-layer to form the through-plating or depositing an electrically conductive material layer-by-layer to form a further contact comprises 3D printing and/or hardening/sintering.
Medendorp et al. teaches:
wherein at least one of depositing the electrically conductive material layer-by-layer to form the through-plating [822A/822B, paragraph [0111-0112], Fig. 8] or depositing an electrically conductive material layer-by-layer to form a further contact [804, paragraph [0111-0112], Fig. 8] comprises 3D printing and/or hardening/sintering.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Medendorp et al. into the teachings of Zitzlsperger et al. and Medendorp et al. to include wherein at least one of depositing the electrically conductive material layer-by-layer to form the through-plating or depositing an electrically conductive material layer-by-layer to form a further contact comprises 3D printing and/or hardening/sintering. The ordinary artisan would have been motivated to modify Zitzlsperger et al. and Medendorp et al. in the above manner for the purpose of omitting wire bonds, creating better connections, lowering cost of production, using 3D printing because it is faster, highly precise, can deposit multiple materials simultaneously, highly customizable, and improves thermal management leading to improved accuracy and speed.
Regarding claim 40, Zitzlsperger et al. and Medendorp et al. teach the method according to claim 37.
Zitzlsperger et al. further teaches:
wherein at least one of depositing the electrically conductive material to form the through-plating [103, Fig. 2, 12] or depositing an electrically conductive material to form a further contact [105, Fig. 2, 12]
Zitzlsperger et al. does not teach:
depositing the electrically conductive material layer by layer and comprising:
depositing the electrically conductive material;
stripping off an excess material;
melting or fixing the material in desired areas;
curing the material in the desired areas; and
removing an uncured material.
Medendorp et al. teaches:
wherein at least one of depositing the electrically conductive material layer by layer [paragraph [0112], Fig. 8] to form the through-plating [822A/822B, paragraph [0112], Fig. 8] or depositing an electrically conductive material layer by layer [paragraph [0112], Fig. 8] to form a further contact [804, paragraph [0112], Fig. 8] comprises:
depositing the electrically conductive material;
stripping off an excess material;
melting or fixing the material in desired areas;
curing the material in the desired areas; and
removing an uncured material [paragraph [0050]]
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Medendorp et al. into the teachings of Zitzlsperger et al. and Medendorp et al. to include depositing the electrically conductive material layer by layer and comprising: depositing the electrically conductive material; stripping off an excess material; melting or fixing the material in desired areas; curing the material in the desired areas; and removing an uncured material. The ordinary artisan would have been motivated to modify Zitzlsperger et al. and Medendorp et al. in the above manner for the purpose of forming a continuous interconnected structure in desired shape and size.
Regarding claim 41, Zitzlsperger et al. and Medendorp et al. teach the method according to claim 37.
Zitzlsperger et al. further teaches:
wherein introducing the filler material [201, Fig. 2, 12] is conducted after arranging the semiconductor device [Fig. 1-2], and wherein introducing the filler material [201, paragraph [0062-0064], [0096], Fig. 2, 12] comprises a casting process or a transfer molding process.
Regarding claim 42, Zitzlsperger et al. and Medendorp et al. teach the method according to claim 37.
Zitzlsperger et al. does not teach:
wherein introducing the filler material by a layer-by-layer deposition of the electrically insulating material to form the filler material is conducted substantially simultaneously with a layer-by-layer deposition of the electrically conductive material to form the through-plating, and wherein deposited layers to form the through-plating and layers to form the filler material have substantially the same thickness.
Medendorp et al. teaches:
wherein introducing the filler material [814A/814B/814C, paragraph [0112], Fig. 8] by a layer-by-layer deposition of the electrically insulating material to form the filler material [814A/814B/814C, Fig. 8] is conducted substantially simultaneously with a layer-by-layer deposition of the electrically conductive material to form the through-plating [822A/822B, paragraph [0112], Fig. 8], and wherein deposited layers to form the through-plating [822A/822B, Fig. 8] and layers to form the filler material [814A/914B/814C, Fig. 8] have substantially the same thickness.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Medendorp et al. into the teachings of Zitzlsperger et al. and Medendorp et al. to include wherein introducing the filler material by a layer-by-layer deposition of the electrically insulating material to form the filler material is conducted substantially simultaneously with a layer-by-layer deposition of the electrically conductive material to form the through-plating, and wherein deposited layers to form the through-plating and layers to form the filler material have substantially the same thickness. The ordinary artisan would have been motivated to modify Zitzlsperger et al. and Medendorp et al. in the above manner for the purpose of increasing density, improving connections between features, electrically connecting features within the device and electrically insulating other features within the device, and preventing short circuits.
Claims 43-44 are rejected under 35 U.S.C. 103 as being unpatentable over Zitzlsperger et al. (DE 102015102785 A1), in view of Medendorp et al. (US 20150021628 A1) as applied to claim 37 above, and further in view of Schwarz et al. (JP 6261718 B2).
Regarding claim 43, Zitzlsperger et al. and Medendorp et al. teach the method according to claim 37.
Zitzlsperger et al. and Medendorp et al. do not teach:
wherein introducing the filler material comprises creating a cavity in which the semiconductor device is placed.
Schwarz et al. teaches:
wherein introducing the filler material [44, paragraph [0069], [0072], Fig. 4B, 5B] comprises creating a cavity [45, paragraph [0069], Fig. 4B, 5B] in which the semiconductor device [2, paragraph [0069], Fig. 4B, 5B] is placed.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Schwarz et al. into the teachings of Zitzlsperger et al. and Medendorp et al. to include wherein introducing the filler material comprises creating a cavity in which the semiconductor device is placed. The ordinary artisan would have been motivated to modify Zitzlsperger et al. and Medendorp et al. in the above manner for the purpose of improving connections, increasing density, protecting features within device, and ensuring reliability and performance.
Regarding claim 44, Zitzlsperger et al., Medendorp et al., and Schwarz et al. teach the method according to claim 43.
Schwarz et al. further teaches:
further comprising filling a gap between the semiconductor device [2, Fig. 4B, 5B] and the cavity [45, Fig. 4B, 5B] with the filler material [3, paragraph [0050], [0069], Fig. 4B, 5B].
Claims 45-48 are rejected under 35 U.S.C. 103 as being unpatentable over Zitzlsperger et al. (DE 102015102785 A1), in view of Medendorp et al. (US 20150021628 A1) as applied to claim 37 above, and further in view of Plössl (DE 102015109333 A1).
Regarding claim 45, Zitzlsperger et al. and Medendorp et al. teach the method according to claim 37.
Zitzlsperger et al. and Medendorp et al. do not teach:
further comprising detaching the auxiliary carrier.
Plössl teaches:
further comprising detaching the auxiliary carrier [1/12, paragraph [0040-0041], Fig. 1-6].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Plössl into the teachings of Zitzlsperger et al. and Medendorp et al. to include further comprising detaching the auxiliary carrier. The ordinary artisan would have been motivated to modify Zitzlsperger et al. and Medendorp et al. in the above manner for the purpose of electrically connect subsequent features, improving performance, efficiency and charge transportation.
Regarding claim 46, Zitzlsperger et al., Medendorp et al. and Plössl teach the method according to claim 45.
Zitzlsperger et al. further teaches:
wherein electrically connecting a first electrical contact area and the through-plating [103, Fig. 2, 12] by the at least one conductor track [1003, Fig. 12].
Zitzlsperger et al. and Plössl do not teach:
wherein electrically connecting a first electrical contact area and the through-plating by the at least one conductor track comprises 3D printing or hardening/sintering.
Medendorp et al. teaches:
wherein electrically connecting a first electrical contact area [810-1, paragraph [0112], Fig. 8] and the through-plating [822B, paragraph [0112], Fig. 8] by the at least one conductor track [824B, paragraph [0112], Fig. 8] comprises 3D printing or hardening/sintering.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Medendorp et al. into the teachings of Zitzlsperger et al., Medendorp et al. and Plössl to include wherein electrically connecting a first electrical contact area and the through-plating by the at least one conductor track comprises 3D printing or hardening/sintering. The ordinary artisan would have been motivated to modify Zitzlsperger et al., Medendorp et al. and Plössl in the above manner for the purpose of electrically connecting features within the device, using 3D printing because it is faster, highly precise, can deposit multiple materials simultaneously, highly customizable, and improves thermal management leading to improved accuracy and speed.
Regarding claim 47, Zitzlsperger et al., Medendorp et al. and Plössl teach the method according to claim 45.
Zitzlsperger et al., and Medendorp et al. do not teach:
wherein after, before or during detaching the auxiliary carrier, the semiconductor component is rotated, and a first connection point and a second connection point are arranged on the surface of the semiconductor component facing the auxiliary carrier after the auxiliary carrier has been detached, and
wherein the first connection point is electrically connected to the at least one conductor track via the through-plating and the second connection point is electrically connected to the second electrical contact surface.
Plössl teaches:
wherein after, before or during detaching the auxiliary carrier [1/12, paragraph [0040-0041], Fig. 1-6], the semiconductor component [2, paragraph [0040], Fig. 4-5] is rotated, and a first connection point [11, paragraph [0037-0040], Fig. 4-8] and a second connection point [10, paragraph [0037-0040], Fig. 4-8] are arranged on the surface of the semiconductor component [2, Fig. 4-6] facing the auxiliary carrier [1/12, Fig. 1-8] after the auxiliary carrier [1/12, Fig. 1-8] has been detached, and
wherein the first connection point [11, Fig. 4-8] is electrically connected to the at least one conductor track [14, Fig. 5-8] via the through-plating [3, Fig. 1-9] and the second connection point [10, Fig. 4-8] is electrically connected to the second electrical contact surface [10, Fig. 4-8].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Plössl into the teachings of Zitzlsperger et al., Medendorp et al. and Plössl to include wherein after, before or during detaching the auxiliary carrier, the semiconductor component is rotated, and a first connection point and a second connection point are arranged on the surface of the semiconductor component facing the auxiliary carrier after the auxiliary carrier has been detached, and wherein the first connection point is electrically connected to the at least one conductor track via the through-plating and the second connection point is electrically connected to the second electrical contact surface. The ordinary artisan would have been motivated to modify Zitzlsperger et al., Medendorp et al. and Plössl in the above manner for the purpose of electrically connect features within the device and for subsequent processing.
Regarding claim 48, Zitzlsperger et al., and Medendorp et al. teach the method according to claim 37.
Zitzlsperger et al., and Medendorp et al. do not teach:
further comprising depositing an at least partially transparent layer on a top side of the filler material, wherein the at least partially transparent layer has light-scattering or light-shaping properties, or wherein the at least partially transparent layer protects underlying elements or elements of the semiconductor component embedded therein from corrosion.
Plössl teaches:
further comprising depositing an at least partially transparent layer [15, paragraph [0041], [0044], Fig. 6-8] on a top side of the filler material [4/5, Fig. 2-8], wherein the at least partially transparent layer [15, Fig. 4-8] has light-scattering or light-shaping properties, or wherein the at least partially transparent layer [15, Fig. 4-8] protects underlying elements or elements of the semiconductor component [2, Fig. 1-8] embedded therein from corrosion.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to incorporate the teachings of Plössl into the teachings of Zitzlsperger et al., and Medendorp et al. to include further comprising depositing an at least partially transparent layer on a top side of the filler material, wherein the at least partially transparent layer has light-scattering or light-shaping properties, or wherein the at least partially transparent layer protects underlying elements or elements of the semiconductor component embedded therein from corrosion. The ordinary artisan would have been motivated to modify Zitzlsperger et al., and Medendorp et al. in the above manner for the purpose of protecting features within, improving optical performance, light distribution and utilization, and reducing optical loss.
Conclusion
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/D.M.H./Examiner, Art Unit 2815 10/17/2025
/MONICA D HARRISON/Primary Examiner, Art Unit 2815