DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Receipt of the Amendment, filed on February 5, 2026, is acknowledged.
Cancellation of claim 2 has been entered.
Claims 1 and 3-20 are pending in the instant application.
The indicated allowability of claims 7-8 and 18-19 is withdrawn in view of the newly discovered reference(s) to Hatano et al. (US 2014/0103385 A1). Rejections based on the newly cited reference(s) follow.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 3 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 3 states “wherein the insulated metal block covers an outer edge of the corresponding pixel electrode”, the recitation renders the claim indefinite since it contradicts the previous limitation of “an outer edge of the pixel electrode is flush with an outer edge of the corresponding insulated metal block”. It is unclear how the metal block can cover an outer edge of the corresponding pixel electrode and at the same time be flush with an outer edge of the corresponding pixel electrode.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5, 7-14, 17 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hatano et al. (US 2014/0103385 A1).
Regarding claim 1, Hatano discloses a display panel (Fig. 4A), comprising a substrate (410), a driver layer (416, ¶[0062]) and a pixel layer stacked in sequence, wherein the pixel layer comprises a pixel electrode layer (118b), an insulated metal layer (155), a pixel definition layer (150), an electroluminescence layer (120) and a common electrode layer (122) stacked in sequence on a side of the driver layer (416) away from the substrate; wherein the pixel electrode layer (118) comprises a pixel electrode, and the insulated metal layer comprises an insulated metal block (155, ¶[0140,0124]) corresponding to the pixel electrode; the insulated metal block (155) and the pixel definition layer (150) are provided with a pixel opening that exposes the corresponding pixel electrode (118b); and an insulated lateral slot (156) that surrounds the pixel opening and opens at the pixel opening, is provided between the insulated metal block (155) and the pixel opening; and wherein the electroluminescence layer (120) covers the pixel opening, and a thickness of the electroluminescence layer (120) in a direction perpendicular to the substrate is equal to or greater than a thickness of the insulated metal block (Fig. 4A); wherein an outer edge of the pixel electrode (118b) is flush with an outer edge of the corresponding insulated metal block (155).
Regarding claim 3, Hatano discloses a display panel wherein the insulated metal block (155) covers an outer edge of the corresponding pixel electrode (embodiment shown in Fig. 3B).
Regarding claim 5, Hatano discloses a display panel wherein the insulated metal block comprises a metal layer (¶[0140,0124]).
Regarding claim 7, Hatano discloses a display panel wherein a material of a surface of the pixel electrode layer away from the substrate is a conductive metal oxide (¶[0123]).
Regarding claim 8, Hatano discloses a display panel wherein the electroluminescence layer comprises a first organic light-emitting layer (141), a charge generation layer (142, ¶[0180]) and a second organic light-emitting layer (143) stacked in sequence on a side of the pixel electrode away from the substrate; and wherein the charge generation layer (142) is discontinuous at an edge of the pixel opening close to the substrate (Fig. 4A).
Regarding claim 9, Hatano discloses a display panel wherein the insulated metal block (155) is in a closed annular structure (Figs. 6A-6D); and an orthographic projection of the pixel opening corresponding to the pixel electrode on the substrate, is within an orthographic projection of an inner cavity of the insulated metal block corresponding to the pixel electrode on the substrate (Figs. 6A-6D).
Regarding claim 10, Hatano discloses a display device, comprising a display panel, wherein the display panel comprises: a substrate (410), a driver layer (416) and a pixel layer stacked in sequence; wherein the pixel layer comprises a pixel electrode layer (118b), an insulated metal layer (155, ¶[0140,0124]), a pixel definition layer (150), an electroluminescence layer (120) and a common electrode layer (122) stacked in sequence on a side of the driver layer away from the substrate; wherein the pixel electrode layer (118b) comprises a pixel electrode, and the insulated metal layer comprises an insulated metal block (155) corresponding to the pixel electrode; the insulated metal block (155) and the pixel definition layer (150) are provided with a pixel opening that exposes the corresponding pixel electrode; and an insulated lateral slot (156) that surrounds the pixel opening and opens at the pixel opening, is provided between the insulated metal block (155) and the pixel opening (Fig. 4A); and wherein the electroluminescence layer (120) covers the pixel opening, and a thickness of the electroluminescence layer (120) in a direction perpendicular to the substrate is equal to or greater than a thickness of the insulated metal block (155, Fig. 4A); wherein an outer edge of the pixel electrode (118b) is flush with an outer edge of the corresponding insulated metal block (155, Fig. 4A).
Regarding claim 11, Hatano discloses a method for preparing a display panel (Figs. 8A-8E), comprising: forming a driver layer (103) on a side of a substrate (101); and forming a pixel layer on a side of the driver layer away from the substrate (Fig. 7E), the pixel layer comprising a pixel electrode layer (118b), an insulated metal layer (155, ¶[0140,0124]), a pixel definition layer (150), an electroluminescence layer (120, Fig. 4A) and a common electrode layer (122, Fig. 4A) stacked in sequence on the side of the driver layer away from the substrate; wherein the pixel electrode layer comprises a pixel electrode (118b), and the insulated metal layer comprises an insulated metal block (155) corresponding to the pixel electrode; the insulated metal block (155) and the pixel definition layer (150) are provided with a pixel opening that exposes the corresponding pixel electrode (188b); an insulated lateral slot (156) that surrounds the pixel opening and opens at the pixel opening, is provided between the insulated metal block (155) and the pixel opening; and the electroluminescence layer (120) covers the pixel opening, and a thickness of the electroluminescence layer (120) in a direction perpendicular to the substrate is equal to or greater than a thickness of the insulated metal block (155, Fig. 4A); wherein an outer edge of the pixel electrode (118b) is flush with an outer edge of the corresponding insulated metal block (155, Fig. 4A).
Regarding claim 12, Hatano discloses a method for preparing a display panel (Figs. 8A-8E) wherein forming the pixel layer on the side of the driver layer away from the substrate, comprises: forming a pixel electrode material layer (118) and an insulated metal material layer (155a) sequentially on the side of the driver layer away from the substrate (Fig. 8A); patterning the pixel electrode material layer (1118) and the insulated metal material layer (155a) to form a pixel electrode and an insulated metal intermediate portion corresponding to and stacked with the pixel electrode (Fig. 8C); forming the pixel definition layer (150) on a side of the insulated metal intermediate portion away from the substrate, the pixel definition layer (150) having a pixel top opening that exposes part of the insulated metal intermediate portion (Fig. 8D); etching the exposed part of the insulated metal intermediate portion using the pixel definition layer as a mask (Fig. 8E, ¶[0144]), and forming a pixel bottom opening and the insulated lateral slot (156) that expose at least part of the pixel electrode (Fig. 8E), the insulated lateral slot (156) being interconnected to the pixel bottom opening and surrounding the pixel bottom opening (Figs. 6A-6D); and forming the electroluminescence layer (120) and the common electrode layer (122) sequentially on a side of the pixel definition layer (150) away from the substrate, the thickness of the electroluminescence layer (120) being equal to or greater than a thickness of the insulated metal material layer (155, Fig. 4A).
Regarding claim 13, Hatano discloses a method for preparing a display panel (Figs. 8A-8E) wherein forming the pixel layer (118) on the side of the driver layer (103) away from the substrate, comprises: forming the pixel electrode layer (118) on the side of the driver layer (118) away from the substrate (101), the pixel electrode layer (118) comprising the pixel electrode; forming an insulated metal intermediate portion (155a) corresponding to the pixel electrode on a side of the pixel electrode layer away from the substrate (Fig. 8A), the insulated metal intermediate portion (155a) covering the corresponding pixel electrode; forming the pixel definition layer (150) on a side of the insulated metal intermediate portion away from the substrate, the pixel definition layer (150) having a pixel top opening that exposes part of the insulated metal intermediate portion; etching the exposed part of the insulated metal intermediate portion using the pixel definition layer as a mask (¶[0144]), and forming a pixel bottom opening and the insulated lateral slot (156) that expose at least part of the pixel electrode (Fig. 8E), the insulated lateral slot (156) being interconnected to the pixel bottom opening and surrounding the pixel bottom opening (Fig. 6A-6D); and forming the electroluminescence layer (120) and the common electrode layer (122) sequentially on a side of the pixel definition layer away from the substrate (Fig. 4A), the thickness of the electroluminescence layer (120) being equal to or greater than a thickness of the insulated metal intermediate portion (155, Fig. 4A).
Regarding claim 14, Hatano discloses a method for preparing a display panel wherein etching the exposed part of the insulated metal intermediate portion using the pixel definition layer as the mask, comprises: performing wet etching (¶[0125,0144], using TMAH as an etchant) on the insulated metal intermediate portion, and continuing etching the insulated metal intermediate portion after the insulated metal intermediate portion exposes the pixel electrode until remaining insulated metal intermediate portion shrinks to be within a coverage of the pixel definition layer to form the insulated lateral slot (Figs. 4A and 8E).
Regarding claim 17, Hatano discloses a method for preparing a display panel wherein the insulated metal intermediate portion comprises a metal layer (¶[0124]).
Regarding claim 19, Hatano discloses a method for preparing a display panel wherein the electroluminescence layer (120) comprises a first organic light-emitting layer (141), a charge generation layer (142, ¶[0180]) and a second organic light-emitting layer (143) stacked in sequence on a side of the pixel electrode away from the substrate; and when the electroluminescence layer (120) is formed on a side of the pixel definition layer away from the substrate, the charge generation layer (142) is discontinuous at an edge of the pixel opening close to the substrate (Fig. 4A).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hatano et al. (US 2014/0103385 A1).
Regarding claims 4 and 16, Hatano fails to state a thickness of the insulated metal intermediate portion ranges from 100 to 1000 A. One skilled in the art would reasonably contemplate optimization of the insulated metal intermediate portion within the claimed range in order to prevent disconnection of the common electrode and prevent a decrease in thickness of the common electrode, as an obvious matter of design engineering. It has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. It would have been obvious to one having ordinary skill in the art at the time the invention was made to provide a thickness of the insulated metal intermediate portion ranges from 100 to 1000 A in order to prevent disconnection of the common electrode and prevent a decrease in thickness of the common electrode, since optimization of workable ranges is considered within the skill of the art.
Claim(s) 6, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hatano et al. (US 2014/0103385 A1) in view of Yan et al. (CN 114497161, of record).
Regarding claims 6 and 20, Hatano fails to disclose wherein the insulated metal block comprises a first metal layer and a second metal layer stacked in sequence on a side of the pixel electrode away from the substrate, a metal activity of the second metal layer being weaker than a metal activity of the first metal layer; and wherein the second metal layer protrudes from the first metal layer at an edge of the insulated metal block close to the insulated lateral slot.
Yan discloses a display panel, comprising a substrate (31), a pixel layer (Fig. 4), wherein the pixel layer comprises a pixel electrode layer (34) on the substate, an insulated metal layer (322/321/323, Fig. 7), a pixel definition layer (324), an electroluminescence layer (33) and a common electrode layer (35) stacked in sequence on a side away from the substrate; wherein the pixel electrode layer comprises a pixel electrode (34), and the insulated metal layer comprises an insulated metal block (322/321/323) corresponding to the pixel electrode; the insulated metal block (322/321/323) and the pixel definition layer (324) are provided with a pixel opening that exposes the corresponding pixel electrode (34); and an insulated lateral slot (A) that surrounds the pixel opening and opens at the pixel opening, is provided between the insulated metal block and the pixel opening (Fig. 4); and wherein the electroluminescence layer (133) covers the pixel opening, and a thickness of the electroluminescence layer (133) in a direction perpendicular to the substrate is equal to or greater than a thickness of the insulated metal block (Fig. 4), wherein the insulated metal block comprises a first metal layer (321) and a second metal layer (323) stacked in sequence on a side of the pixel electrode away from the substrate, a metal activity of the second metal layer being weaker than a metal activity of the first metal layer (¶[0081]); and wherein the second metal layer (323) protrudes from the first metal layer at an edge of the insulated metal block close to the insulated lateral slot (Fig. 7) in order to block a sub-pixel side leakage path and reduce lateral leakage. Thus, it would have been obvious to one of ordinary skill in the art at the time of effective filling of the claimed invention to incorporate the insulated metal block as disclosed by Yan in the display panel of Hatano in order to block a sub-pixel side leakage path and reduce lateral leakage.
Regarding claim 18, Hatano discloses wherein when the exposed part of the insulated metal intermediate portion is etched using the pixel definition layer as the mask, the insulated metal intermediate portion is patterned as the insulated metal block, but fails to disclose wherein the insulated metal intermediate portion comprises a first metal layer and a second metal layer stacked in sequence on a side of the pixel electrode away from the substrate, a metal activity of the second metal layer being weaker than a metal activity of the first metal layer; and the second metal layer protrudes from the first metal layer at an edge of the insulated metal block close to the insulated lateral slot.
Yan discloses a method for preparing a display panel (Fig. 7), comprising: forming a pixel layer (33/34) on a side of a substrate (31), the pixel layer comprising a pixel electrode layer (33), an insulated metal layer (322/323/321), a pixel definition layer (324), an electroluminescence layer (33) and a common electrode layer (35) stacked in sequence on the side of the substrate; wherein the pixel electrode layer comprises a pixel electrode (34), and the insulated metal layer comprises an insulated metal block (322/321/323) corresponding to the pixel electrode; the insulated metal block (322/321/323) and the pixel definition layer (324) are provided with a pixel opening that exposes the corresponding pixel electrode (Fig. 7); an insulated lateral slot (Fig. 7) that surrounds the pixel opening and opens at the pixel opening, is provided between the insulated metal block (322/321/323) and the pixel opening; and the electroluminescence layer (33) covers the pixel opening, and a thickness of the electroluminescence layer (33) in a direction perpendicular to the substrate is equal to or greater than a thickness of the insulated metal block (Fig. 7); wherein the insulated metal intermediate portion comprises a first metal layer (322) and a second metal layer (323) stacked in sequence on a side of the pixel electrode away from the substrate, a metal activity of the second metal layer being weaker than a metal activity of the first metal layer (¶[0081]); and the second metal layer (323) protrudes from the first metal layer (321) at an edge of the insulated metal block close to the insulated lateral slot (Fig. 7), in order to block a sub-pixel side leakage path and reduce lateral leakage. Thus, it would have been obvious to one of ordinary skill in the art at the time of effective filling of the claimed invention to incorporate the insulated metal block as disclosed by Yan in the method of Hatano in order to block a sub-pixel side leakage path and reduce lateral leakage.
Allowable Subject Matter
Claim 15 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim(s) 15, the references of the Prior Art of record fails to teach or suggest the combination of the limitations as set forth in claim(s) 15, and specifically comprising the limitation of before etching the exposed part of the insulated metal intermediate portion using the pixel definition layer as the mask, the method further comprises: performing heat treatment.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 3-14 and 16-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gao et al. (CN 112397555 A) discloses an organic light emitting diode display comprises: a substrate; TFTs on the substrate; a planarization layer on the TFT; a pixel electrode on the planarization layer, wherein the pixel electrode comprises an upper layer and a lower layer comprising a transparent conductive oxide and an intermediate layer comprising silver; an etching stop layer on the pixel electrode, wherein the upper surface of the pixel electrode is exposed by the etching stop layer; etching the spacer on the stop layer, wherein the upper surface of the pixel electrode is exposed by the spacer; an organic emitting layer on the upper surface of the pixel electrode, wherein the upper surface of the pixel electrode is exposed by the etching stop layer and the spacer; and a common electrode on the organic emitting layer and the spacer, wherein the etching stop layer covers the edge and the side surface of the pixel electrode.
The rejections above rely on the references for all the teachings expressed in the text of the references and/or one of ordinary skill in the art would have reasonably understood or implied from the texts of the references. To emphasize certain aspects of the prior art, only specific portions of the texts have been pointed out. Each reference as a whole should be reviewed in responding to the rejection, since other sections of the same reference and/or various combinations of the cited references may be relied on in future rejections in view of amendments.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mariceli Santiago whose telephone number is (571) 272-2464. The examiner can normally be reached on Monday-Friday from 8:00 AM to 4:00 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James R. Greece, can be reached on (571) 272-3711. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Mariceli Santiago/Primary Examiner, Art Unit 2879