DETAILED ACTION
This office action is in response to amendment filed on 1/15/2026.
Claims 1, 3 – 15, 17, 32 – 34 and 43 are amended.
Claim 2 is cancelled.
Claims 1, 3 – 15, 17, 32 – 34 and 43 are pending.
35 USC 112(b) rejection of claim 1 is withdrawn in view of the amendment.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are: first scheduling unit, first computation unit, first sending unit, second scheduling unit, second computation unit and second sending unit in claim 34.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3 – 9, 15, 32, 33 and 43 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang (US 20150121391, hereinafter Wang), in view of Broughton et al (USPAT 7080365, hereinafter Broughton), and further in view of Cheng (USPAT 10620958).
As per claim 1, Wang discloses: A circuit for inter-chip communication, comprising;
a first scheduling unit configured to receive a first task descriptor; (Wang [0009]: “after receiving a task which is required to be executed, a main central processing unit (CPU) of the system on chip (SOC) obtaining a dynamic execution parameter of the task”. Examiner notes that the main CPU is mapped to the claimed “scheduling unit”)
a sending unit; a first computation unit configured to: receive the first task descriptor from the first scheduling unit, wherein the first task descriptor includes a parameter size (Wang [0018]: “the dynamic execution parameter comprises the maximum number of the CPUs executing the task in parallel”), configuration information of the first computational unit (Wang [0017]: “the dynamic execution parameter comprises the type of a CPU executing the task”); process data according to the first task descriptor to obtain processed data; send the processed data to the sending unit, wherein the sending unit, under control of the first computation unit, is configured to send the processed data in response to the reception of the processed data. (Wang [0041]: “the main CPU determining, according to one or more currently available subsidiary CPUs in the SOC, a task allocation solution which meets the dynamic execution parameter; and the main CPU scheduling, in accordance with the task allocation solution, one or more subsidiary CPUs to execute the task”; [0042]: “the selected subsidiary CPU schedule subsidiary CPUs in the plurality of subsidiary CPUs to execute the task; each subsidiary CPU executes the distributed tasks in parallel and returns results of task execution to the selected subsidiary CPU. The selected CPU receives the results of task execution fed back by each subsidiary CPU, and feeds back a summary of the results fed back by each subsidiary CPU to the main CPU. The main CPU receives the summary of the results of the selected subsidiary CPUs and outputs a task execution result.”. Examiner notes that the subsidiary CPU is mapped to the claimed “first computation unit”.)
Wang did not explicitly disclose:
wherein the first task descriptor includes a task identifier (ID), a task category, a data size, a data address;
wherein the sending unit sends the processed data off-chip;
However, Broughton teaches
wherein the first task descriptor includes a task identifier (ID), a task category, a data size, a data address; (Broughton col 29, line 55 – col 30, line 15.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Broughton into that of Wang in order to have the wherein the first task descriptor includes a task identifier (ID), a task category, a data size, a data address. Wang [0017] and [0018] teaches some of the examples of the “dynamic execution parameter” of the tasks being type of CPU executing the task or maximum number of CPUs executing the task in parallel. One of ordinary skill in the art can easily see that other types of task information can easily be included, without deviating from the general teaching of Wang. Broughton col 29, line 55 – col 30, line 15 merely shown that the claimed limitations are commonly known and used data for a task, applicants have merely claimed the combination of known parts in the field to achieve the predictable results of enhanced scheduling and execution of tasks and is therefore rejected under 35 USC 103.
Cheng teaches
wherein the sending unit sends the processed data off-chip; (Cheng col 8, lines 42 – 52.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Cheng into that of Wang and Broughton in order to have the sending unit sends the processed data off-chip. Wang [0041] – [0042] the subsidiary CPUs send the processing result back to the main CPU. However, one of ordinary skill in the art can easily see that the processing result can be easily sent off-chip too, such as sending it to off-chip storage as taught by Cheng reference, without deviating from the general teaching of the prior arts. Applicants have, applicants have merely claimed the combination of known parts in the field to achieve the predictable results of enhanced scheduling and execution of tasks and is therefore rejected under 35 USC 103.
As per claim 3, the combination of Wang, Broughton and Cheng further teach:
The circuit for inter-chip communication of claim 1, wherein the first scheduling unit is further configured to receive the first task descriptor from a host; an receive the data from one of the host or a first storage unit. (Wang [0005])
As per claim 4, the combination of Wang, Broughton and Cheng further teach:
The circuit for inter-chip communication of claim 1, further comprising a monitor unit, wherein the monitor unit is configured to monitor transmission of the processed data from the first computation unit to the sending unit; and send a first instructing signal to the first scheduling unit according to the transmission of the processed data from the first computation unit to the sending unit, and the first scheduling unit is further configured to instruct the first computation unit to release computation resources according to the first instructing signal. (Wang [0060] – [0062])
As per claim 5, the combination of Wang, Broughton and Cheng further teach:
The circuit for inter-chip communication of claim 4, wherein the sending unit is further configured to receive the processed data from the first computation unit, and send a feedback signal in response to the reception the processed data, the monitor unit is further configured to send a second instructing signal to the first scheduling unit according to the feedback signal, and the first scheduling unit is further configured to instruct the first computation unit to release computation resources according to the second instructing signal. (Wang [0060] – [0062])
As per claim 6, the combination of Wang, Broughton and Cheng further teach:
The circuit for inter-chip communication of claim 5 wherein the first computation unit is further configured to send a first finish signal after the transmission of the processed data is finished, the monitor unit is further configured to send the first instructing signal to the first scheduling unit in response to monitoring the first finish signal, wherein the first finish signal indicates the transmission of the processed data is finished, and the first scheduling unit is further configured to instruct the first computation unit to release the computation resources according to the first instructing signal. (Wang [0060] – [0062])
As per claim 7, the combination of Wang, Broughton and Cheng further teach:
The circuit for inter-chip communication of claim 6, wherein, when the second instructing signal is sent to the first scheduling unit according to the feedback signal, the monitor unit is further configured to comprising: monitoring the feedback signal sent from the sending unit to the first computation unit, and sending the second instructing signal to the first scheduling unit based on the monitoring of the feedback signal. (Wang [0060] – [0062])
As per claim 8, the combination of Wang, Broughton and Cheng further teach:
The circuit for inter-chip communication of claim 6, wherein the sending unit is further configured to send a second finish signal in response to the reception of the feedback signal, and wherein when the monitor unit is further configured to send the second instructing signal to the first scheduling unit according to the feedback signal, the monitor unit is further configured to send the second instructing signal to the first scheduling unit according to monitored second finish signal sent from the first computation unit. (Wang [0060] – [0061])
As per claim 9, the combination of Wang, Broughton and Cheng further teach:
The circuit for inter-chip communication of claim 4, wherein the monitor unit is further configured to: send a third instructing signal to the first scheduling unit in response to one of non-reception of a feedback signal within scheduled time, or reception of an incorrect feedback signal; and according to the third instructing signal, the first scheduling unit is further configured to instruct the first computation unit to: resend the processed data; and retrieve the released computation resources to recompute the processed data. (Wang [0061] – [0062])
As per claim 15, it is the method variant of claim 1 and is therefore rejected under the same rationale.
As per claim 32, it is the method variant of claim 4 and is therefore rejected under the same rationale.
As per claim 33, it is the method variant of claim 5 and is therefore rejected under the same rationale.
As per claim 43, Wang discloses: A system for inter-chip communication, comprising a first chip and a second chip, wherein the first chip comprises a first scheduling unit, a first computation unit, and a sending unit,
wherein the first scheduling unit is configured to a first task descriptor; (Wang [0009]: “after receiving a task which is required to be executed, a main central processing unit (CPU) of the system on chip (SOC) obtaining a dynamic execution parameter of the task”.)
the first computation unit is configured to receive the first task descriptor from the first scheduling unit wherein the first task descriptor includes a parameter size (Wang [0018]: “the dynamic execution parameter comprises the maximum number of the CPUs executing the task in parallel”), configuration information of the first computational unit (Wang [0017]: “the dynamic execution parameter comprises the type of a CPU executing the task”); process first data according to the first task descriptor to obtain first processed data; send the first processed data to the sending unit; the sending unit, under control of the first computation unit, is configured to send the first processed data in response to reception of the first processed data; (Wang [0041]: “the main CPU determining, according to one or more currently available subsidiary CPUs in the SOC, a task allocation solution which meets the dynamic execution parameter; and the main CPU scheduling, in accordance with the task allocation solution, one or more subsidiary CPUs to execute the task”; [0042]: “the selected subsidiary CPU schedule subsidiary CPUs in the plurality of subsidiary CPUs to execute the task; each subsidiary CPU executes the distributed tasks in parallel and returns results of task execution to the selected subsidiary CPU. The selected CPU receives the results of task execution fed back by each subsidiary CPU, and feeds back a summary of the results fed back by each subsidiary CPU to the main CPU. The main CPU receives the summary of the results of the selected subsidiary CPUs and outputs a task execution result.”.)
and the second chip comprises a second scheduling unit; a second computation unit; a receiving unit; and a second storage unit, wherein the receiving unit is configured to:
receive [a second task]; send the first processed data to the second storage unit; notify the second scheduling unit that the first processed data is received; the second scheduling unit is configured to: receive second task descriptor; (Wang [0009]: “after receiving a task which is required to be executed, a main central processing unit (CPU) of the system on chip (SOC) obtaining a dynamic execution parameter of the task”.)
instruct the second computation unit to process the first processed data; the second computation unit is configured to: acquire the first processed data from the second storage unit; receive the second task descriptor from the second scheduling unit; and process the first processed data according to the second task descriptor to obtain second processed data. (Wang [0041]: “the main CPU determining, according to one or more currently available subsidiary CPUs in the SOC, a task allocation solution which meets the dynamic execution parameter; and the main CPU scheduling, in accordance with the task allocation solution, one or more subsidiary CPUs to execute the task”; [0042]: “the selected subsidiary CPU schedule subsidiary CPUs in the plurality of subsidiary CPUs to execute the task; each subsidiary CPU executes the distributed tasks in parallel and returns results of task execution to the selected subsidiary CPU. The selected CPU receives the results of task execution fed back by each subsidiary CPU, and feeds back a summary of the results fed back by each subsidiary CPU to the main CPU. The main CPU receives the summary of the results of the selected subsidiary CPUs and outputs a task execution result.”.)
Wang did not explicitly disclose:
wherein the first task descriptor includes a task identifier (ID), a task category, a data size, a data address;
wherein the sending unit sends the processed data to the second chip;
However, Broughton teaches
wherein the first task descriptor includes a task identifier (ID), a task category, a data size, a data address; (Broughton col 29, line 55 – col 30, line 15.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Broughton into that of Wang in order to have the wherein the first task descriptor includes a task identifier (ID), a task category, a data size, a data address. Wang [0017] and [0018] teaches some of the examples of the “dynamic execution parameter” of the tasks being type of CPU executing the task or maximum number of CPUs executing the task in parallel. One of ordinary skill in the art can easily see that other types of task information can easily be included, without deviating from the general teaching of Wang. Broughton col 29, line 55 – col 30, line 15 merely shown that the claimed limitations are commonly known and used data for a task, applicants have merely claimed the combination of known parts in the field to achieve the predictable results of enhanced scheduling and execution of tasks and is therefore rejected under 35 USC 103.
Cheng teaches
wherein the sending unit sends the processed data to the second chip; (Cheng col 8, lines 42 – 52.)
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Cheng into that of Wang and Broughton in order to have the sending unit sends the processed data off-chip. Wang [0041] – [0042] the subsidiary CPUs send the processing result back to the main CPU. However, one of ordinary skill in the art can easily see that the processing result can be easily sent off-chip too, such as sending it to off-chip storage as taught by Cheng reference, without deviating from the general teaching of the prior arts. Applicants have, applicants have merely claimed the combination of known parts in the field to achieve the predictable results of enhanced scheduling and execution of tasks and is therefore rejected under 35 USC 103.
Claim(s) 10 – 14 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wang, Broughton and Cheng, and further in view of Kaveri et al (US 20190324801, hereinafter Kaveri).
As per claim 10, Wang, Broughton and Cheng did not teach:
The circuit for inter-chip communication of claim 1, wherein the first computation unit is further configured to: receive the first task descriptor from the first scheduling unit, execute a first task according to the first task descriptor; suspend the first task in response to a case where a first specific event happens; and execute a second task in response to suspending the first task.
However, Kaveri teaches:
The circuit for inter-chip communication of claim 1, wherein the first computation unit is further configured to: receive the first task descriptor from the first scheduling unit, execute a first task according to the first task descriptor; suspend the first task in response to a case where a first specific event happens; and execute a second task in response to suspending the first task. (Kaveri [0014])
It would have been obvious for one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Kaveri into that of Wang, Broughton and Cheng in order to receive the first task description information from the first scheduling unit and execute a first task according to the first task description information; suspend the first task in response to a case where a first specific event happens; and execute a second task in response to suspending the first task. Kaveri has shown that the claimed limitations are merely commonly known steps for managing concurrent execution of tasks, applicants have thus merely claimed the combination of known parts in the field to achieve predictable results and is therefore rejected under 35 USC 103.
As per claim 11, the combination of Wang, Broughton, Cheng and Kaveri further teach:
The circuit of claim 10, wherein the first scheduling unit is configured to send second task descriptor to the first computation unit in response to suspending the first task by the first computation unit; and the first computation unit is further configured to execute the second task in response to receiving the second task descriptor. (Kaveri [0014] - [0016])
As per claim 12, the combination of Wang, Broughton, Cheng and Kaveri further teach:
The circuit for inter-chip communication of claim 10, wherein the first computation unit is configured to: suspend the first task in response to a case where the sending of processed data by the sending unit is blocked; and suspend the first task in response to a case where the caching of the processed data by the a first storage unit is failed; and suspend the first task in response to a case where the first task comprises a suspension instruction. (Kaveri [0014] - [0016])
As per claim 13, the combination of Wang, Broughton, Cheng and Kaveri further teach:
The circuit for inter-chip communication of claim 11, wherein each of the first computation unit and the first scheduling unit comprise a task execution list, and the task execution list at least comprises a position where the first task is suspended. (Kaveri [0014] - [0016])
As per claim 14, the combination of Wang, Broughton, Cheng and Kaveri further teach:
The circuit for inter-chip communication of claim 13, wherein the first computation unit is further configured to resume the first task according to the position where the execution of the first task is suspended in response to an end of the specific events, when a plurality of tasks are suspended, one of the plurality of tasks is resumed randomly, or a specific task with a highest priority is resumed according to priorities of the plurality of tasks, and the plurality of tasks include the specific task. (Kaveri [0014] - [0016])
As per claim 17, it is the method variant of claim 12 and is therefore rejected under the same rationale.
Conclusion
Applicant’s arguments with respect to claim(s) 1, 3 – 14, 17, 32 – 34 and 43 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHARLES M SWIFT whose telephone number is (571)270-7756. The examiner can normally be reached Monday - Friday: 9:30 AM - 7PM.
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/CHARLES M SWIFT/Primary Examiner, Art Unit 2196