DETAILED ACTION
This Action is responsive to the RCE filed on 04/08/2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/08/2026 has been entered.
Claim Status
Claims 1-18 are amended. Claims 1-18 are pending and have been examined.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Specifically, the claim limitations that are being interpreted under 35 U.S.C. 112(f) are:
“means for processing” of Claim 17, 2-3rd lines; examiner determines the corresponding structure for performing claimed function is ‘processing circuitry 4’ [Fig. 2]; support found in Specification pg. 11 / Claim 1
“means for caching context information translations” of Claim 17, 5th line; examiner determines the corresponding structure for performing claimed function is ‘context information translation cache 10’ [Fig. 2]; support found in Specification pg. 11 / Claim 1
“means for performing a lookup” of Claim 17, 8th line; examiner determines the corresponding structure for performing claimed function is ‘lookup circuitry 14’ [Fig. 2]; support found in Specification pg. 11 / Claim 1
Examiner Note
Claim 18 recites the following limitations:
A method comprising:
in response to a context-information-dependent instruction processed by processing circuitry:
performing a lookup of a context information translation cache by looking up specified context information specified for the context-information-dependent instruction in the context information translation cache and by comparing the specified context information against one or more of a plurality of context information translation entries, the specified context information indicative of a specified execution context,
where the context information translation cache is configured to store the plurality of context information translation entries each specifying a mapping between untranslated context information and translated context information
based on the lookup, identifying whether the context information translation cache includes a matching context information translation entry which is valid and which specifies the untranslated context information corresponding to the specified context information
when the context information translation cache is identified as including the matching context information translation entry
causing a context-information-dependent operation to be performed based on the translated context information specified by the matching context information translation entry.
Claim 18 recites the following contingent limitations:
in response to a context-information-dependent instruction processed by processing circuitry:
performing a lookup of a context information translation cache by looking up specified context information specified for the context-information-dependent instruction in the context information translation cache and by comparing the specified context information against one or more of a plurality of context information translation entries, the specified context information indicative of a specified execution context,
where the context information translation cache is configured to store the plurality of context information translation entries each specifying a mapping between untranslated context information and translated context information
based on the lookup, identifying whether the context information translation cache includes a matching context information translation entry which is valid and which specifies the untranslated context information corresponding to the specified context information
when the context information translation cache is identified as including the matching context information translation entry
causing a context-information-dependent operation to be performed based on the translated context information specified by the matching context information translation entry.
The limitations are contingent because they recite steps that are only required to be performed if their conditions precedent are met. Limitations a) through f) only need to be performed “in response to a context-information-dependent instruction processed by processing circuitry”. Therefore, in an embodiment whereby no context-information-dependent instruction is processed by processing circuitry, none of steps a) through f) will be performed.
Therefore, the BRI of Claim 18 does not require any of steps a) through f) to be performed.
In addition, examiner notes that even in embodiments whereby step a) is performed, Claim 18 recites additional contingent limitations. In particular, Claim 18 recites the following contingent limitations:
causing a context-information-dependent operation to be performed based on the translated context information specified by the matching context information translation entry.
Limitation f) only needs to be performed if limitation e) is met. Therefore, in embodiments whereby limitation e) is not performed (i.e., no matching entry which is valid is identified in the context information translation cache), limitation f) is not performed.
Therefore, even if Claim 18 were to require step a) to be performed, the BRI of Claim 18 only requires limitations a) through d) to be performed.
See MPEP 2111.04 for additional details.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-10 and 17-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Krueger (US 20180203807 A1)(cited by examiner in Final Rejection 11/12/2025; see pg. 47)(hereafter referred to as Krueger).
Regarding Claim 1,
Krueger anticipates the following limitations:
An apparatus comprising:
processing circuitry (Processing Clusters 4, Fig. 1) responsive to a context-information-dependent instruction (Fig. 7, step 116) to cause a context-information-dependent operation (Fig. 7, step 150) to be performed based on specified context information indicative of a specified execution context (“software execution environments” [0059] // Fig. 4) – (“FIG. 4 shows a number of different software execution environments … Each of these software execution environments can be allocated a given partition identifier” [0059] // “At step 110 the processing element determines that a memory transaction needs to be issued .. At step 112 the processing element selects one of the partition ID registers … At 114, the processor determines … an instruction access … the partition ID used for resource partitioning depends on whether the access is for data or an instruction” [0077-83] // “At step 150 of FIG. 7, the memory transaction is issued [0102] // Fig. 7) – As taught in Krueger, software applications are executed within respective “execution environments” which are each allocated a “partition identifier”. As clarified in Fig. 7, processing circuitry generates a memory instruction (step 116) directed to a particular partition id (i.e., generates “a context-information-dependent instruction”) which in turn causes a corresponding memory transaction (step 150) to be performed (i.e., performing “a context-information-dependent operation”)--;
a context information translation cache (Remapping Circuitry 130, Fig. 9) to store a plurality of context information translation entries (“remapping entries” [0086]) each specifying a mapping between untranslated context information (“virtual partition ID” [0086]) and translated context information (“physical partition ID” [0086])(Fig. 9 // “the remapping registers 126, 128 define a remapping table which provides a number of remapping entries for mapping the virtual partition IDs used by that guest operating system to physical partition IDs within the global operating space” [0086]) – As shown in Fig. 9, remapping circuitry 130 includes a remapping table which maps a virtual partition ID (i.e., “untranslated context information”) to a physical partition ID (i.e., “translated context information”)--; and
lookup circuitry (“selection circuitry” [0087] // Fig. 8) to perform a lookup (Fig. 7, step 122) of the context information translation cache (“At step 120, the processing element determines whether virtualization is enabled for the read partition ID … If virtualization is enabled … at step 122 at least one of the partition IDs read at step 116 or 118 is mapped to a physical partition ID appended to the memory transaction to be issued” [0084] // Fig. 9) – As shown in Fig. 7, during step 122, the virtual physical ID is remapped to a physical partition ID using the remapping table of Fig. 9--
by looking up the specified context information (“indexed based on the virtual partition ID” [0086]) specified for the context-information-dependent instruction in the context information translation cache (Fig. 9) and by comparing the specified context information against one or more of the plurality of context information translation entries (Fig. 9 // “The remapping table is indexed based on the virtual partition ID used by the operating system and returns a corresponding physical partition ID in the global ID space … The virtual partition ID … is used to select a corresponding remapping entry from the remapping registers 128. In this example each remapping register 128 includes four remapping entries” [0086-87]) – As shown in Fig. 9, the virtual partition ID (read during step 116) is used as an index into the remapping table to identify a corresponding entry in the remapping table--,
to identify whether the context information translation cache includes a matching context information translation entry which is valid (¶0088) and which specifies the untranslated context information corresponding to the specified context information (“the IDs … are passed via remapping circuitry 130. The virtual partition ID … is used to select a corresponding remapping entry … The physical partition ID is read from the selected remapping entry … when virtualization is enabled, the physical partition ID is used.… Each remapping entry is associated with a corresponding valid bit … The valid bit for a given remapping entry specifies whether that virtual-to-physical partition ID mapping is valid” [0087-88]) – As taught in ¶¶0087-88 and as shown in Fig. 9, the virtual partition ID is indexed into the remapping table to identify a corresponding remapping entry which specifies a corresponding physical partition ID (i.e., “a matching context information translation entry” which “specifies the untranslated context information corresponding to the specified context information”) and which further includes a valid bit specifying that the remapping entry is still valid (i.e., a matching remapping entry “which is valid”)-- and
when the context information translation cache is identified as including the matching context information translation entry, to cause the context-information-dependent operation to be performed (Fig. 7, step 150) based on the translated context information specified by the matching context information translation entry. (“At step 150, the memory transaction is issued specifying the PMG and PARTID (… following remapping at step 122)” [0102]) – As clarified in ¶0102, during step 150, a memory transaction including the translated partition ID (translated during step 122; i.e., including “the translated context information specified by the matching” remapping table entry) is issued.
Regarding Claim 2,
Krueger anticipates the following limitations:
The apparatus according to claim 1, in which the context information translation cache is a software-managed cache. (“Each memory system component … may have a set of parameter registers … configuration software first stores a partition ID to configure into the selector register” [0126]) – As taught in ¶0126, “configuration software” establishes partition IDs for a system by storing configuration parameters into registers. Accordingly, the remapping table of Fig. 9 is considered as “a software-managed cache”.
Regarding Claim 3,
Krueger anticipates the following limitations:
The apparatus according to claim 1, in which when the lookup of the context information translation cache fails to identify any matching context information translation entry (Fig. 10), the lookup circuitry is configured to trigger (Fig. 10, step 144) signalling of an exception. (“FIG. 10 is a flow diagram illustrating step 122 in more detail. At step 140, it is determined whether the partition ID being remapped is out of range … at step 146, it is determined whether the corresponding remapping entry is valid … If the current ID is not valid, then again at step 144 an exception event is signalled to trap to EL2” [0097-98] // Fig. 7) – As shown in Fig. 10, when no valid partition ID is identified during the lookup of step 122 (see Fig. 7; i.e., when the lookup “fails to identify any matching” remapping entry), an exception event is triggered to trap to EL2.
Regarding Claim 4,
Krueger anticipates the following limitations:
The apparatus according to claim 1, in which the processing circuitry is configured to execute instructions at one of a plurality of privilege levels (“exception levels” [0057]), the plurality of privilege levels including at least: a first privilege level (EL0, Fig. 4), a second privilege level (EL1, Fig. 4) with greater privilege than the first privilege level, and a third privilege level (EL2, Fig. 4) with greater privilege than the second privilege level. (Fig. 4 // “the architecture supports four different exception levels EL0 to EL3 increasing in privilege level [0057] // “generate the partition ID of the current memory transaction, in dependence on at least the current exception level” [0077] // ¶0054) – As shown in Fig. 4 and taught in ¶0057, software instructions can be executed in one of four “exception levels” with increasing privilege.
Regarding Claim 5,
Krueger anticipates the following limitations:
The apparatus according to claim 4, in which the context-information- dependent instruction is allowed to be executed at the first privilege level. (“Applications 80 are executed at the lowest privilege level EL0” [0057] // Fig. 4 // ¶0077) – As shown in Fig. 4, instructions for applications 80 are processed at the lowest exception level EL0 (see also ¶0077).
Regarding Claim 6,
Krueger anticipates the following limitations:
The apparatus according to claim 4,
in which in response to the context information-dependent instruction, the processing circuitry is configured to read (Fig. 7, step 112) the specified context information from a context information storage location (partition ID registers 100, Fig. 9)(“At step 112, the processing element selects one of the partition ID registers … in dependence on at least the current exception level” [0077]) – As shown in Figs. 7 + 9, during step 112, the processing element uses the current exception level to select a particular partition ID register 100 to read from in order to obtain the corresponding virtual partition ID associated with the current exception level--
which is updatable in response to an instruction executed at the second privilege level. (Table 4 // “an attempt to set the partition ID register 100 from within the same exception state when not allowed by a higher exception state causes an exception event which triggers a switch to a higher exception state. An exception handler at the higher exception state can then decide how the partition ID should be set” [0069] // Fig. 9) – As shown in Table 4 and detailed in ¶0069, certain partition ID registers (e.g., MPAM0_EL1, MPAM1_EL1, and MPAM1_EL1_S) are able to be written to at EL1.
Regarding Claim 7,
Krueger anticipates the following limitations:
The apparatus according to claim 6 (see Claim 6 limitation mappings above), in which the processing circuitry is configured to allow the context information storage location to be updated in response to the instruction executed at the second privilege level without requiring a trap to the third privilege level. (Table 4 // Fig. 9 // ¶0069) – As previously discussed (see Claim 6 limitation mappings above), certain partition registers are able to be written to at EL1 and thus do not need to be updated at a higher exception level (i.e., at EL2; see Table 4; i.e., “without requiring a trap to the third privilege level”).
Regarding Claim 8,
Krueger anticipates the following limitations:
The apparatus according to claim 6, in which each context information translation entry also specifies a second-privilege-level context identifier (“PARTID_D” [0060]) indicative of a second- privilege level execution context associated with a mapping between the untranslated context information and the translated context information specified by that context information translation entry (“Each partition ID register 100 comprises fields for up to three partition IDs… Table 2 below summarizes which partition ID register 100 is used for memory transactions executed in each operating state” [0060] // Table 2 // Figs. 7 + 9) – As taught in ¶0060 and as shown in Table 2, up to three types of partition ID (e.g., “PARTID_D”, “PARTID_I”, and “PMG”) are stored in registers 100 and serve as the basis for the virtual partition ID used as a lookup by Remapping Circuitry 130. Examiner accordingly considers a PARTID_D type of virtual partition ID used for data accesses as “a second-privilege-level context identifier” which is distinct from a PARTID_I type of virtual partition ID used for instruction accesses (see Fig. 7, steps 116 + 118); and
in the lookup of the context information translation cache, the lookup circuitry is configured to identify, as the matching context information translation entry, a context information translation entry which is valid, specifies the untranslated context information corresponding to the specified context information (Krueger; see Claim 1 limitation mappings above) – As previously discussed (see Claim 1 limitation mappings above) and as taught in Krueger, a lookup by remapping circuitry 130 uses a PARTID_I to identify a corresponding physical partition ID which is valid--, and
specifies (Fig. 7, step 118) the second-privilege-level context identifier corresponding to a current second-privilege-level context associated with the context-information-dependent instruction. (“At step 114, the processing element determines whether the memory access is an instruction access or a data access … if the access is a data access then at step 118 the PMG and PARTID_D fields are read. Hence, the partition ID used for resource partitioning depends on whether the access is for data or an instruction (although in some cases both may nevertheless specify the same partition ID)” [0083]) – As clarified in ¶0083, for data type accesses, the PARTID_D associated with the data access is used to identify a corresponding matching entry (i.e., entries “specif[y]” “the second-privilege-level context identifier” when performing “the lookup of the context information translation cache” corresponding to a data type of access).
Regarding Claim 9,
Krueger anticipates the following limitations:
The apparatus according to claim 4, in which when the lookup of the context information translation cache fails to identify any matching context information translation entry (Fig. 10), the lookup circuitry is configured to trigger (Fig. 10, step 144) signalling of an exception to be handled at the third exception level. (“FIG. 10 is a flow diagram illustrating step 122 in more detail. At step 140, it is determined whether the partition ID being remapped is out of range … at step 146, it is determined whether the corresponding remapping entry is valid … If the current ID is not valid, then again at step 144 an exception event is signalled to trap to EL2” [0097-98] // Fig. 7) – As shown in Fig. 10, when no valid partition ID is identified during the lookup of step 122 (see Fig. 7; i.e., when the lookup “fails to identify any matching” remapping entry), an exception event is triggered to trap to EL2.
Regarding Claim 10,
Krueger anticipates the following limitations:
The apparatus according to claim 4, in which the context information translation entries (Remapping Registers 126, 128, Fig. 9) of the context information translation cache are allowed to be updated in response to an instruction executed at the third privilege level (Fig. 4) and are prohibited from being updated in response to an instruction executed at the first privilege level or the second privilege level. (“The global partition ID space may be controlled by the hypervisor at EL2 … The hypervisor may restrict a guest operating system executing at EL1 to use only a small range of partition IDs (e.g., starting from zero) and the remapping registers 126, 128 define a remapping table” [0085-86]) – As disclosed in ¶¶0085-86, a hypervisor operating at EL2 controls the global partition ID space and can restrict guest operating systems executing at EL1 to particular ranges of partition IDs using the remapping registers 126 + 128. As shown in Fig. 4, guest operating systems execute applications at EL0. Accordingly, the remapping registers 126 + 128 are “allowed to be updated by” a hypervisor operating at EL2, instead of (i.e., “prohibited from being updated”) by a guest OS operating at EL1 or by an application executing in EL0.
Regarding Claim 17,
Krueger anticipates the following limitations:
An apparatus comprising:
means for processing (Processing Clusters 4, Fig. 1), responsive to a context-information-dependent instruction (Fig. 7, step 116) to cause a context-information-dependent operation (Fig. 7, step 150) to be performed based on specified context information indicative of a specified execution context (“software execution environments” [0059] // Fig. 4) – (“FIG. 4 shows a number of different software execution environments … Each of these software execution environments can be allocated a given partition identifier” [0059] // “At step 110 the processing element determines that a memory transaction needs to be issued .. At step 112 the processing element selects one of the partition ID registers … At 114, the processor determines … an instruction access … the partition ID used for resource partitioning depends on whether the access is for data or an instruction” [0077-83] // “At step 150 of FIG. 7, the memory transaction is issued [0102] // Fig. 7) – As taught in Krueger, software applications are executed within respective “execution environments” which are each allocated a “partition identifier”. As clarified in Fig. 7, processing circuitry generates a memory instruction (step 116) directed to a particular partition id (i.e., generates “a context-information-dependent instruction”) which in turn causes a corresponding memory transaction (step 150) to be performed (i.e., performing “a context-information-dependent operation”)--;
means for caching context information translations (Remapping Circuitry 130, Fig. 9), to store a plurality of context information translation entries (“remapping entries” [0086]) each specifying a mapping between untranslated context information (“virtual partition ID” [0086]) and translated context information (“physical partition ID” [0086])(Fig. 9 // “the remapping registers 126, 128 define a remapping table which provides a number of remapping entries for mapping the virtual partition IDs used by that guest operating system to physical partition IDs within the global operating space”) – As shown in Fig. 9, remapping circuitry 130 includes a remapping table which maps a virtual partition ID (i.e., “untranslated context information”) to a physical partition ID (i.e., “translated context information”)--; and
means for performing a lookup of the means for caching (“selection circuitry” [0087] // Fig. 8) by looking up the specified context information (“indexed based on the virtual partition ID” [0086]) specified for the context-information-dependent instruction in the context information translation cache (Fig. 9) and by comparing the specified context information against one or more of the plurality of context information translation entries (Fig. 9 // “The remapping table is indexed based on the virtual partition ID used by the operating system and returns a corresponding physical partition ID in the global ID space … The virtual partition ID … is used to select a corresponding remapping entry from the remapping registers 128. In this example each remapping register 128 includes four remapping entries” [0086-87]) – As shown in Fig. 9, the virtual partition ID (read during step 116) is used as an index into the remapping table to identify a corresponding entry in the remapping table--,
to identify whether the means for caching includes a matching context information translation entry which is valid (¶0088) and which specifies the untranslated context information corresponding to the specified context information (“the IDs … are passed via remapping circuitry 130. The virtual partition ID … is used to select a corresponding remapping entry … The physical partition ID is read from the selected remapping entry … when virtualization is enabled, the physical partition ID is used.… Each remapping entry is associated with a corresponding valid bit … The valid bit for a given remapping entry specifies whether that virtual-to-physical partition ID mapping is valid” [0087-88]) – As taught in ¶¶0087-88 and as shown in Fig. 9, the virtual partition ID is indexed into the remapping table to identify a corresponding remapping entry which specifies a corresponding physical partition ID (i.e., “a matching context information translation entry” which “specifies the untranslated context information corresponding to the specified context information”) and which further includes a valid bit specifying that the remapping entry is still valid (i.e., a matching remapping entry “which is valid”)--, and
when the means for caching is identified as including the matching context information translation entry, to cause the context-information-dependent operation to be performed (Fig. 7, step 150) based on the translated context information specified by the matching context information translation entry. (“At step 150, the memory transaction is issued specifying the PMG and PARTID (… following remapping at step 122)” [0102]) – As clarified in ¶0102, during step 150, a memory transaction including the translated partition ID (translated during step 122; i.e., including “the translated context information specified by the matching” remapping table entry) is issued.
Regarding Claim 18,
Krueger anticipates the following limitations:
A method comprising: (Fig. 3 // “fetching instructions from the instruction cache 10” [0053]) – As taught in Krueger, before processing a context-information dependent instruction, the context-information dependent instruction is fetched from an instruction cache. --
in response to a context-information-dependent instruction processed by processing circuitry: performing a lookup of a context information translation cache by looking up specified context information specified for the context-information-dependent instruction in the context information translation cache and by comparing the specified context information against one or more of a plurality of context information translation entries, the specified context information indicative of a specified execution context, where the context information translation cache is configured to store the plurality of context information translation entries each specifying a mapping between untranslated context information and translated context information; based on the lookup, identifying whether the context information translation cache includes a matching context information translation entry which is valid and which specifies the untranslated context information corresponding to the specified context information; and when the context information translation cache is identified as including the matching context information translation entry, causing a context-information-dependent operation to be performed based on the translated context information specified by the matching context information translation entry. – As previously discussed (see Examiner Note above), the BRI of Claim 18 does not require any of the aforementioned limitations to be performed (see MPEP 2111.04). Therefore, Krueger anticipates all limitations under the BRI of Claim 18.
In addition, even if Claim 18 were interpreted as requiring each limitation to be performed, Krueger nonetheless anticipates the following limitations:
in response to a context-information-dependent instruction (Fig. 7, step 116) processed by processing circuitry(Processing Clusters 4, Fig. 1) (“FIG. 4 shows a number of different software execution environments … Each of these software execution environments can be allocated a given partition identifier” [0059] // “At step 110 the processing element determines that a memory transaction needs to be issued .. At step 112 the processing element selects one of the partition ID registers … At 114, the processor determines … an instruction access … the partition ID used for resource partitioning depends on whether the access is for data or an instruction” [0077-83] // “At step 150 of FIG. 7, the memory transaction is issued [0102] // Fig. 7) – As taught in Krueger, software applications are executed within respective “execution environments” which are each allocated a “partition identifier”. As clarified in Fig. 7, processing circuitry generates a memory instruction (step 116) directed to a particular partition id (i.e., generates “a context-information-dependent instruction”) which in turn causes a corresponding memory transaction (step 150) to be performed (i.e., performing “a context-information-dependent operation”)--;
performing a lookup of a context information translation cache (Remapping Circuitry 130, Fig. 9) by looking up specified context information (“indexed based on the virtual partition ID” [0086]) specified for the context-information-dependent instruction in the context information translation cache (Fig. 9) and by comparing the specified context information against one or more of a plurality of context information translation entries (Fig. 9 // “The remapping table is indexed based on the virtual partition ID used by the operating system and returns a corresponding physical partition ID in the global ID space … The virtual partition ID … is used to select a corresponding remapping entry from the remapping registers 128. In this example each remapping register 128 includes four remapping entries” [0086-87]) – As shown in Fig. 9, the virtual partition ID (read during step 116) is used as an index into the remapping table to identify a corresponding entry in the remapping table--,
the specified context information indicative of a specified execution context(“software execution environments” [0059] // Fig. 4),
where the context information translation cache is configured to store the plurality of context information translation entries (“remapping entries” [0086]) each specifying a mapping between untranslated context information (“virtual partition ID” [0086]) and translated context information (“physical partition ID” [0086])(Fig. 9 // “the remapping registers 126, 128 define a remapping table which provides a number of remapping entries for mapping the virtual partition IDs used by that guest operating system to physical partition IDs within the global operating space”) – As shown in Fig. 9, remapping circuitry 130 includes a remapping table which maps a virtual partition ID (i.e., “untranslated context information”) to a physical partition ID (i.e., “translated context information”)--;
based on the lookup, identifying whether the context information translation cache includes a matching context information translation entry which is valid (¶0088) and which specifies the untranslated context information corresponding to the specified context information (“the IDs … are passed via remapping circuitry 130. The virtual partition ID … is used to select a corresponding remapping entry … The physical partition ID is read from the selected remapping entry … when virtualization is enabled, the physical partition ID is used.… Each remapping entry is associated with a corresponding valid bit … The valid bit for a given remapping entry specifies whether that virtual-to-physical partition ID mapping is valid” [0087-88]) – As taught in ¶¶0087-88 and as shown in Fig. 9, the virtual partition ID is indexed into the remapping table to identify a corresponding remapping entry which specifies a corresponding physical partition ID (i.e., “a matching context information translation entry” which “specifies the untranslated context information corresponding to the specified context information”) and which further includes a valid bit specifying that the remapping entry is still valid (i.e., a matching remapping entry “which is valid”)--; and
when the context information translation cache is identified as including the matching context information translation entry, causing a context-information-dependent operation to be performed (Fig. 7, step 150) based on the translated context information specified by the matching context information translation entry. (“At step 150, the memory transaction is issued specifying the PMG and PARTID (… following remapping at step 122)” [0102]) – As clarified in ¶0102, during step 150, a memory transaction including the translated partition ID (translated during step 122; i.e., including “the translated context information specified by the matching” remapping table entry) is issued.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Krueger further in view of Evans et al. (WO 2019002810 A1)(cited by examiner in previous action)(hereafter referred to as Evans).
Regarding Claim 15,
Krueger discloses the following limitations:
The apparatus according to claim 1 (see Claim 1 limitation mappings above),
Although Krueger ¶0140 generally discusses data invalidation, Krueger does not disclose the following limitations:
in which when the context- information- dependent instruction is an instruction for causing an address translation cache invalidation request to be issued to request invalidation of address translation data from at least one address translation cache, the context-information-dependent operation comprises issuing the address translation cache invalidation request to request invalidation of address translation data associated with the translated context information specified by the matching context information translation entry.
However, Evans discloses the following limitations:
when the context- information- dependent instruction is an instruction (“Instructions such as virtual address unmapping instructions (VUMAP) and translation lookaside buffer invalidate instructions (TLBI)” [pg. 10, 35th line-end + pg. 11, 1-5th lines]) for causing an address translation cache invalidation request to be issued (“Instructions … are broadcast within the system-on-chip integrated circuit 4” [pg. 11, 1-5th lines]) to request invalidation of address translation data (“serve to purge the use of translation data as specified by those commands” [pg. 11, 1-5th lines]) from at least one address translation cache (Translation Lookaside Buffers 100, Fig. 25 // “purge the use of translation data as specified by those commands from locations within the system” [pg. 11, 1-5th lines]) – As taught in Evans, instructions such as “VUMAP” and “TBLI” are broadcast within a system and cause translation data to be purged at a memory location (e.g., Translation Lookaside Buffers 100 of Fig. 25) within the system--,
the context-information-dependent operation comprises issuing the address translation cache invalidation request to request invalidation of address translation data associated with the translated context information specified by the matching context information translation entry. (Krueger, see Claim 1 limitation mappings above) – As previously discussed (see Claim 1 limitation mappings above) and as taught in Krueger, context-dependent instructions (e.g., such as a TLBI instruction) cause context-dependent operations (e.g., such as purging translation data from a TLB) to be performed in association with translated context information specified by a matching context information translation entry.
Evans and Krueger are considered analogous to the claimed invention because they all relate to the same field of performing context-dependent memory operations on data in storage environments whereby processes executing within distinct contexts access the same memory locations. Therefore, it would have been obvious for someone of ordinary skill in the art before the effective filing date of the claimed invention to have modified Krueger with the teachings of Evans and realize an apparatus whereby context-dependent operations including address translation invalidation operations are performed to invalidate address translation data. Doing so ensures that a memory region, such as a page, will not be used elsewhere within the system when an export operation of the data stored in that memory region is to be performed, as disclosed in Evans pg. 11: “By unmapping (and thus effectively removing) the virtual address translation data for a given memory region (page), it can be ensured that such a memory region will not be in use elsewhere within the system when an export operation of the data stored in that memory region is to be performed” [pg. 11, 15-20th lines]
Regarding Claim 16,
The same motivation to combine provided in Claim 15 is equally applicable to Claim 16. The combined teachings of Krueger and Evans disclose the following limitations:
The apparatus according to claim 15, comprising a system memory management unit (Evans, MMU 26, Fig. 9) to perform address translation on behalf of a peripheral device (Evans, Memory 16, Fig. 9)(“a memory management unit 26 … for caching entries of the translation tables” [pg. 16, 1-25th lines]) – As taught in Evans, an MMU 26 caches address translation entries from translation tables 26 stores on a Memory 16 (i.e., “on behalf of a peripheral device”)--,
where the system memory management unit is configured to support an advance address translation function (Evans, TLBs 100, Fig. 9) in which the peripheral device is allowed to cache pre-translated addresses within an address translation cache (Evans, Translation Tables 120, Fig. 9) of the peripheral device (Evans, “a memory management unit 26, which may include one or more translation lookaside buffers 100 for caching entries of the translation tables” [pg. 16, 1-25th lines]) – As taught in Evans, MMU 26 includes TLBs 100 which cache particular translation entries from translation tables 120 of memory 16--; and
the address translation cache invalidation request is a request to invalidate pre-translated addresses from the address translation cache of the peripheral device (Evans, “Instructions such as virtual address unmapping instructions (VUMAP) and translation look aside buffer invalidate instructions (TLBI) are broadcast … to purge the use of translation data … virtual address unmapping can be performed by modifying a translation table entry by performing a store to memory” [pg. 11, 1-10th lines]) – As taught in Evans, VUMAP instructions are performed by performing a store to a particular translation table entry (i.e., translation table 120 of Fig. 9) located in memory (i.e., Memory 16 of Fig. 9)--
that are associated with the translated context information specified by the matching context information translation entry. (Krueger, see Claim 1 limitation mappings above) --
As previously discussed (see Claim 1 limitation mappings above) and as taught in Krueger, context-dependent instructions (e.g., such as VUMAP) cause context-dependent operations (e.g., such as purging translation data from a translation table entry) to be performed in association with translated context information specified by a matching context information translation entry.
Allowable Subject Matter
Claims 11-14 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 11 recites the following limitations:
An apparatus comprising: processing circuitry responsive to a context-information-dependent instruction to cause a context-information-dependent operation to be performed based on specified context information indicative of a specified execution context; a context information translation cache to store a plurality of context information translation entries each specifying a mapping between untranslated context information and translated context information; and lookup circuitry to perform a lookup of the context information translation cache by looking up the specified context information specified for the context-information-dependent instruction in the context information translation cache and by comparing the specified context information against one or more of the plurality of context information translation entries, to identify whether the context information translation cache includes a matching context information translation entry which is valid and which specifies the untranslated context information corresponding to the specified context information, and when the context information translation cache is identified as including the matching context information translation entry, to cause the context-information-dependent operation to be performed based on the translated context information specified by the matching context information translation entry.
The apparatus according to claim 1, in which when the context- information- dependent instruction is a context-information-dependent type of store instruction specifying a target address and at least one source register, the context-information-dependent operation comprises issuing a store request to a memory system to request writing of store data to at least one memory system location corresponding to the target address, the store data comprising source data read from the at least one source register with a portion of the source data replaced with the translated context information specified by the matching context information translation entry.
The closest prior art of record is Krueger (see limitation mappings above), which discloses a remapping table storing a plurality of entries which translate a virtual partition ID into a physical partition ID (see Fig. 9); a method of replacing a value read from a register with a physical partition ID identified by a matching entry (see Fig. 9); and a general context-information-dependent type of store instruction whereby source data is read from a specified register (see Fig. 3 // ¶0053).
Krueger does not anticipate nor render obvious a context-information-dependent type of store operation whereby a portion of source data read from a specified register is replaced with translated context information specified by a matching entry in a context information translation cache. Specifically, the prior art of record neither anticipates nor renders obvious the claimed concept of “a context-information-dependent type of store instruction specifying a target address and at least one source register, … to request writing of store data to at least one memory system location corresponding to the target address, the store data comprising source data read from the at least one source register with a portion of the source data replaced with the translated context information specified by the matching context information translation entry.” (Emphasis Added) when considered in conjunction with the other limitations recited in independent Claim 1.
Claims 12-14 would all at least be allowable due to their respective claim dependencies.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-18 have been considered but are moot in view of the newly-applied Kreuger reference because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIAN SCOTT MENDEL whose telephone number is (703)756-1608. The examiner can normally be reached M-F 10am - 4pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocío del Mar Pérez-Vélez can be reached at 571-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/J.S.M./Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
Prosecution Insights