DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-15 are pending in this office action.
Claims 1, 5 and 10 are amended.
Response to Arguments
Applicant's arguments filed 12/10/2025 have been fully considered but they are not persuasive.
Applicant’s argument:
Independent claims 1, 5 and 10:
Applicant respectfully asserts that Hubson makes no mention of a updating a register with a value that indicates a status of the programming, including a percentage. Rather, Hubson generically describes the execution of subsequent tasks upon a BIOS being written. Venkatachalam and Bulusu fail to remedy this shortfall of Hubson.
Examiner response:
The issue in the argument is that arts of record fail to discloses write, read an update status of the update. Hubson discloses two register in order to update the BIOS in the flash memory. To write to the memory the register is updated, and when finished it is updated also and the comparison between the register X and Y to infer that the update is finished (0013 and 0026).
Finishing an update is associated with progress status as 100%(Done writing the update), but to emphasize such claim, Bandakka writes and reads the update progress status. The status such as in progress, finished, started can be achieved, but updating the user to see the progress, an update progress status is forwarded and provided to the user as percentage of the update. Such progress percentage can be provided after certain time interval is passed:
[0026] Finally, the methods and systems can provide a user with the ability to see an update status related to individual component updates, and including a percentage progress of the firmware update process, when the firmware update process is scheduled using a remote management software. In order to provide the progress update, the firmware update process can send a message to a remote management server while starting the update process of any component of the firmware, and can also send a message at the end of each component update. The firmware update process can further send the percentage completion of the firmware update process when the upgrade process takes significant time. For example, in the case of updating an O/S which may take from 4 minutes to 40 minutes or more to complete, the firmware update process can send percentage completion information for every 25% of progress”;
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-6 and 8-20 are rejected under 35 U.S.C. 103 as being unpatentable over Hobson et al US20100077199A1 in view of Venkatachalam et al US20090064125A1 and Bulusu et al US20190179628A1 and Bandakka et al US20130125107A1.
As per claim 1, Hobson discloses an electronic device, comprising
a storage circuit:
[0027] SMI logic 190 can be implemented in hardware, including, but not limited to, a programmable logic device (PLD), programmable gate stray (PGA), field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system on chip (SoC), and a system in package (SIP)].
a central processing unit (CPU) coupled to the storage circuit: Fig. 1
the CPU to: during an operation of the CPU, receive a Basic Input/Output System (BIOS) update image for the electronic device:
[0016]“One such condition is when processor 110 writes to a memory unprotect register 350. Thus, when processor 110 writes to memory unprotect register 350, SMI 180 is generated and SMI handler 240 (FIG. 2) executes in SMM mode.”:
[0024] “Normal-mode secure BIOS update code 270 begins with block 510, which loads a buffer with the image of the update for BIOS 160. The image buffer is accessible to both normal-mode code 270 and secure BIOS update handler 250.”;
and responsive to verification of the BIOS update image, store a portion of the BIOS update image in the storage circuit:
[0025]”Processing then continues at block 530, where secure BIOS update handler 250 verifies that the code that wrote to memory unprotect register 350 is trustworthy.
[0024]“The image buffer is accessible to both normal-mode code 270 and secure BIOS update handler 250. In some embodiments, this image contains the entire BIOS 160. In other embodiments, this image contains only a portion of BIOS 160. “;
and an embedded controller coupled to the storage circuit, the embedded controller to: obtain the portion of the BIOS update image from the storage circuit;
[0026] “However, if handler 250 determines that the request code-is trustworthy, the handler prepares to update BIOS 160 by disabling memory protect signal 170. To do so, handier 250 retrieves (block 540) retrieves the value previously written by power on code 210 to register X (320) and stored in a shared location (e.g., SMM RAM 230). At block 550, the retrieved value is written to register Y (330). The presence of the same value in register X (320) and register Y (330) causes SMI logic 190 to deassert memory protect signal 170, thus allowing writes to BIOS 160”;
program the portion of the plurality of portions of the BIOS update image to a BIOS component of the electronic device and update a register with a value indicating a status of the programming,.
[0026] “ Next, at block 550, code from the image prepared by normal-mode code 270 is written to BIOS 160, using techniques known to a person of ordinary skill in the art. When writes to BIOS 160 are finished, block 570 locks or protects BIOS 160 again by writing a different value to register Y (330), causing SMI logic 190 to assert memory protect signal 170 once again.”;
But not explicitly:
without interrupting the operation of the CPU store update.
wherein the BIOS update image is received in a plurality of portions;
update a register with a value, the value comprising a current percentage of the BIOS update image that has been programmed.
Venkatachalam discloses:
wherein the BIOS update image is in multiple portions:
[0049] At block 702, the memory update may be divided into blocks. At block 704, a respective hash corresponding to each of the blocks may be created”;
[0053] “At block 712, a first block may be sent to the target device responsive to the confirmation. At block 714, responsive to a second confirmation verifying that the first block was confirmed by the target device, execution may continue by looping to block 712 and a second block may be sent to the target. Receipt of the second confirmation indicates the target was able to confirm the first block using the respective hash corresponding to the first block that was included in the header 400. This process may be followed until all data blocks are sent, at which time, the `no` branch from block 714 may be followed to block 716 and the download process ended”.
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Venkatachalam into teachings of Hobson for securely downloading an update such as basic input/output system (BIOS) update and a firmware image of a security module, to a constrained memory of the secure module of an electronic device. Because the security module may have limited memory, a memory update process is used that allows individual blocks to be separately downloaded and verified. Verification data is sent in a header block prior to sending the individual data blocks. an update metadata field may include a sequence number or update version number so that data blocks from other updates are distinguishable from data blocks of the current update and a block number so blocks that arrive out of sequence can be correctly stored.[ Venkatachalam 0040].
But not explicitly:
without interrupting the operation of the CPU store update.
update a register with a value, the value comprising a current percentage of the BIOS update image that has been programmed.
Busulu discloses:
without interrupting the operation of the CPU store update.
[0039] “As described earlier, multiple applications may be running on each of the processors 202. According to an aspect of the present disclosure, when the updater 110 ascertains that the BIOS firmware is to be updated, a new processor thread may be created for writing the firmware update to the secondary portion 104-3 of the secondary non-volatile memory 104-2. The new thread may be created at any of the processors 202. Simultaneously, the other application threads may continue to perform the tasks without being interrupted by the update process. Upon writing the firmware update to the secondary non-volatile memory 104-2, the firmware manager 112 may determine if a warm reboot is to be performed”;
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Bulusu into teachings of Hobson and Venkatachalam to perform a multistage firmware update to minimize downtime during a firmware update and to maintain the state of virtual machines. the firmware update does not shut the entire system down, and the operations of the running applications are not interrupted. [Bulusu 0042].
But not explicitly:
update a register with a value, the value comprising a current percentage of the BIOS update image that has been programmed.
Bandakka discloses:
update a register with a value, the value comprising a current percentage of the BIOS update image that has been programmed.
[0084]“Finally, the method provides a process for providing progress updates during the updating process, by sending to the RMS messages indicating the start and end of each update command execution, and by calculating the percentage progress of completion of updates during execution and sending percentage progress status information to the RMS at regular intervals.”;
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Bandakka into teachings of Hobson Bulusu and Venkatachalam to improve the reliability of a firmware update process, the integrity of a firmware installation package on a target client device can be checked prior to beginning the installation of the package on the client device. Furthermore, to avoid receiving update status at the end of the update, the user is notified by a progress of the update in real-time during the update procedure, which component update is executing or what percentage of the update is completed [Bandakka 0022].
As per claim 3, the rejection of claim 1 is incorporated and furthermore Hobson does not explicitly disclose:
wherein the BIOS update image is in multiple portions and the controller is to store the BIOS update image to the storage circuit one portion at a time such that one portion of the multiple portions is present in the storage circuit at a given time.
Venkatachalam discloses:
wherein the BIOS update image is in multiple portions:
[0049] At block 702, the memory update may be divided into blocks. At block 704, a respective hash corresponding to each of the blocks may be created”;
and the controller is to store the BIOS update image to the storage circuit one portion at a time such that one portion of the multiple portions is present in the storage circuit at a given time.
[0053] “At block 712, a first block may be sent to the target device responsive to the confirmation. At block 714, responsive to a second confirmation verifying that the first block was confirmed by the target device, execution may continue by looping to block 712 and a second block may be sent to the target. Receipt of the second confirmation indicates the target was able to confirm the first block using the respective hash corresponding to the first block that was included in the header 400. This process may be followed until all data blocks are sent, at which time, the `no` branch from block 714 may be followed to block 716 and the download process ended”.
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Venkatachalam into teachings of Hobson, Bandakka and Bulusu for securely downloading an update such as basic input/output system (BIOS) update and a firmware image of a security module, to a constrained memory of the secure module of an electronic device. Because the security module may have limited memory, a memory update process is used that allows individual blocks to be separately downloaded and verified. Verification data is sent in a header block prior to sending the individual data blocks. an update metadata field may include a sequence number or update version number so that data blocks from other updates are distinguishable from data blocks of the current update and a block number so blocks that arrive out of sequence can be correctly stored.[ Venkatachalam 0040].
As per claim 4, the rejection of claim 1 is incorporated and furthermore Hubson does not explicitly discloses:
wherein the BIOS update image is a BIOS update for the CPU, and wherein the CPU is to perform processing unrelated to the BIOS update image while the controller programs the portion of the BIOS update image.
Bulusu discloses:
wherein the BIOS update image is a BIOS update for the CPU, and wherein the CPU is to perform processing unrelated to the BIOS update image while the controller programs the portion of the BIOS update image:
[0039] “As described earlier, multiple applications may be running on each of the processors 202. According to an aspect of the present disclosure, when the updater 110 ascertains that the BIOS firmware is to be updated, a new processor thread may be created for writing the firmware update to the secondary portion 104-3 of the secondary non-volatile memory 104-2. The new thread may be created at any of the processors 202. Simultaneously, the other application threads may continue to perform the tasks without being interrupted by the update process. Upon writing the firmware update to the secondary non-volatile memory 104-2, the firmware manager 112 may determine if a warm reboot is to be performed”;
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Bulusu into teachings of Hobson Bandakka and Venkatachalam to perform a multistage firmware update to minimize downtime during a firmware update and to maintain the state of virtual machines. the firmware update does not shut the entire system down, and the operations of the running applications are not interrupted. [Bulusu 0042].
As per claim 5, Hubson discloses an electronic device, comprising:
a central processing unit (CPU):
[0008] “Computer system 100 includes a processor 110, which accesses random access memory (RAM) 120 and flash memory 130 through a communications link, such as bus 140. RAM 120 contains code that is executed by processor 110, such as an operating system 150 and one or more applications 155”;
and a controller, wherein the controller is to: during operation of the CPU obtain a portion of a Basic Input/Output System (BIOS) update image for the electronic device from the CPU:
[0016] “In some embodiments, memory unprotect register 350 is not a separate register, but is implemented as a single bit which is part of an SMI control register (not shown). SMI logic 190 may contain other registers such that logic 340 also generates SMI 180 in response to reads and/or writes to these locations. In some embodiments of system 100, SMI handler 240 reads an SMI status register (not shown) which indicates what particular event caused SMI 180 to be generated.”;
[0024] Normal-mode secure BIOS update code 270 begins with block 510, which loads a buffer with the image of the update for BIOS 160. The image buffer is accessible to both normal-mode code 270 and secure BIOS update handler 250. In some embodiments, this image contains the entire BIOS 160. In other embodiments, this image contains only a portion of BIOS 160. The name and/or location of the image file may be specified by a user, or may be predetermined. Processing continues at block 520, where normal-mode code 270 triggers a system management interrupt (SMI) by writing to memory unprotect register 350.
program the portion of the BIOS update image to a BIOS component of the electronic device:
[0025] Processing then continues at block 530, where secure BIOS update handler 250 verifies that the code that wrote to memory unprotect register 350 is trustworthy.
[0024]“The image buffer is accessible to both normal-mode code 270 and secure BIOS update handler 250. In some embodiments, this image contains the entire BIOS 160. In other embodiments, this image contains only a portion of BIOS 160. “;
update a register with a value indicating a status of the programming:
[0026] “ Next, at block 550, code from the image prepared by normal-mode code 270 is written to BIOS 160, using techniques known to a person of ordinary skill in the art. When writes to BIOS 160 are finished, block 570 locks or protects BIOS 160 again by writing a different value to register Y (330), causing SMI logic 190 to assert memory protect signal 170 once again.”;
But not explicitly:
without interrupting the operation of the CPU, store update
wherein the BIOS update image is received in a plurality of portions;
the value indicating an amount of the BIOS update image that has been programmed;
and generate an interrupt that causes the CPU to provide a second portion of the plurality of portions of the BIOS update image to the controller responsive to the portion of the BIOS update image not being a last portion of the BIOS update image.
Venkatachalam discloses:
wherein the BIOS update image is received in a plurality of portions; verify a signature of the BIOS update image;
[0049] At block 702, the memory update may be divided into blocks. At block 704, a respective hash corresponding to each of the blocks may be created”;
and generate an interrupt that causes the CPU to provide a second portion of the plurality of portions of the BIOS update image to the controller responsive to the portion of the BIOS update image not being a last portion of the BIOS update image.
[0053] “At block 712, a first block may be sent to the target device responsive to the confirmation. At block 714, responsive to a second confirmation verifying that the first block was confirmed by the target device, execution may continue by looping to block 712 and a second block may be sent to the target. Receipt of the second confirmation indicates the target was able to confirm the first block using the respective hash corresponding to the first block that was included in the header 400. This process may be followed until all data blocks are sent, at which time, the `no` branch from block 714 may be followed to block 716 and the download process ended”.
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Venkatachalam into teachings of Hobson for securely downloading an update such as basic input/output system (BIOS) update and a firmware image of a security module, to a constrained memory of the secure module of an electronic device. Because the security module may have limited memory, a memory update process is used that allows individual blocks to be separately downloaded and verified. Verification data is sent in a header block prior to sending the individual data blocks. an update metadata field may include a sequence number or update version number so that data blocks from other updates are distinguishable from data blocks of the current update and a block number so blocks that arrive out of sequence can be correctly stored.[Venkatachalam 0040].
But not explicitly:
without interrupting the operation of the CPU, store update
the value indicating an amount of the BIOS update image that has been programmed;
Busulu discloses:
without interrupting the operation of the CPU store update.
[0039] “As described earlier, multiple applications may be running on each of the processors 202. According to an aspect of the present disclosure, when the updater 110 ascertains that the BIOS firmware is to be updated, a new processor thread may be created for writing the firmware update to the secondary portion 104-3 of the secondary non-volatile memory 104-2. The new thread may be created at any of the processors 202. Simultaneously, the other application threads may continue to perform the tasks without being interrupted by the update process. Upon writing the firmware update to the secondary non-volatile memory 104-2, the firmware manager 112 may determine if a warm reboot is to be performed”;
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Bulusu into teachings of Hobson and Venkatachalam to perform a multistage firmware update to minimize downtime during a firmware update and to maintain the state of virtual machines. the firmware update does not shut the entire system down, and the operations of the running applications are not interrupted. [Bulusu 0042].
But not explicitly:
the value indicating an amount of the BIOS update image that has been programmed;
Bandakka discloses:
the value indicating an amount of the BIOS update image that has been programmed:
[0084]“Finally, the method provides a process for providing progress updates during the updating process, by sending to the RMS messages indicating the start and end of each update command execution, and by calculating the percentage progress of completion of updates during execution and sending percentage progress status information to the RMS at regular intervals.”;
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Bandakka into teachings of Hobson Bulusu and Venkatachalam to improve the reliability of a firmware update process, the integrity of a firmware installation package on a target client device can be checked prior to beginning the installation of the package on the client device. Furthermore, to avoid receiving update status at the end of the update, the user is notified by a progress of the update in real-time during the update procedure, which component update is executing or what percentage of the update is completed [Bandakka 0022].
As per claim 6, the rejection of claim 5 is incorporated and furthermore Hobson discloses:
wherein the controller is to obtain the portion of the BIOS update image from a shared memory accessible to the CPU and the controller and to which the CPU wrote the portion of the BIOS update image:
[0015] More specifically, using techniques further described below in connection with FIGS. 4-5, power on code 210 (see FIG. 2) writes a particular value to register X (320), then saves that particular value into SMM scratchpad 250 (FIG. 2). Later, secure BIOS update handler 250 (FIG. 2) retrieves the value from BUM scratchpad 260 and writes it to register Y (330). Since SMM scratchpad 260 is accessible to processor 110 only in SMM mode, and register X (320) is a writs-only register (i.e., a read by processor 110 after a write will not return the value written), code that is running outside of SMM mode after power up does not "know" the correct value to write to register Y (330) in order to match the value written to register X (320).
As per claim 8, the rejection of claim 5 is incorporated and furthermore Hobson discloses:
wherein the BIOS component is a flash memory component having a serial peripheral interface shared between the BIOS component and the CPU.
[0008] “Flash memory 130 also contains executable code, in particular code 160, known as the Basic input Output System (BIOS). As understood by a person of ordinary skill in the art, BIOS 160 recognizes and controls various hardware devices that make up system 100 (e.g., keyboard, display, disk drive, universal serial bus hub, etc.). In some embodiments system 100 is a personal computer (PC) that is Intel x86 compatible, a computer server, a network attached storage server, and the like.”;
As per claim 9, the rejection of claim 5 is incorporated and furthermore Hobson does not explicitly disclose:
wherein the CPU is not interrupted from performing operations unrelated to the BIOS update image while the portion of the BIOS update image is programed to the BIOS component of the electronic device.
Bulusu discloses:
wherein the CPU is not interrupted from performing operations unrelated to the BIOS update image while the portion of the BIOS update image is programed to the BIOS component of the electronic device;
[0039] “As described earlier, multiple applications may be running on each of the processors 202. According to an aspect of the present disclosure, when the updater 110 ascertains that the BIOS firmware is to be updated, a new processor thread may be created for writing the firmware update to the secondary portion 104-3 of the secondary non-volatile memory 104-2. The new thread may be created at any of the processors 202. Simultaneously, the other application threads may continue to perform the tasks without being interrupted by the update process. Upon writing the firmware update to the secondary non-volatile memory 104-2, the firmware manager 112 may determine if a warm reboot is to be performed”;
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Bulusu into teachings of Hobson , Bandakka and Venkatachalam to perform a multistage firmware update to minimize downtime during a firmware update and to maintain the state of virtual machines. the firmware update does not shut the entire system down, and the operations of the running applications are not interrupted. [Bulusu 0042].
As per claim 10, Hobson discloses a non-transitory computer-readable medium storing instructions, which, when executed by a processor of an electronic device:
[0028] Software component described herein, such as secure BIOS update handier 250, normal-mode secure BIOS update code 270, and Power on code 210, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device. Such instruction execution systems include any computer-based system, processor-containing system, or other system that can fetch and execute the instructions from the instruction execution system “;
causes the processor to: during an operation of a central processing unit(CPU), receive a Basic Input/Output System (BIOS) update image for the electronic device:
[0016] “In some embodiments, memory unprotect register 350 is not a separate register, but is implemented as a single bit which is part of an SMI control register (not shown). SMI logic 190 may contain other registers such that logic 340 also generates SMI 180 in response to reads and/or writes to these locations. In some embodiments of system 100, SMI handler 240 reads an SMI status register (not shown) which indicates what particular event caused SMI 180 to be generated.”;
[0024] Normal-mode secure BIOS update code 270 begins with block 510, which loads a buffer with the image of the update for BIOS 160. The image buffer is accessible to both normal-mode code 270 and secure BIOS update handler 250. In some embodiments, this image contains the entire BIOS 160. In other embodiments, this image contains only a portion of BIOS 160. The name and/or location of the image file may be specified by a user, or may be predetermined. Processing continues at block 520, where normal-mode code 270 triggers a system management interrupt (SMI) by writing to memory unprotect register 350.
verify a signature of the BIOS update image:
[0025]“Processing then continues at block 530, where secure BIOS update handler 250 verifies that the code that wrote to memory unprotect register 350 is trustworthy. Various techniques can be used to determine trustworthiness. A technique that provides some level of security involves handler 250 looking for a particular signature written to a register location within SMI logic 190”;
responsive to verification of the BIOS update image, provide a portion of the BIOS update image to a controller that programs the portion of the BIOS update image to a BIOS component of the electronic device:
[0026]”However, if handler 250 determines that the request code-is trustworthy, the handler prepares to update BIOS 160 by disabling memory protect signal 170. To do so, handier 250 retrieves (block 540) retrieves the value previously written by power on code 210 to register X (320) and stored in a shared location (e.g., SMM RAM 230). At block 550, the retrieved value is written to register Y (330). The presence of the same value in register X (320) and register Y (330) causes SMI logic 190 to deassert memory protect signal 170, thus allowing writes to BIOS 160”;
But not explicitly:
without interrupting the operation of the CPU,
wherein the BIOS update image is received in a plurality of portions;
receive an interrupt from the controller; responsive to receiving the interrupt from the controller, read the status of a BIOS update corresponding to the BIOS update image;
and responsive to receiving the interrupt from the controller, provide a second portion of the plurality of portions of the BIOS update image to the controller responsive to the portion of the BIOS update image not being a last portion of the BIOS update image.
Venkatachalam discloses:
wherein the BIOS update image is received in a plurality of portions;
[0049] At block 702, the memory update may be divided into blocks. At block 704, a respective hash corresponding to each of the blocks may be created”;
receive an interrupt from the controller; and responsive to receiving the interrupt from the controller, provide a second portion of the plurality of portions of the BIOS update image to the controller responsive to the portion of the BIOS update image not being a last portion of the BIOS update image:
[0053] “At block 712, a first block may be sent to the target device responsive to the confirmation. At block 714, responsive to a second confirmation verifying that the first block was confirmed by the target device, execution may continue by looping to block 712 and a second block may be sent to the target. Receipt of the second confirmation indicates the target was able to confirm the first block using the respective hash corresponding to the first block that was included in the header 400. This process may be followed until all data blocks are sent, at which time, the `no` branch from block 714 may be followed to block 716 and the download process ended”.
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Venkatachalam into teachings of Hobson for securely downloading an update such as basic input/output system (BIOS) update and a firmware image of a security module, to a constrained memory of the secure module of an electronic device. Because the security module may have limited memory, a memory update process is used that allows individual blocks to be separately downloaded and verified. Verification data is sent in a header block prior to sending the individual data blocks. an update metadata field may include a sequence number or update version number so that data blocks from other updates are distinguishable from data blocks of the current update and a block number so blocks that arrive out of sequence can be correctly stored.[ Venkatachalam 0040].
But not explicitly:
without interrupting the operation of the CPU;
responsive to receiving the interrupt from the controller, read the status of a BIOS update corresponding to the BIOS update image;
Busulu discloses:
without interrupting the operation of the CPU store update.
[0039] “As described earlier, multiple applications may be running on each of the processors 202. According to an aspect of the present disclosure, when the updater 110 ascertains that the BIOS firmware is to be updated, a new processor thread may be created for writing the firmware update to the secondary portion 104-3 of the secondary non-volatile memory 104-2. The new thread may be created at any of the processors 202. Simultaneously, the other application threads may continue to perform the tasks without being interrupted by the update process. Upon writing the firmware update to the secondary non-volatile memory 104-2, the firmware manager 112 may determine if a warm reboot is to be performed”;
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Bulusu into teachings of Hobson and Venkatachalam to perform a multistage firmware update to minimize downtime during a firmware update and to maintain the state of virtual machines. the firmware update does not shut the entire system down, and the operations of the running applications are not interrupted. [Bulusu 0042].
But not explicitly:
receive an interrupt from the controller; responsive to receiving the interrupt from the controller, read the status of a BIOS update corresponding to the BIOS update image;
Bandakka discloses:
receive an interrupt from the controller; responsive to receiving the interrupt from the controller, read the status of a BIOS update corresponding to the BIOS update image;
[0084]“Finally, the method provides a process for providing progress updates during the updating process, by sending to the RMS messages indicating the start and end of each update command execution, and by calculating the percentage progress of completion of updates during execution and sending percentage progress status information to the RMS at regular intervals.”;
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Bandakka into teachings of Hobson Bulusu and Venkatachalam to improve the reliability of a firmware update process, the integrity of a firmware installation package on a target client device can be checked prior to beginning the installation of the package on the client device. Furthermore, to avoid receiving update status at the end of the update, the user is notified by a progress of the update in real-time during the update procedure, which component update is executing or what percentage of the update is completed [Bandakka 0022].
As per claim 11, the rejection of claim 10 is incorporated and furthermore Hubson discloses:
wherein the instructions cause the processor to provide the portion of the BIOS update image to the controller by writing the portion of the BIOS update image to a shared memory accessible to both the processor and the controller:
[0026]“However,if handler 250 determines that the request code-is trustworthy, the handler prepares to update BIOS 160 by disabling memory protect signal 170. To do so, handier 250 retrieves (block 540) retrieves the value previously written by power on code 210 to register X (320) and stored in a shared location (e.g., SMM RAM 230). At block 550, the retrieved value is written to register Y (330). The presence of the same value in register X (320) and register Y (330) causes SMI logic 190 to deassert memory protect signal 170, thus allowing writes to BIOS 160”;
As per claim 12, the rejection of claim 11 is incorporated and furthermore Hobson does not explicitly disclose:
wherein the BIOS update image includes multiple portions, including the portion of the BIOS update image, and the instructions cause the processor to provide write one of the multiple portions to the shared memory at a time;
Venkatachalam discloses:
wherein the BIOS update image includes multiple portions, including the portion of the BIOS update image
[0049] At block 702, the memory update may be divided into blocks. At block 704, a respective hash corresponding to each of the blocks may be created”;
and the instructions cause the processor to provide write one of the multiple portions to the shared memory at a time:
[0053] “At block 712, a first block may be sent to the target device responsive to the confirmation. At block 714, responsive to a second confirmation verifying that the first block was confirmed by the target device, execution may continue by looping to block 712 and a second block may be sent to the target. Receipt of the second confirmation indicates the target was able to confirm the first block using the respective hash corresponding to the first block that was included in the header 400. This process may be followed until all data blocks are sent, at which time, the `no` branch from block 714 may be followed to block 716 and the download process ended”.
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Venkatachalam into teachings of Hobson, Bandakka and Bulusu for securely downloading an update such as basic input/output system (BIOS) update and a firmware image of a security module, to a constrained memory of the secure module of an electronic device. Because the security module may have limited memory, a memory update process is used that allows individual blocks to be separately downloaded and verified. Verification data is sent in a header block prior to sending the individual data blocks. an update metadata field may include a sequence number or update version number so that data blocks from other updates are distinguishable from data blocks of the current update and a block number so blocks that arrive out of sequence can be correctly stored.[Venkatachalam 0040].
As per claim 13, the rejection of claim 11 is incorporated and furthermore Hobson discloses:
wherein the interrupt indicates successful programming by the controller of the portion of the BIOS update image to the BIOS component of the electronic device:
[0026]“Next, at block 550, code from the image prepared by normal-mode code 270 is written to BIOS 160, using techniques known to a person of ordinary skill in the art. When writes to BIOS 160 are finished, block 570 locks or protects BIOS 160 again by writing a different value to register Y (330), causing SMI logic 190 to assert memory protect signal 170 once again. Processing by secure BIOS update handler 250 is then complete, the processor exits out of SMM mode, and control returns to normal-mode secure BIOS update code 270. Code 270 optionally performs some clean-up or post-processing (not shown), and processing is complete.”;
As per claim 14, the rejection of claim 10 is incorporated and furthermore Hobson does not explicitly disclose:
wherein the processor is not interrupted from performing operations unrelated to the BIOS update image while the controller performs the programming of the portion of the BIOS image;
Bulusu discloses:
wherein the processor is not interrupted from performing operations unrelated to the BIOS update image while the controller performs the programming of the portion of the BIOS image;
[0039] “As described earlier, multiple applications may be running on each of the processors 202. According to an aspect of the present disclosure, when the updater 110 ascertains that the BIOS firmware is to be updated, a new processor thread may be created for writing the firmware update to the secondary portion 104-3 of the secondary non-volatile memory 104-2. The new thread may be created at any of the processors 202. Simultaneously, the other application threads may continue to perform the tasks without being interrupted by the update process. Upon writing the firmware update to the secondary non-volatile memory 104-2, the firmware manager 112 may determine if a warm reboot is to be performed”;
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Bulusu into teachings of Hobson, Bandakka and Venkatachalam to perform a multistage firmware update to minimize downtime during a firmware update and to maintain the state of virtual machines. the firmware update does not shut the entire system down, and the operations of the running applications are not interrupted. [Bulusu 0042].
As per claim 15, the rejection of claim 10 is incorporated and furthermore Hobson does not explicitly disclose:
wherein the BIOS update image is a BIOS update for the processor, and wherein the instructions when executed cause the processor to perform processing unrelated to the processor update image while the controller programs the portion of the BIOS update image.
Bulusu discloses:
wherein the BIOS update image is a BIOS update for the processor, and wherein the instructions when executed cause the processor to perform processing unrelated to the processor update image while the controller programs the portion of the BIOS update image.
[0039] “As described earlier, multiple applications may be running on each of the processors 202. According to an aspect of the present disclosure, when the updater 110 ascertains that the BIOS firmware is to be updated, a new processor thread may be created for writing the firmware update to the secondary portion 104-3 of the secondary non-volatile memory 104-2. The new thread may be created at any of the processors 202. Simultaneously, the other application threads may continue to perform the tasks without being interrupted by the update process. Upon writing the firmware update to the secondary non-volatile memory 104-2, the firmware manager 112 may determine if a warm reboot is to be performed”;
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Bulusu into teachings of Hobson, Bandakka and Venkatachalam to perform a multistage firmware update to minimize downtime during a firmware update and to maintain the state of virtual machines. the firmware update does not shut the entire system down, and the operations of the running applications are not interrupted. [Bulusu 0042].
As per claim 16, the rejection of claim 1 is incorporated and furthermore Hobson does not explicitly disclose:
an indicator configured to display at least one of a progress bar, the current percentage, or a graphical user interface element corresponding to the status.
Bandakka discloses:
an indicator configured to display at least one of a progress bar, the current percentage, or a graphical user interface element corresponding to the status.
[0026] “Finally, the methods and systems can provide a user with the ability to see an update status related to individual component updates, and including a percentage progress of the firmware update process, when the firmware update process is scheduled using a remote management software”.
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Bandakka into teachings of Hobson Bulusu and Venkatachalam to improve the reliability of a firmware update process, the integrity of a firmware installation package on a target client device can be checked prior to beginning the installation of the package on the client device. Furthermore, to avoid receiving update status at the end of the update, the user is notified by a progress of the update in real-time during the update procedure, which component update is executing or what percentage of the update is completed [Bandakka 0022].
As per claim 17, the rejection of claim 5 is incorporated and furthermore Hobson discloses:
wherein the register is stored in a non-volatile memory of the controller.
[0016] “In addition to registers X (320) and Y (330), SMS logic 190 also includes logic 340 for generating an interrupt, which is electrically coupled to processor 110”;
[0027] SMI logic 190 can be implemented in hardware, including, but not limited to, a programmable logic device (PLD), programmable gate stray (PGA), field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a system on chip (SoC), and a system in package (SIP).
As per claim 18, the rejection of claim 10 is incorporated and furthermore Hobson does not explicitly disclose:
wherein the status of the BIOS update is read upon an expiration of a timer.
Bandakka discloses:
wherein the status of the BIOS update is read upon an expiration of a timer.
[0026] “The firmware update process can further send the percentage completion of the firmware update process when the upgrade process takes significant time. For example, in the case of updating an O/S which may take from 4 minutes to 40 minutes or more to complete, the firmware update process can send percentage completion information for every 25% of progress.
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Bandakka into teachings of Hobson Bulusu and Venkatachalam to improve the reliability of a firmware update process, the integrity of a firmware installation package on a target client device can be checked prior to beginning the installation of the package on the client device. Furthermore, to avoid receiving update status at the end of the update, the user is notified by a progress of the update in real-time during the update procedure, which component update is executing or what percentage of the update is completed [Bandakka 0022].
As per claim 19, the rejection of claim 1 is incorporated and furthermore Hobson discloses:
wherein the CPU is to: responsive to receiving an interrupt from the embedded controller, read the value indicating the status of the programming from the register.
[0026]” The presence of the same value in register X (320) and register Y (330) causes SMI logic 190 to deassert memory protect signal 170, thus allowing writes to BIOS 160. Next, at block 550, code from the image prepared by normal-mode code 270 is written to BIOS 160, using techniques known to a person of ordinary skill in the art. When writes to BIOS 160 are finished, block 570 locks or protects BIOS 160 again by writing a different value to register Y (330),”;
Examiner interpretation:
Also, Bandakka read the status of the update [0084]: Finally, the method provides a process for providing progress updates during the updating process, by sending to the RMS messages indicating the start and end of each update command execution, and by calculating the percentage progress of completion of updates during execution and sending percentage progress status information to the RMS at regular intervals.
As per claim 20, the rejection of claim 5 is incorporated and furthermore Hobson discloses:
wherein the interrupt further causes the CPU to read the value indicating the status of the programming from the register.
[0026]” The presence of the same value in register X (320) and register Y (330) causes SMI logic 190 to deassert memory protect signal 170, thus allowing writes to BIOS 160. Next, at block 550, code from the image prepared by normal-mode code 270 is written to BIOS 160, using techniques known to a person of ordinary skill in the art. When writes to BIOS 160 are finished, block 570 locks or protects BIOS 160 again by writing a different value to register Y (330),”;
Examiner interpretation:
Also, Bandakka read the status of the update [0084]: Finally, the method provides a process for providing progress updates during the updating process, by sending to the RMS messages indicating the start and end of each update command execution, and by calculating the percentage progress of completion of updates during execution and sending percentage progress status information to the RMS at regular intervals.
Claims 2 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Hobson et al US20100077199A1 in view of Venkatachalam et al US20090064125A1 and Bulusu et al US20190179628A1, Bandakka et al US20130125107A1.
and Desselle et al 20070169076A1.
As per claim 2, the rejection of claim 1 is incorporated and furthermore Hobson does not explicitly disclose:
wherein the BIOS update image is in multiple portions, each 4 kilobytes in size or smaller.
Desselle discloses:
wherein the BIOS update image is in multiple portions, each 4 kilobytes in size or smaller.
[0023] “The WMI function calls 122 correspond to an ACPI method that buffers data received via the WMI/WBEM interface 114 into the memory space 110. The BIOS image update 150 is therefore transferred from the updating computer 140 to the memory space 110 through the WMI/WBEM interface 114. As an example, if the BIOS image update 150 comprises a 1 megabyte (MB) image, the image may be buffered into the memory space 110 by transferring 4 Kilobyte (KB) blocks of data at a time. As previously described, the ACPI method also validates the blocks of data and transmits a code (that acknowledges a successful data transfer or an unsuccessful data transfer) to the WMI/WBEM interface 114.”;
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Desselle into teachings of Hobson , Venkatachalam, Bandakka and Bulusu to update a computer system's Basic Input/Output System (BIOS). the BIOS is updated using a multi-platform management interface such as a Web-Based Enterprise Management (WBEM) interface without installation of new routines and reconfiguration. This eliminates accessing the memory space for other uses, but allows the BIOS image to be updated without re-booting. [Desselle 0030].
As per claim 7, the rejection of claim 5 is incorporated and furthermore Hobson does not explicitly disclose:
wherein the portion of the BIOS update image has a size of 4 kilobytes or less.
Desselle discloses:
wherein the BIOS update image is in multiple portions, each 4 kilobytes in size or smaller.
[0023] “The WMI function calls 122 correspond to an ACPI method that buffers data received via the WMI/WBEM interface 114 into the memory space 110. The BIOS image update 150 is therefore transferred from the updating computer 140 to the memory space 110 through the WMI/WBEM interface 114. As an example, if the BIOS image update 150 comprises a 1 megabyte (MB) image, the image may be buffered into the memory space 110 by transferring 4 Kilobyte (KB) blocks of data at a time. As previously described, the ACPI method also validates the blocks of data and transmits a code (that acknowledges a successful data transfer or an unsuccessful data transfer) to the WMI/WBEM interface 114.”;
It would have obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to combine the teachings of cited references. One of ordinary skill in the art before the effective filling date of the claimed invention would have been motivated to incorporate the teachings of Desselle into teachings of Hobson , Venkatachalam, Bandakka and Bulusu to update a computer system's Basic Input/Output System (BIOS). the BIOS is updated using a multi-platform management interface such as a Web-Based Enterprise Management (WBEM) interface without installation of new routines and reconfiguration. This eliminates accessing the memory space for other uses, but allows the BIOS image to be updated without re-booting.[Desselle 0030].
Pertinent arts:
US20210110041A1:
The update progress of a basic input/output system (BIOS) is displayed on a display screen. The BIOS update progress visual is displayed on the display screen of the computer system while updating the first program of instructions.
Conclusion
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/BRAHIM BOURZIK/ Examiner, Art Unit 2191
/WEI Y MUI/ Supervisory Patent Examiner, Art Unit 2191