Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 2/11/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claims 34 and 36 have been considered but are moot. Applicant’s arguments, pg. 13, alleges that the motivation to combine from paragraph 76 of Rubin “is generic and would not animate the skilled artisan to make the specific combination being alleged to ultimately arrive at Applicants claims.” This rejection no longer relies on the Rubin reference.
Applicant's arguments with respect to the rejection of “claims 45 and 45” have been fully considered but they are not persuasive. Applicant alleges that “the generic motivation of having ‘a more economical system’ per Kuze’s col. 1, lines 31-32… bears no relation to the specific elements the combination of which is alleged as obvious.” Examiner respectfully disagrees. In the rejections, Kuze is only relied on for teaching implementing a separate read and write controller, instead of a joint read/write controller as taught by Perets. The motivation of “reducing costs” is clearly directly related to the improvements Kuze is relied on to teach. See Kuze, col. 1, lines 10-31: “A conventional sequence controller has a writing means and a reading means. However, the writing means is not used after a necessary data has been written in. Therefore the sequence controller having both writing means and reading means is very expensive… A sequence controller is divided into a write-only sequence controller and a read-only sequence controller.” Therefore, one of ordinary skill in the art would absolutely be motivated to implement the separate read and write controllers taught by Kuze, as the improvement of reduced cost is clearly directly related to the taught elements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 26, 28-35, 37, 39-41, 43 are rejected under 35 U.S.C. 102a1 as being anticipated by Perets (US Publication No. 20140192857).
Regarding claim 26, Perets teaches:
A method of controlling memory operations,
the method comprising:
identifying a plurality of data sets to store in memory, each data set comprising two or more bits ordered from a most significant bit to a least significant bit; (para. 44: When buffering a set of LLRs computed for a given process, unit 106 divides each LLR into a more significant (MSB) portion and a least significant (LSB) portion.) The most significant bit is, by definition, the leftmost bit; the least significant bit is, by definition, the rightmost bit. Therefore, the LLRs must be ordered from a most significant bit to a least significant bit.
storing in memory a first plurality of bits selected from the bits for the plurality of data sets, wherein the first plurality of bits is selected by selecting one or more successive first bits of each data set, including the most significant bit of each data set, wherein the stored one or more successive first bits of each data set define a stored portion of each data set; (para. 44: When buffering a set of LLRs computed for a given process, unit 106 divides each LLR into a more significant (MSB) portion [first plurality of bits] and a least significant (LSB) portion. Fig. 5, operation 128: Store in HARQ buffer [memory]: MSB portion in process specific regions.)
storing in memory a further plurality of bits selected from the bits for the plurality of data sets, wherein the further plurality of bits is selected by selecting one or more successive further bits of each data set, outside the stored portion and including the most significant bit outside the stored portion of the each data set. (para. 44: When buffering a set of LLRs computed for a given process, unit 106 divides each LLR into a more significant (MSB) portion and a least significant (LSB) portion. Fig. 5, operation 128: Store in HARQ buffer [memory]: LSB portion in common region.) The LSB portion contains all bits not in the MSB portion. Therefore, it must contain the most significant bit outside of the stored MSB portion.
And, stopping when a stopping event is detected, the step of storing a further plurality of bits before completion of the step of storing a further plurality of bits, wherein the stopping event is detected when a specified number of bits of each data stet have been stored, and wherein the specified number of bits is defined by a predefined compression policy table. (para. 49: Unit 106 stores the MSB portions in the appropriate process-specific region, and, if space is available, stores the LSB portions in the common region. See also para. 47: The MSB portion of each LLR (and thus the bit-width of the process-specific regions) comprises a single bit). The stopping event is an indication to stop storing LSB portions, triggered there being no more space available in the common region, which is only detected once a specified number of bits of each data set (# of bits in MSB portions) have been stored. When the stopping event is detected, the step of storing the LSB portions (further plurality of bits) is stopped. Examiner notes that the broadest reasonable interpretation of a “predefined compression policy table” is any data structure that contains predefined information about compression policy, and therefore can be mapped to the bit-width of the process specific regions which is a data structure containing predefined information about the compression policy (how many bits are allocated to the MSB portion of the compressed LLR).
Regarding claim 28, Perets teaches the method of claim 26. Perets further teaches:
wherein the method further comprises:
subsequent to the step of storing a further plurality of bits, updating for each data set the stored portion to comprise the stored one or more successive further bits of each data set; (para. 49: Unit 106 stores the MSB portions in the appropriate process-specific region, and, if space is available, stores the LSB portions in the common region. In one example, the common region comprises “FREE FLAG” indications that indicate to unit 106 whether the respective space in the common region is already used or available.) Once an LSB portion (the further plurality of bits) has been stored, the system is updated to indicate that space in the stored portion is storing the one or more further bits.
repeating the storing a further plurality of bits step and updating step, until a stopping criterion is met, wherein a stopping criterion comprises one or more of:
each of the plurality of data sets being fully stored in memory;
and/or the stopping event being detected.
(para. 49: Unit 106 stores the MSB portions in the appropriate process-specific region, and, if space is available, stores the LSB portions in the common region. In one example, the common region comprises “FREE FLAG” indications that indicate to unit 106 whether the respective space in the common region is already used or available.) This implies that additional bits of LSB portions are repeatedly stored, only stopping once all MSB/LSB portions are stored (all of the data sets being fully stored), or when there is no more available space (which constitutes detecting a stopping event, only detected after the MSB portions are stored).
Regarding claim 29, Perets teaches the method of claim 26. Perets further teaches:
wherein the stopping event is triggered by one or more of:
a stopping parameter being met, the stopping parameter indicating a number of repeat times for repeating the step of storing a further plurality of bits;
an instruction to stop storing the plurality of data sets in memory;
a detection of a load of memory being above a threshold; and/or
a detection of a latency performance of the memory being above a threshold. (para. 49: Unit 106 stores the MSB portions in the appropriate process-specific region, and, if space is available, stores the LSB portions in the common region. In one example, the common region comprises “FREE FLAG” indications that indicate to unit 106 whether the respective space in the common region is already used or available.) When the free flags indicate there is no more available space, it is a detection of load of memory being above a threshold and is effectively instructing unit 106 to stop storing LSB portions in memory.
Regarding claim 30, Perets teaches the method of claim 26. Perets further teaches:
further comprising, upon detection of the stopping event and upon detection that a first data set of the plurality of data set has not been fully stored in memory, storing an indication that the storing of the first data set has been interrupted. (para. 49-51: Unit 106… if space is available, stores the LSB portions in the common region… When the stored LLRs of a given process are needed, buffer control unit 106 checks for overflow in the common region, at a checking operation 132. Typically, unit 106 checks whether the LSB portions of the LLRs are stored in the common region 114 or not.) Not storing the LSB portion of the first data set in the common region is effectively storing an indication that the storing of the first data set has been interrupted.
Regarding claim 31, Perets teaches the method of claim 30. Perets further teaches:
wherein the indication comprises an indication of the number of bits of the first data set that have been stored in memory. (para. 49-51: Unit 106… if space is available, stores the LSB portions in the common region… When the stored LLRs of a given process are needed, buffer control unit 106 checks for overflow in the common region, at a checking operation 132. Typically, unit 106 checks whether the LSB portions of the LLRs are stored in the common region 114 or not.) Not storing the LSB portion of the first data set in the common region is effectively an indication that 0 bits of the LSB portion of the first data set have been stored. (para. 47: The MSB portion of each LLR… comprises a single bit. And para. 44: stores the MSB portions of the LLRs in the process-specific region… the process-specific memory will not overflow.) Because the MSB portion is 1 bit and will always be stored, an indication that 0 bits of the LSB portion was stored, is effectively an indication of the total number of bits of a given data set that were stored (1).
Regarding claim 32, Perets teaches the method of claim 26. Perets further teaches:
further comprising:
measuring a performance of the memory; and setting a stopping parameter based on the measured performance, wherein the stopping event is triggered at least by the stopping parameter being met. (para. 49: Unit 106 stores the MSB portions in the appropriate process-specific region, and, if space is available, stores the LSB portions in the common region.) Unit 106 measures the performance of memory by checking whether there is space available in the common region. In response to the measured performance, it effectively sets a stopping parameter (whether or not the memory is full). A stopping event (not storing more LSB portions), is triggered if the stopping parameter is met (if the memory is full).
Regarding claim 33, Perets teaches the method of claim 26. Perets further teaches:
wherein selecting one or more successive first bits of each data set comprises selecting only the most significant bit of each data set as the one or more successive first bits of each data set. (para. 47: The MSB portion of each LLR… comprises a single bit.)
Regarding claim 34, Perets teaches the method of claim 26. Perets further teaches:
Wherein selecting one or more successive further bits of each data set comprises selecting only the most significant bit outside the stored portion of each data set as one or more successive further bits of each data set. (para. 47: Unit 106 divides the LLRs into MSB and LSB portions having any suitable sizes, in an embodiment… in one example embodiment…. The MSB portion of each LLR… comprises a single bit… the LSB portion of each LLR… comprises four bits.) If the Unit 106 divides the LLRs into MSB and LSB portions having any suitable sizes, it is therefore an obvious alternate embodiment to swap the bit allocation described such that the MSB portion comprises four bits and the LSB portion comprises a single bit, for this would certainly be a “suitable size”.
Regarding claim 35, Perets teaches the method of claim 26. Perets further teaches:
wherein each data set is at least one of
a Log-likelihood ratio "LLR"; (para. 44: the set of LLRs)
associated with a coded bit;
a representation of an expected value of a coded bit.
Regarding claim 37, Perets teaches:
A method of controlling memory operations, the method comprising: identifying a plurality of data sets to read from memory, each data set comprising two or more bits ordered from a most significant bit to a least significant bit; (para. 51: unit 106 retrieves both the MSB portions and the LSB portions of the LLRS from buffer 40.)
reading from memory a first plurality of bits selected from the bits for the plurality of data sets, wherein the first plurality of bits is selected by selecting one or more successive first bits of each data set, including the most significant bit of each data set, wherein the read one or more successive first bits of each data set define a read portion of each data set; (para. 51: unit 106 retrieves… the MSB portions… of the LLRS from buffer 40.)
and reading from memory a further plurality of bits… selected from the bits for the plurality of data sets, wherein the further plurality of bits is selected by selecting one or more successive further bits of each data set, outside the read portion and including the most significant bit outside the read portion of each data set. (para. 51: unit 106 retrieves… the LSB portions of the LLRS from buffer 40.)
stopping, when a stopping event is detected, the step of reading a further plurality of bits before completion of the step of reading a further plurality of bits, wherein the stopping event is detected when a specified number of bits of each data set have been read, and wherein the specified number of bits is defined by a predefined compression policy table. (para. 46: When the LLRs of a given process are to be retrieved, buffer control unit 106 retrieves the MSB portions of the LLRs from the appropriate process-specific region 110, and (if available) retrieves the LSB portions from common region 114. And see para. 47: The MSB portion of each LLR (and thus the bit-width of the process-specific regions) comprises a single bit.) The stopping event is an indication to stop reading LSB portions, triggered by there being overflow in the common region (no available LSB portions), which is only detected once a specified number of bits of each data set (# of bits in MSB portions) have been read. When the stopping event is detected, the step of reading the LSB portions (further plurality of bits) is stopped. Examiner notes that the broadest reasonable interpretation of a “predefined compression policy table” is any data structure that contains predefined information about compression policy, and therefore can be mapped to the bit-width of the process specific regions which is a data structure containing predefined information about the compression policy (how many bits are allocated to the MSB portion of the compressed LLR).
Regarding claim 39, Perets teaches the method of claim 37. Perets further teaches:
wherein the method further comprises: subsequent to the step of reading a further plurality of bits, updating for each data set the read portion to comprise the read one or more successive further bits of each data set;
repeating the reading a further plurality of bits step and updating step, until a stopping criterion is met, wherein a stopping criterion comprises one or more of: each of the plurality of data sets being fully read from memory; and/or the stopping event being detected. (para. 51: If no overflow is found (i.e., if the LSB portions of the LLRs of the given process are found in the common region), unit 106 retrieves both the MSB portions and the LSB portions of the LLRs from the buffer 40, at a full retrieval operation 136. Processing circuitry then decodes the signal using the complete LLRs, including both the MSB and LSB portions.) This implies that the LSB portions are continually read out until each of the plurality of data sets have been fully read from memory or overflow is detected. Each time a LSB portion is read out, the read portion is effectively updated to include the read bits.
Regarding claim 40, Perets teaches the method of claim 37. Perets further teaches:
wherein a stopping event is triggered by one or more of:
a stopping parameter being met, the stopping parameter indicating a number of repeat times for repeating the step of reading a further plurality of bits;
an instruction to stop reading the plurality of data sets in memory; (fig. 5, operation 136: overflow in common region? -> yes -> operation 144: retrieve only MSB portions of LLRs from process-specific region.) The detected overflow is effectively an instruction to stop reading data sets from memory.
a detection of a load of the memory being above a threshold; (fig. 5, operation 136: overflow in common region? -> yes -> operation 144: retrieve only MSB portions of LLRs from process-specific region.) The detected overflow is a detection of a load of the memory being above a threshold.
a detection of a latency performance of the memory being above a threshold;
and/or a determination, based on an indicator, that an earlier step of storing plurality of the data sets had been interrupted and that the first portion of the plurality of data sets stored during the earlier step have all been read.
Claims 41 and 43 correspond to claims 26 and 37, respectively, and are rejected accordingly.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 36 is rejected under 35 U.S.C. 103 as being unpatentable over Perets.
Regarding claim 36 Perets, in view of the general state of the art teaches:
wherein the memory is a Double Data Rate "DDR" Synchronous Dynamic Random-Access Memory "SDRAM". (para. 54: Memory 36 may comprise any Suitable type of memory, e.g., Random Access Memory (RAM).) It is well known in the art that Double Data Rate “DDR” Synchronous Dynamic Random-Access Memory “SDRAM” is a kind of Random Access Memory often used in similar applications to allow for benefits such as effectively doubling the data rate without increasing the clock frequency.
Claims 45-49 are rejected under 35 U.S.C. 103 as being unpatentable over Perets in view of Kuze (US Patent No. 4456967).
Claim 45 corresponds to the combination of claims 41 and 43, and is rejected accordingly, but for one difference: the storing/writing steps are performed by a first controller, and the reading steps are performed by a second controller.
The combination of Perets and Shapiro fails to teach:
… a first controller configured to… [write]
… a second controller configured to… [read]
In the analogous art of memory operations, Kuze teaches:
… a first controller configured to… [write] … a second controller configured to… [read] (col. 1, lines 10-31: A conventional sequence controller has a writing means and a reading means. However, the writing means is not used after a necessary data has been written in. Therefore the sequence controller having both writing means and reading means is very expensive… A sequence controller is divided into a write-only sequence controller and a read-only sequence controller.)
It would have been obvious to one of ordinary skill in the art, having the teachings of Perets and Kuze before the effective filing date of the claimed invention, to incorporate substituting a read/write memory controller into a read controller and a write controller (taught by Kuze) into Perets’ method for storing LLRs, to allow for benefits such as a more economical system (Kuze, col. 1, lines 31-32.)
Regarding claim 46, the combination of Perets and Kuze teaches the controller system of claim 45. Kuze further teaches:
Wherein the first controller is a reading controller, and wherein the second controller is a writing controller. (col. 1, lines 10-31: A conventional sequence controller has a writing means and a reading means. However, the writing means is not used after a necessary data has been written in. Therefore the sequence controller having both writing means and reading means is very expensive… A sequence controller is divided into a write-only sequence controller and a read-only sequence controller.)
It would have been obvious to one of ordinary skill in the art, having the teachings of Perets and Kuze before the effective filing date of the claimed invention, to incorporate substituting a read/write memory controller into a read controller and a write controller (taught by Kuze) into Perets’ method for storing LLR’s, to allow for benefits such as a more economical system (Kuze, col. 1, lines 31-32.)
Regarding claim 47, the combination of Perets and Kuze teaches the controller system of claim 45. Perets further teaches:
Wherein the first stopping event is different from the second stopping event (para. 46: When the LLRs of a certain process are to be retrieved, buffer control unit 106 retrieves the MSB portions of the LLRs from the appropriate process-specific region 110 and (if available) retrieves the LSB portions of the LLRs from common region 114. And see para. 49: Unit 106 stores the MSB portions in the appropriate process-specific region, and, if space is available, stores the LSB portions in the common region.) The first stopping event is triggered when storing LLRs, and the second stopping event is triggered when retrieving LLRs, therefore they are different.
Regarding claim 48, the combination of Perets and Kuze teaches the controller system of claim 45. Perets further teaches:
Wherein the first predefined compression policy table is the same as the second predefined compression policy table. (para. 49: Unit 106 stores the MSB portions in the appropriate process-specific region, and, if space is available, stores the LSB portions in the common region. And see para. 46: When the LLRs of a given process are to be retrieved, buffer control unit 106 retrieves the MSB portions of the LLRs from the appropriate process-specific region 110, and (if available) retrieves the LSB portions from common region 114. And see para. 47: The MSB portion of each LLR (and thus the bit-width of the process-specific regions) comprises a single bit)) Stopping events triggered during read and write operations are only detected once the specific number of bits (MSB portion) has been read or written (respectively). Examiner notes that the broadest reasonable interpretation of a “predefined compression policy table” is any data structure that contains predefined information about compression policy, and therefore can be mapped to the bit-width of the process specific regions which is a data structure containing predefined information about the compression policy (how many bits are allocated to the MSB portion of the compressed LLR). The bit-width of the process specific regions does not change from a read cycle to a write cycle, and therefore the first and second compression policy tables are effectively disclosed to be the same.
Regarding claim 49, the combination of Perets and Kuze teaches the controller system of claim 45. Perets further teaches:
Wherein the second plurality of bits is different from the first plurality of bits, (And see para. 49: Unit 106 stores the MSB portions in the appropriate process-specific region, and, if space is available, stores the LSB portions in the common region.) It is clear that the MSB portions to be written are different from the LSB portions to be written.
And wherein the fourth plurality of bits is different from the third plurality of bits. (para. 46: When the LLRs of a certain process are to be retrieved, buffer control unit 106 retrieves the MSB portions of the LLRs from the appropriate process-specific region 110 and (if available) retrieves the LSB portions of the LLRs from common region 114.) It is clear that the MSB portions to be read are different from the LSB portions to be read.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK K BARNETT whose telephone number is (571)270-0431. The examiner can normally be reached M-Th 8-5, F 8-4 EST.
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/JACK KENSINGTON BARNETT/Examiner, Art Unit 2111
/MARK D FEATHERSTONE/Supervisory Patent Examiner, Art Unit 2111
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