DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO AMENDMENT
Claim rejections based on prior arts
Applicant’s arguments filed on 07/20/2026 with respect to claims 1-5, 7-10, 12-14, 17, 20-22, 26 and 28-29 have been fully considered but are moot in view of newly interpretation of the cited refence based on most recent amendment.
Note, even though prosecution is now closed, to help expedite any further potential prosecution of this application, Applicant is encouraged to contact the Examiner to discuss the invention, and a potential allowance.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
1. Claims 1, 3-5, 7-10, 12, 13, 17, 20-22, 26 and 28-29 are rejected under 35 U.S.C. 103(a) as being unpatentable over Bjorling et al. (US pub. # 2022/0050599), hereinafter, “Bjorling”, in view of Alameldeen et al. (US pub. # 2018/0095674), hereinafter, “Alameldeen”.
2. As per claims 1, 12 and 13, Bjorling discloses a data processing system (storage system 100 of fig. 1) comprising: a communications bus (communication path from host device 104 to memories 110, 112 and 116) over which bus transactions to access memory (memory 110, 112 and 116, combined) are performed (see paragraphs 0060 and 0072); a processing unit (see paragraph 0030, which teaches host device 104 comprising a computer, which comprises a CPU) configured to initiate bus transactions over the communications bus (see paragraphs 0060, 0072 and figs. 8, 9); and a codec (controller 108) configured to compress and decompress data (see paragraphs 0060 and 0072); wherein the processing unit is configured to initiate over the communications bus, direct bus transactions that comprise the processing unit accessing the memory via the communications bus (note, this limitation is being interpreted to recite the processing unit is accessing the memory via the communications bus; therefore, see paragraph 0068, which discloses “FIG. 8 illustrates a method 800 for writing data to a location in the non-volatile memory, according to one embodiment. At block 802, the controller, such as the controller 108 of FIG. 1, of the storage device, such as the data storage device 106 of FIG. 1, receives one or more commands from the host, such as the host 104 of FIG. 1, to write data to a first zone of a plurality of zones. At block 804, the compression engine, such as the compression engine 120 of FIG. 1, utilizes the maximum compression ratio to compress the data associated with the write command from a first chunk including a first number of logical blocks or grains to a first compressed chunk including a second number of logical blocks of a plurality of grains. The first number of logical blocks or grains may be equal to or greater than the second number of logical blocks or grains”); wherein the processing unit is configured to initiate over the communications bus, codec bus transactions that comprise the codec accessing the memory via the communications bus to read or write compressed data in the memory (see paragraphs 0068 and 0072 teaching reading compressed data from memory via controller 108), or to read or write metadata associated with compressed data in the memory; wherein the processing unit initiating a codec bus transaction comprises the processing unit issuing over the communications bus, a bus transaction request (a write command, as discloses in paragraph 0056) including a predetermined signal [a number of logical blocks (NLB), grain, as disclose in paragraphs 0056 and 0059] that indicates (note, ‘indicates’ is not clarify; for example, how the ‘indication’ is expressed) that the codec is to access the memory [see paragraph 0056, which discloses “FIG. 3A illustrates a conventional compression solution, according to one embodiment. The host, such as the host device 104 of FIG. 1, sends a write command to the storage device 302, such as the data storage device 106 of FIG. 1, to write a number of logical blocks (NLB) at a starting LBA. The write command may require a number of buffers, such as about 4 data buffers, to store the data associated with the write command. The NVMe frontend module 304 of the storage device 302 receives the NLB and the starting LBA location. After processing the write command, the storage device 302 moves the data and the buffers associated with the write command to the hardware (HW) compression module 306, where the NLB is compressed. The compressed data is stored in the media 308, such as the NVM 110 of FIG. 1, and the resulting LBA of the compressed data stored in the media 308 is recorded at a flash translation layer (FTL) mapping table 310. After both the compressed data is written to the media 308 and the location of the compressed data is recorded in the FTL mapping table 310, the storage device 302 returns a command completion response to the host indicating that the write command has been completed”]; wherein the codec is configured to, in response to receiving a bus transaction request over the communications bus, determine whether to access the memory based on whether the bus transaction request includes the predetermined signal (see paragraphs 0066 and 0072, which disclose not compressing a chunk of data that doesn’t have an associated grain, NLB), and when it is determined to access the memory, access the memory via the communications bus to read or write compressed data in the memory, or to read or write metadata associated with compressed data in the memory (see paragraph 0070, which discloses “At block 806, the compressed data is written to a first zone. In one embodiment, a header may be written before the compressed data. The header may include pointers that point to the grains that correspond to the start of each compressed chunk. Each grain written to the first zone corresponds with a media LBA, where the media LBA represents the location of the grain in the media. At block 808, the information concerning the compressed data, such as the location of each grain, is reported to the host”), or to read or write metadata associated with compressed data in the memory.
Bjorling fails to expressly disclose ’to read or write uncompressed data in the memory’.
Alameldeen discloses to read or write uncompressed data in the memory (with near memory 110a and far memory 110b, combined, being equated to claim ‘memory’, see paragraph 0040).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Alameldeen’s teaching of an inter-memory transfer interface having selective data compression/decompression to select from multiple candidate processes, a compression/decompression process to compress a region of data from a near memory before transmitting the compressed data to the far memory, into Bjorling’s teaching of a storage device with a controller that includes a compression engine, for the ability/benefit of having a read operation from a far memory to a near memory that’s transferred in relatively small units of data such as a sector of data, for example, to reduce latency of such read operations.
3. As per claim 3, the combination of Bjorling and Alameldeen discloses “The system of claim 1” [See rejection to claim 1 above], wherein compressed data is stored in the memory in one or more memory space regions, with each memory space region being divided into one or more memory space sub-regions; wherein the processing unit is configured to issue over the communications bus, a signal that indicates a memory address for one of the memory space regions and an index indicating one of the memory space sub-regions of that memory space region; and the codec is configured to, in response to receiving the signal that indicates a memory address and an index, determine a memory address for the memory space sub-region indicated by the index based on the memory address and index indicated by the signal, and access the determined memory address (see paragraph 0067 of Bjorling).
4. As per claim 4, Bjorling discloses wherein the processing unit is configured to issue over the communications bus, a signal that indicates a memory address of a header associated with compressed data; and the codec is configured to: in response to receiving a memory address indicating signal that indicates a memory address of a header associated with compressed data to be read, determine a memory address for the compressed data based on the indicated memory address of the header, and memory address offset information in the header that indicates a memory address offset relative to the memory address of the header for the compressed data; and in response to receiving a memory address indicating signal that indicates a memory address of a header associated with compressed data to be written, write memory address offset information in the header that indicates a memory address offset relative to the memory address of the header for the compressed data (see paragraph 0066).
5. As per claim 5, Bjorling discloses wherein the processing unit is configured to initiate over the communications bus, a codec bus transaction that comprises; the codec compressing data provided by the processing unit to produce compressed data; and/or the codec decompressing compressed data to produce decompressed data, and providing the decompressed data to the processing unit (see paragraph 0072).
6. As per claim 7, Bjorling discloses wherein the processing unit is configured to initiate over the communications bus, a codec bus transaction that comprises the codec: receiving, from the processing unit via the communications bus, information indicative of encoding parameters and/or properties to be used when compressing or decompressing data; and compressing or decompressing data in accordance with the encoding parameters and/or properties indicated by the information (see paragraph 0067).
7. As per claim 8, Bjorling discloses wherein the codec comprises an encoder and decoder circuit configured to compress and decompress data, wherein the encoder and decoder circuit is configurable over the communications bus; and the processing unit is configured to issue over the communications bus, information indicative of encoding parameters and/or properties to be used by the encoder and decoder circuit when compressing or decompressing data; and the codec is configured to, in response to receiving the information over the communications bus, configure the encoder and decoder circuit to compress or decompress data in accordance with the encoding parameters and/or properties indicated by the information (see paragraphs 0060 and 0072).
8. As per claims 9 and 21, Bjorling discloses wherein the processing unit is configured to initiate over the communications bus, a codec bus transaction that comprises the codec reading metadata associated with compressed data from the memory without reading the compressed data, and returning the read metadata to the processing unit (see paragraphs 0070 and 0075).
9. As per claim 10, Bjorling discloses wherein the processing unit is configured to initiate over the communications bus, a codec bus transaction that comprises the codec receiving a signature (NLB, as discloses in paragraph 0056) representative of associated compressed data from, or providing a signature representative of associated compressed data to, the processing unit via the communications bus (see paragraph 0056).
10. As per claim 17, Bjorling discloses wherein the processing unit initiating the bus transaction comprises the processing unit initiating a bus transaction in which the codec is to compress data provided by the processing unit to produce compressed data; and the method comprises: the codec, in response to the processing unit initiating the bus transaction: compressing data provided by the processing unit to produce compressed data; or wherein the processing unit initiating the bus transaction comprises the processing unit initiating a bus transaction in which the codec is to decompress compressed data to produce decompressed data, and provide the decompressed data to the processing unit; and the method comprises: the codec, in response to the processing unit initiating the bus transaction: decompressing compressed data to produce decompressed data; and providing the decompressed data to the processing unit (see paragraph 0072).
11. As per claim 20, Bjorling discloses wherein the codec comprises an encoder and decoder circuit configured to compress and decompress data, wherein the encoder and decoder circuit is configurable over the communications bus, and the method comprises: the processing unit issuing over the communications bus, information indicative of encoding parameters and/or properties to be used by the encoder and decoder circuit when compressing or decompressing data; and the codec, in response to receiving the information over the communications bus, configuring the encoder and decoder circuit to compress or decompress data in accordance with the encoding parameters and/or properties indicated by the information (see paragraphs 0067 and 0072).
12. As per claim 22, Bjorling discloses wherein the processing unit initiating the codec bus transaction comprises the processing unit initiating a bus codec transaction in which the codec is to receive a signature representative of associated compressed data from, or provide a signature representative of associated compressed data to, the processing unit via the communications bus; and the method comprises: the codec, in response to the processing unit initiating the codec bus transaction: receiving a signature representative of associated compressed data from, or providing a signature representative of associated compressed data to, the processing unit via the communications bus (see paragraph 0056).
13. As per claim 26, Bjorling discloses wherein the processing unit is a central processing unit (CPU), a graphics processing unit (GPU), a video processor, a sound processor, an image signal processor (ISP), a digital signal processor (DSP), a neutral network processor or a display controller (see paragraph 0030, which teaches host device 104 comprising a computer, which comprises a CPU).
14. As per claim 28, Alameldeen discloses wherein the codec is configured to present an uncompressed view of compressed data in the memory to the processing unit; and wherein the processing unit initiating a codec bus transaction comprises the processing unit accessing an uncompressed view of compressed data in the memory presented by the codec (see paragraph 0040).
15. As per claim 29, Bjorling discloses wherein the processing unit initiating a direct bus transaction comprises the processing unit issuing over the communications bus, a bus transaction request not including the predetermined signal that indicates that the codec is to access the memory (see paragraphs 0066 and 0072, which disclose not compressing a chunk of data that doesn’t have an associated grain, NLB).
16. Claims 2 and 14 are rejected under 35 U.S.C. 103(a) as being unpatentable over Bjorling et al. (US pub. # 2022/0050599), hereinafter, “Bjorling”, in view of Alameldeen et al. (US pub. # 2018/0095674), hereinafter, “Alameldeen” and further in view of Itoh et al. (US pub. # 2018/0267746), hereinafter, “Itoh”.
17. As per claims 2 and 14, the combination of Bjorling and Alameldeen discloses “The system of claim 1” [See rejection to claim 1 above], but fails to expressly discloses wherein the communications bus comprises a set of channels including a control channel for conveying control data and an address channel for conveying address data, and the processing unit is configured to issue the predetermined signal that indicates that the codec is to access the memory on the control channel or on the address channel.
Itoh discloses wherein the communications bus comprises a set of channels including a control channel for conveying control data and an address channel for conveying address data, and the processing unit is configured to issue the predetermined signal that indicates that the codec is to access the memory on the control channel or on the address channel (see paragraph 0038).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Itoh’s teaching of a readout control device including a memory and one or more processors configured to function as a converter, a reader and an analyzer, into Alameldeen’s teaching of an inter-memory transfer interface having selective data compression/decompression to select from multiple candidate processes, a compression/decompression process to compress a region of data from a near memory before transmitting the compressed data to the far memory and Bjorling’s teaching of a data storage device such a solid state drive that includes a controller that includes a compression/de-compression engine, for the benefit of a reducing a delay time of readout at a time of random access of a memory.
CLOSING COMMENTS
Conclusion
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the application as recommended by M.P.E.P. 707.07(i):
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-5, 7-10, 12-14, 17, 20-22, 26 and 28-29 have received a final action on the merits.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Ernest Unelus whose telephone number is (571) 272-8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00 PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful,
the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone
number: Area Code (571) 270-1023.
The fax phone number for the organization where this application or proceeding
is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Ernest Unelus/
Primary Examiner
Art Unit 2181
Prosecution Insights