DETAILED ACTION
This office action is responsive to application 18/261,615 filed on July 14, 2023. Claims 1-20 are pending in the application and have been examined by the Examiner.
Information Disclosure Statement
The Information Disclosure Statement (IDS) filed on July 14, 2023 was received and has been considered by the Examiner.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 11 recites “the plurality of charge accumulation units”. However, parent claims 1 and 10 only recite a single charge accumulation unit. Therefore, it is unclear what this recitation is referring to. As such, claim 11 is deemed indefinite by the Examiner.
Claims 12 and 13 are indefinite as depending from claim 11 and not remedying the deficiencies of claim 11.
Additionally, claim 13 recites “the first through electrodes connected to the plurality of charge accumulation units”. However, claim 13 and parent claims 1, 10 and 11 do not previously recite first through electrodes connected to the plurality of charge accumulation units. As such, it is unclear what this recitation is referring to. Therefore, claim 13 is deemed indefinite for this additional reason.
In order to overcome the rejection of claims 11 and 12, claim 11 may be amended to instead recite “a plurality of charge accumulation units”, and this is how the Examiner will interpret claim 11 for prior art purposes. In order to overcome the rejection of claim 13, claim 13 may be amended to depend from claim 12 in addition to the amendments described above with respect to claim 11, and this is how the Examiner will interpret claim 13 for prior art purposes.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9, 14-16 and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Endo et al. (US 2012/0267690).
Consider claim 1, Endo et al. teaches:
A solid-state imaging device (see figures 2 and 11) including:
a first substrate (first substrate, 204, figure 2, paragraph 0047) including a photoelectric conversion unit that generates a charge by photoelectrically converting incident light (“n-type charge storage regions 212 constituting the photoelectric conversion elements” paragraph 0050);
a second substrate (second substrate, 208, figure 2, paragraph 0048) bonded to the first substrate (“In the solid-state image pickup device according to the present embodiment, the first chip 201 and the second chip 202 are laminated such that the principal surface 205 of the first substrate 204 and the rear surface 210 of the second substrate 208 face each other.” paragraph 0049) and including at least a part of a pixel circuit (figure 11) that generates a voltage signal based on the charge generated at the photoelectric conversion unit (“In the second substrate 208, parts constituting the amplifying transistors 306 in FIG. 11 are arranged.” paragraph 0048); and
first metal wiring (second interconnect layer, 229, figure 2, paragraph 0048) disposed on a side opposite to the first substrate (204) with the second substrate (208) sandwiched between the first substrate (204) and the first metal wiring (229, see figure 2), wherein the pixel circuit includes:
a charge accumulation unit (FD region, 213, figure 2, 305, figure 11) that accumulates a charge generated at the photoelectric conversion unit (see paragraphs 0049 and 0037);
an amplification transistor (amplifying transistor, 306, figure 11) that converts the charge accumulated in the charge accumulation unit (213, 305) into a voltage of a voltage value in accordance with a charge amount of the charge (see paragraphs 0029 and 0049);
a reset transistor (reset transistor, 307, figure 11) that releases the charge accumulated in the charge accumulation unit (213, 305, see paragraph 0029);
a first through electrode (through electrode, 235, figure 2) that penetrates the second substrate (208) from the first metal wiring (229) to be connected to the charge accumulation unit (213, see figure 2, paragraph 0049); and
first wiring that connects a gate electrode of the amplification transistor (“gate electrode 226 of the amplifying transistor” paragraph 0049) with the first through electrode (As shown in figure 2, there is a first wiring (236) that connects the gate electrode (226) of the amplifying transistor to the first metal wiring (229) via a through electrode (not labeled), wherein the first metal wiring (229) is connected to the through electrode (235), so as to connect the FD region (213) to the gate electrode (226) of the amplifying transistor, paragraphs 0051 and 0049. See also figure 11.).
Consider claim 2, and as applied to claim 1 above, Endo et al. further teaches that the first wiring (229) is an extending portion extending from a gate electrode of the amplification transistor (“gate electrode 226 of the amplifying transistor” paragraph 0049, see figure 2).
Consider claim 3, and as applied to claim 1 above, Endo et al. further teaches that the pixel circuit further includes a second through electrode connected to a gate electrode (226) of the amplification transistor (“gate electrode 226 of the amplifying transistor” paragraph 0049), and the first wiring (236) connects the first through electrode (235) with a second through electrode (As shown in figure 2, there is a first wiring (236) that connects the gate electrode (226) of the amplifying transistor to the first metal wiring (229) via a second through electrode (not labeled), wherein the first metal wiring (229) is connected to the through electrode (235), so as to connect the FD region (213) to the gate electrode (226) of the amplifying transistor, paragraphs 0051 and 0049.).
Consider claim 4, and as applied to claim 3 above, Endo et al. further teaches that the amplification transistor (306) is disposed on the first substrate (“In the second substrate 208, parts constituting the amplifying transistors 306 in FIG. 11 are arranged.” paragraph 0048. The second substrate (208) is disposed on the first substrate (204), and as such, the amplifying transistor (306) is disposed on the first substrate (204), see figure 2.).
Consider claim 5, and as applied to claim 1 above, Endo et al. further teaches that the first wiring includes a part of the first metal wiring (The first metal wiring may be interpreted to include the second interconnect layer (229) and the first wiring (236), see figure 2.).
Consider claim 6, and as applied to claim 1 above, Endo et al. further teaches that the pixel circuit further includes second wiring that connects a source of the reset transistor (307) with the charge accumulation unit (305, see figure 11).
Consider claim 7, and as applied to claim 6 above, Endo et al. further teaches that the second wiring includes a part of the first metal wiring (The first metal wiring (229) is connected to the charge accumulation unit (FD region, 213, figure 2, 305, figure 11), as is the second metal wiring (see figure 11). Therefore, the Examiner interprets the second wiring to include part of the first metal wiring.).
Consider claim 8, and as applied to claim 6 above, Endo et al. further teaches that the reset transistor (307) is disposed on the second substrate (“In the second chip 309, the amplifying transistors 306 and the reset transistors 307 of the pixel portion 301 and the peripheral circuit portion 302 are arranged.” paragraph 0031), and the second wiring is a second diffusion region continuous with a first diffusion region functioning as the source of the reset transistor (see figure 11).
Consider claim 9, and as applied to claim 6 above, Endo et al. further teaches that the amplification transistor (306) is disposed on the first substrate (“In the second substrate 208, parts constituting the amplifying transistors 306 in FIG. 11 are arranged.” paragraph 0048. The second substrate (208) is disposed on the first substrate (204), and as such, the amplifying transistor (306) is disposed on the first substrate (204), see figure 2.),
the pixel circuit further includes a second through electrode connected to a gate electrode (226) of the amplification transistor (“gate electrode 226 of the amplifying transistor” paragraph 0049), and the second wiring includes the second through electrode and at least a part of the first wiring (As shown in figure 2, there is a first wiring (236) that connects the gate electrode (226) of the amplifying transistor to the first metal wiring (229) via a second through electrode (not labeled), wherein the first metal wiring (229) is connected to the through electrode (235), so as to connect the FD region (213) to the gate electrode (226) of the amplifying transistor, paragraphs 0051 and 0049. Therefore, the Examiner interprets the second wiring to include the second through electrode and at least a part of the first wiring.).
Consider claim 14, Endo et al. teaches:
An electronic device (figure 12) including:
the solid-state imaging device (image pickup device, 4) according to claim 1 (see paragraph 0077, claim 1 rationale); and
a processor (signal processing unit, 7) that processes an image signal output from the solid-state imaging device (“A signal processing unit 7 performs various correction processes on image data output from the image pickup device 4 and compresses the data.” paragraph 0077).
Consider claim 15, Endo et al. teaches:
A solid-state imaging device (see figures 2 and 11) including:
a photoelectric conversion unit that generates a charge by photoelectrically converting incident light (“n-type charge storage regions 212 constituting the photoelectric conversion elements” paragraph 0050); and
a pixel circuit (see figure 11) that generates a voltage signal based on the charge generated at the photoelectric conversion unit (“In the second substrate 208, parts constituting the amplifying transistors 306 in FIG. 11 are arranged.” paragraphs 0048 and 0029), wherein
the photoelectric conversion unit (212) is disposed on a first substrate (first chip, 201, figure 2, paragraph 0050),
at least a part of the pixel circuit is disposed on a second substrate (second chip, 202, paragraph 0050, “In the second substrate 208, parts constituting the amplifying transistors 306 in FIG. 11 are arranged.” paragraph 0048) bonded to the first substrate (“In the solid-state image pickup device according to the present embodiment, the first chip 201 and the second chip 202 are laminated such that the principal surface 205 of the first substrate 204 and the rear surface 210 of the second substrate 208 face each other.” paragraph 0049),
the pixel circuit (see figure 11) includes:
a charge accumulation unit (FD region, 213, figure 2, 305, figure 11) that accumulates a charge generated at the photoelectric conversion unit (see paragraphs 0049 and 0037);
an amplification transistor (amplifying transistor, 306, figure 11) that converts the charge accumulated in the charge accumulation unit (213, 305) into a voltage of a voltage value in accordance with a charge amount of the charge (see paragraphs 0029 and 0049); and
a reset transistor (reset transistor, 307, figure 11) that releases the charge accumulated in the charge accumulation unit (213, 305, see paragraph 0029),
the amplification transistor (amplifying transistor, 306, figure 11) is disposed on the second substrate (second chip, 202, paragraph 0050, “In the second substrate 208, parts constituting the amplifying transistors 306 in FIG. 11 are arranged.” paragraph 0048) bonded to the first substrate (“In the solid-state image pickup device according to the present embodiment, the first chip 201 and the second chip 202 are laminated such that the principal surface 205 of the first substrate 204 and the rear surface 210 of the second substrate 208 face each other.” paragraph 0049), and
the second substrate (202) further includes:
second metal wiring (second interconnect layer, 229, figure 2, paragraph 0048) disposed on a side opposite to the first substrate (201) with the second substrate (202) sandwiched between the first substrate (201) and the second metal wiring (229, see figure 2); and
a shield electrode disposed at at least a part between the second metal wiring (229) and a gate electrode (“gate electrode 226 of the amplifying transistor” paragraph 0049) of the amplification transistor (As shown in figure 2, there is a shield electrode that connects the gate electrode (226) of the amplifying transistor to the first metal wiring (229) which is connected to the through electrode (235), so as to connect the FD region (213) to the gate electrode (226) of the amplifying transistor, paragraph 0049.).
Consider claim 16, and as applied to claim 15 above, Endo et al. further teaches that the second metal wiring (229) is a power supply line to which a power supply voltage is applied (i.e. applied to the gate electrode (226) of the amplification transistor (306, see figures 2 and 11).
Consider claim 18, and as applied to claim 15 above, Endo et al. further teaches that the shield electrode is further disposed at at least a part between the charge accumulation unit (213) and the second metal wiring (229, i.e. in the vertical direction of figure 2, claim 15 rationale).
Consider claim 19, and as applied to claim 15 above, Endo et al. further teaches that the shield electrode is connected to a well (well, 224) of the second substrate (202, see figure 2, paragraph 0051, claim 15 rationale).
Consider claim 20, Endo et al. teaches:
An electronic device (figure 12) including:
the solid-state imaging device (image pickup device, 4) according to claim 15 (see paragraph 0077, claim 15 rationale); and
a processor (signal processing unit, 7) that processes an image signal output from the solid-state imaging device (“A signal processing unit 7 performs various correction processes on image data output from the image pickup device 4 and compresses the data.” paragraph 0077).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Endo et al. (US 2012/0267690) in view of Dai et al. (US 2021/0360175).
Consider claim 10, and as applied to claim 1 above, Endo et al. further teaches that the first substrate (204) includes a plurality of photoelectric conversion units (212, see figure 2).
However, Endo et al. does not explicitly teach that the plurality of photoelectric conversion units is connected to the charge accumulation unit (i.e. that one charge accumulation unit is connected to plurality photoelectric conversion units).
Dai et al. similarly teaches a solid-state imaging device (figure 4) including a plurality of photoelectric conversion units (P1-P4, see paragraphs 0037 and 0048).
However, Dai et al. additionally teaches that the plurality of photoelectric conversion units (P1-P4) is connected to a single charge accumulation unit (FD, see figure 4A, paragraphs 0037 and 0048).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of photoelectric conversion units taught by Endo et al. be connected to a single charge accumulation unit as taught by Dai et al. for the benefit of enabling fast pixel binning to support both high resolution image capture as well as high speed high definition (HD) video (Dai et al., paragraph 0028).
Consider claim 11, and as applied to claim 10 above, Endo et al. further teaches that the pixel circuit includes a plurality of charge accumulation units (213, see figure 2).
However, Endo et al. does not explicitly teach a third wiring that connects the plurality of charge accumulation units.
Dai et al. similarly teaches a plurality of charge accumulation units (FD, figure 4A) and further teaches a third wiring that connects the plurality of charge accumulation units (i.e. connects the plurality of charge accumulation units (FD) via the extra transistor (428), see figure 4A, paragraph 0049).
Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to have the plurality of charge accumulation units taught by Endo et al. be connected via a third wiring as taught by Dai et al. for the benefit of enabling fast pixel binning to support both high resolution image capture as well as high speed high definition (HD) video (Dai et al., paragraph 0028).
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 12 and 13 would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and upon remedying the 35 USC 112 rejections of claims 12 and 13 in the manner suggested herein by the Examiner.
The following is a statement of reasons for the indication of allowable subject matter:
Consider claim 12, the prior art of record does not teach nor reasonably suggest that the third wiring includes a part of the first metal wiring that connects first through electrodes connected to the plurality of charge accumulation units with each other, in combination with the other elements recited in parent claims 1, 10 and 11.
Consider claim 13, the prior art of record does not teach nor reasonably suggest that the third wiring includes fourth wiring that is provided on the first substrate and that connects the first through electrodes connected to the plurality of charge accumulation units with each other, in combination with the other elements recited in parent claims 1, 10, 11 and 12.
Consider claim 17, the prior art of record does not teach nor reasonably suggest that the second metal wiring is connected to a gate electrode of the reset transistor, in combination with the other elements recited in parent claim 15.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Nomoto (US 2021/0400218) teaches an imaging device (figure 42) with a through electrode (801a, paragraph 0335).
Togashi et al. (US 2019/0057997) teaches an imaging device (figure 1A) with a through electrode (14, paragraph 0091).
Togashi et al. (US 2021/0249474) teaches an imaging device (figure 1) with a through electrode (520, paragraph 0100).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALBERT H CUTLER whose telephone number is (571)270-1460. The examiner can normally be reached approximately Mon - Fri 8:00-4:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sinh Tran can be reached at (571)272-7564. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ALBERT H CUTLER/Primary Examiner, Art Unit 2637