DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 01/12/2024 and 08/07/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 18 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 18 recites the limitation " the n-type gallium nitride conductive layer " in line 21-22. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 4, 9, 23, 28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chu et al. [US 2015/0362165 A1], “Chu”.
Regarding claim 1, Chu discloses a chip structure (Fig. 1-40, specifically Fig. 35* annotated for easier referencing – see below), comprising:
a chip wafer unit (Fig. 35*, UV emission region) and a color conversion layer substrate unit (CCL) arranged on a light-exit side of the chip wafer unit (as shown), wherein the chip wafer unit includes a plurality of sub-pixel light-emitting functional layers (as shown in Fig. 2A, 11); and
the color conversion layer substrate unit (CCL) includes a color conversion layer (wavelength conversion layer (WCL)) arranged on the light- exit side of the chip wafer unit (as shown); and
the chip wafer unit further includes a first bonding layer (top dam array +seal material), arranged between the sub- pixel light-emitting functional layers and the color conversion layer, and configured to bond the chip wafer unit and the color conversion layer substrate unit (as shown in Fig. 34 to 35 shows the bonding between the two units) .
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Regarding claim 2, Chu discloses claim 1, Chu discloses the first bonding layer includes a first metal sub-layer, a second metal sub-layer and a third metal sub-layer that are stacked, wherein the third metal sub-layer is closer to the color conversion layer substrate unit than the first metal sub-layer, and the second metal sub-layer is provided as a eutectic alloy layer connecting the first metal sub-layer and the third metal sub-layer; or the first bonding layer (Fig. 35, top dam array +seal material) includes a first bonding sub-layer (top dam array) and a second bonding sub- layer (seal material) that are stacked.
Regarding claim 4, Chu discloses claim 1, Chu discloses the chip wafer unit includes a first sub-pixel light-emitting functional layer (Fig. 35*, 1SP), a second sub-pixel light- emitting functional layer (2SP) and a third sub-pixel light-emitting functional layer (3SP); and the first bonding layer (top dam array +seal material) includes a first opening area (1SP_1O) corresponding to the first sub- pixel light-emitting functional layer (as shown), a second opening area (2SP_2O) corresponding to the second sub-pixel light-emitting functional layer (as shown) and a third opening area (3SP_3O) corresponding to the third sub-pixel light-emitting functional layer (as shown).
Regarding claim 9, Chu discloses claim 1, Chu discloses the chip wafer unit further includes a second bonding layer (Fig. 35*, bottom dam array), wherein the first bonding layer includes a first metal sub-layer, a second metal sub-layer and a third metal sub-layer that are stacked, and a range of a maximum thickness of the first bonding layer is equal to a range of a thickness of the second bonding layer; or the first bonding layer (Fig. 35, top dam array + seal material) includes a first bonding sub-layer (top dam array) and a second bonding sub- layer (seal material ) that are stacked, and a range of a thickness of the first bonding layer is less than a range of a thickness (as shown) of the second bonding layer (bottom dam array).
Regarding claim 23, Chu discloses claim 1, Chu discloses a display substrate (backplane), comprising the chip structure according to claim 1 (as shown in Fig. 35 and ¶[0053]).
Regarding claim 28, Chu discloses claim 23, Chu discloses a display substrate, comprising the chip structure according to claim 23 (as shown in Fig. 35 and ¶[0053]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 5, 7, 8, 16-18 are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. [US 2015/0362165 A1], “Chu” as applied to claim 4, and further in view of Lee et al. [US 2019/0189876 A1], “Lee”.
Regarding claim 5, Chu discloses claim 4, Chu discloses the chip wafer unit of Fig. 35* discloses the first sub-pixel light-emitting functional layer (1SP) includes a first active layer (using Fig. 2A for referencing, active layer), a first p-type gallium nitride portion (p-type layer and ¶[0053] )and a first anode (anode) that are stacked along a first direction (as shown); the second sub-pixel light-emitting functional layer (2SP) includes a second active layer, a second p-type gallium nitride portion and a second anode that are stacked along the first direction (as shown in Fig. 2); the third sub-pixel light-emitting functional layer (3SP) includes a third active layer, a third p-type gallium nitride portion and a third anode that are stacked along the first direction (as shown in Fig. 2) wherein the first direction is a direction from the color conversion layer substrate unit to the chip wafer unit. Further, Chu discloses an electrical conductive connection is to form a row common-cathode array (¶[0059] and Fig. 2D).
Chu does not explicitly disclose the active regions are quantum well regions.
However, Lee disclose an LED structure a light emitting structure (Fig. 5, 110) in which epitaxial layers, such as a first conductivity-type semiconductor layer (111), an active layer (112) and a second conductivity-type semiconductor layer (113). The active layer (112) may have a multiple quantum well (MQW) structure in which a quantum well layer and a quantum barrier layer are alternately stacked. For example, the active layer (122) may have a nitride-based MQW structure (e.g., InGaN/GaN or GaN/AlGaN).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have a quantum well structure as an active layer as taught in Lee in the device of Chu because such a modification would produce light emitting device packages capable of emitting mixed red (R), green (G) and blue (B) light (¶[0020] of Lee).
Chu as modified does not explicitly disclose in Fig. 35 and 2A the common cathode layer includes a cathode metal layer and a cathode electrode that are stacked along the first direction.
However, Chu discloses an alternative design arrangement for the LED array. Specifically, Chu discloses in Fig. 3 a vertical type light engine array (300) on the backplane (30). Light engine array (300) comprises: multiple light engines (31) arranged into an array, multiple dams (32) located on a first surface of the light engines (31). Further, the light engine array (300) has a common cathode region (see Fig. 3). For the cathode part, a common cathode region could be formed to provide the whole n-type of the light engine array (300) conductive connecting to the common cathode. The common cathode region could be arranged to the side of the edge of the light engine (31). For the anode (33) parts, a sub-pixel array region could be formed to provide an individual light engine (31) as a sub-pixel light engine (11) controlling by each individual anode array unit controller on the backplane (30). Chu disclose the vertical type LED array with the dam array can be used as an alternative to the light emitting array unit module (¶[0060]-¶[0083]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use an alternative vertical type light engine array (chip wafer unit) as disclosed in embodiment of Fig. 3 in the embodiment of Fig. 35 of Chu as modified such that vertical type light engine array such that the chip wafer unit further includes a common cathode layer; the first sub-pixel light-emitting functional layer includes a first quantum well, a first p-type gallium nitride portion and a first anode that are stacked along a first direction; the second sub-pixel light-emitting functional layer includes a second quantum well, a second p-type gallium nitride portion and a second anode that are stacked along the first direction; the third sub-pixel light-emitting functional layer includes a third quantum well, a third p-type gallium nitride portion and a third anode that are stacked along the first direction; and the common cathode layer includes a cathode metal layer and a cathode electrode that are stacked along the first direction, wherein the first direction is a direction from the color conversion layer substrate unit to the chip wafer unit because the vertical type light engine array is a suitable alternative way to control to each LED to light up only in the sub-pixel array region to display a mono-color image (¶[0065]).
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Regarding claim 7, Chu as modified discloses claim 5, Chu as modified discloses the chip wafer unit (with reference to the modification of using the alternative chip wafer unit from Fig. 3* (see annotated below for labeling) – see claim 5) further includes a second bonding layer (40,36,35,33), the second bonding layer including a first bonding portion (1BP), a second bonding portion (2BP), a third bonding portion (3BP) and a fourth bonding portion (4BP), wherein the first bonding portion is stacked between the first p-type gallium nitride portion and the first anode; the second bonding portion is stacked between the second p-type gallium nitride portion and the second anode; the third bonding portion is stacked between the third p-type gallium nitride portion and the third anode; and the cathode metal layer of the common cathode layer includes the fourth bonding portion (as shown in Fig 3*).
Regarding claim 8, Chu as modified discloses claim 5, Chu as modified discloses the chip wafer unit (with reference to the modification of using the alternative chip wafer unit from Fig. 3* (see annotated below for labeling) – see claim 5) further includes a second bonding layer (40,36,35,33), the second bonding layer includes including a fourth metal sub-layer (36), a fifth metal sub-layer (35) and a sixth metal sub-layer (33) that are stacked, wherein the sixth metal sub-layer is farther from the color conversion layer substrate unit than the fourth metal sub-layer, and the fifth metal sub-layer is provided as a eutectic alloy layer connecting the sixth metal sub-layer and the fourth metal sub-layer (as shown in Fig. 3*).
Regarding claim 16, Chu as modified discloses claim 5, Chu as modified discloses the chip wafer unit (with reference to the modification of using the alternative chip wafer unit from Fig. 3* (see annotated below for labeling) – see claim 5) further includes a reflective metal layer (40, ¶[0066]), the reflective metal layer including a first reflective portion, a second reflective portion and a third reflective portion, wherein the first reflective portion is stacked between the first p-type gallium nitride portion and the first anode; the second reflective portion is stacked between the second p-type gallium nitride portion and the second anode; and the third reflective portion is stacked between the third p-type gallium nitride portion and the third anode (as shown in Fig. 3).
Regarding claim 17, Chu as modified discloses claim 16, Chu as modified discloses the chip wafer unit (with reference to the modification of using the alternative chip wafer unit from Fig. 3* (see annotated below for labeling) – see claim 5) further a second bonding layer (40,36,35,33), the second bonding layer including a first bonding portion (1BP), a second bonding portion (2BP), a third bonding portion (3BP) and a fourth bonding portion (4BP), wherein the first reflective portion is stacked on a side of the first bonding portion facing the color conversion layer substrate unit; the second reflective portion is stacked on a side of the second bonding portion facing the color conversion layer substrate unit; and the third reflective portion is stacked on a side of the third bonding portion facing the color conversion layer substrate unit (as shown in Fig. 3 and the modification of Fig. 35).
Regarding claim 18, Chu as modified discloses claim 17, Chu as modified discloses the second bonding layer (40,36,35,33) includes a fourth metal sub-layer (36), a fifth metal sub-layer (35) and a sixth metal sub-layer (33) that are stacked, wherein the sixth metal sub-layer is farther from the color conversion layer substrate unit than the fourth metal sub-layer, and the fifth metal sub-layer is provided as a eutectic alloy layer connecting the sixth metal sub-layer and the fourth metal sub-layer (as shown in Fig. 3*); and of the first bonding portion (1BP), the second bonding portion (2BP), the third bonding portion (3BP), and the fourth bonding portion (4BP), each bonding portion includes a respective portion of the fourth metal sub-layer, a respective portion of the fifth metal sub- layer and a respective portion of the sixth metal sub-layer; and
the chip structure further comprises a first insulating layer (Fig. 3, 43) arranged a side of the second bonding layer facing the color conversion layer substrate unit, the first insulating layer(43) being provided therein with a first via hole (Fig. 3*, 1VH), a second via hole (2VH), a third via hole (3VH) and a fourth via hole (4VH), wherein
a respective portion of the fourth metal sub-layer (36) of included in the first bonding portion (1BP) fills the first via hole and is connected to the first reflective portion (40) (as shown in Fig. 3*);
a respective portion of the fourth metal sub-layer (36) of included in the second bonding portion (2BP) fills the second via hole and is connected to the second reflective portion (40);
a respective portion of the fourth metal sub-layer (36) of included in the third bonding portion fills the third via hole (3BP) and is connected to the third reflective portion (40); and
a respective portion of the fourth metal sub-layer (36) of included in the fourth bonding portion (4BP) fills the fourth via hole (4VH)and is connected to the n-type gallium nitride conductive layer (n-type layer).
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chu et al. [US 2015/0362165 A1], “Chu”.
Regarding claim 19, Chu discloses claim 1, Chu discloses wherein the chip wafer unit includes a first sub-pixel light-emitting functional layer (Fig. 35*, 1SP), a second sub-pixel light-emitting functional layer (2SP) and a third sub-pixel light-emitting functional layer (3SP); and
the color conversion layer (CCL) includes a limiting dam layer (BM array), and a fourth opening area (4O), a fifth opening area (5O) and a sixth opening area (6O) that are defined by the limiting dam layer (BM array).
The embodiment of Fig. 35* discloses the color conversion layer have a plurality of color filters and white color conversion positioned over each openings. The color conversion layer further includes: a first color filter (R) part, located in the fourth opening area (4O) and corresponding to the first sub-pixel light-emitting functional layer (1SP); a second color filter (B) part, located in the fifth opening area (5O) and corresponding to the second sub-pixel light-emitting functional layer (2SP); and a third color filter (G) part, located in the sixth opening area (6O)and corresponding to the third sub-pixel light- emitting functional layer (3SP). The embodiment of Fig. 33 does not disclose wherein the color conversion layer further includes: a first quantum dot conversion part, a scattering particle part, and a third quantum dot conversion part.
However, Chu discloses an alternative color conversion layer substrate in embodiment of Fig. 33, the color conversion layer further includes: a first quantum dot conversion part (wavelength conversion layer (R)) (¶[0149]), located in the fourth opening area; a scattering particle part (transparent polymer) (¶[0149] teaches the transparent particles could be selected to mix into the transparent polymer to enhance the transparent polymer structure stability), located in the fifth opening area; and a third quantum dot conversion part (wavelength conversion layer (G)) (¶[0149]), located in the sixth opening area. Using the color conversion layer substrate of embodiment 33, will produce a display with full color images (¶[0149]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date the invention to use the quantum dot conversion substrate of embodiment Fig. 33 in the embodiment of Fig. 35 of Chu such that the color conversion layer further includes: a first quantum dot conversion part, a scattering particle part, and a third quantum dot conversion part because such a modification is a suitable alternative way to convert light to produce a display with full color images (¶[0149]).
Regarding claim 20, Chu as modified discloses claim 19, Chu as modified discloses an orthographic projection of the first sub-pixel light-emitting functional layer (1SP) on the color conversion layer substrate unit (modified with Fig. 33) is within an orthographic projection of the fourth opening area (4O) on the color conversion layer substrate unit (as shown Fig. 35*);
an orthographic projection of the second sub-pixel light-emitting functional layer (2SP) on the color conversion layer substrate unit (modified with Fig. 33) is within an orthographic projection of the fifth opening area (5O) on the color conversion layer substrate unit (as shown Fig. 35*); and
an orthographic projection of the third sub-pixel light-emitting functional layer (3SP) on the color conversion layer substrate unit (modified with Fig. 33) is within an orthographic projection of the sixth opening area (6O) on the color conversion layer substrate unit (as shown Fig. 35*); and/or
the color conversion layer substrate unit further includes alight-gathering layer, the light-gathering layer being arranged on a side of the color conversion layer proximate to the chip wafer unit, wherein the light-gathering layer includes a first light-gathering portion corresponding to the first quantum dot conversion part, a second light-gathering portion corresponding to the scattering particle part, and a third light-gathering portion corresponding to the third quantum dot conversion part; and/or the color conversion layer substrate unit further includes a first substrate and a color filter layer; and the first substrate, the color filter layer and the color conversion layer are stacked along a second direction, the second direction being a direction from the chip wafer unit to the color conversion layer substrate unit, wherein the color filter layer includes a black matrix, and a first light-filtering film corresponding to the first quantum dot conversion part, a second light-filtering film corresponding to the scattering particle part and a third light-filtering film corresponding to the third quantum dot conversion part that are defined by the black matrix.
Claim 24 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. [US 2019/0189876 A1], “Lee” in view of Oida et al.[US 2003/0089923 A1], “Oida” and further in view of Yin et al. [US 2013/0285248 A1], “Yin”.
Regarding claim 24, Lee discloses a manufacturing method for a chip structure (Fig. 7 – 13), the manufacturing method comprising:
forming an initial chip wafer unit (as shown in Fig. 10), the initial chip wafer unit including a temporary substrate (TS), a plurality of sub-pixel light-emitting functional layers (191b, 193b, 192b), a first initial metal sub- layer (190b);
forming a color conversion layer substrate unit (Fig. 9) , the color conversion layer substrate unit including a color conversion layer (166/167) and a first substrate (160) that are stacked (as shown);
forming a third initial metal sub-layer (190a) on a side of the color conversion layer away (as shown) from the first substrate (160);
bonding (Fig. 11) the first initial metal sub-layer (190b), and the third initial metal sub-layer (190a) to form a first bonding layer (190), and
peeling off (Fig. 12) the temporary substrate (TS) to form a chip wafer unit (as shown), wherein the chip wafer unit and the color conversion layer substrate unit are connected through the first bonding layer to form the chip structure (as shown in Fig. 13).
Lee does not disclose a second initial metal sub-layer, wherein the second initial metal sub-layer includes a plurality of first metal protrusions.
Oida discloses a contact structure (Fig. 16A and 17B, 11 and 3) form over the package substrate (2). The solder paste (3) is a Sn--37Pb-based, Sn--Ag-based or Sn--Zn-based. A land (11) serving as a wiring electrode provided on the package substrate (2) is principally made of copper. The solder paste (3) is formed on the land (11). The solder paste can be form with multiple protrusion as show in Fig. 17B. The solder paste pattern is capable of being soldered at a lower temperature and having high soldering reliability (¶[0008]).
Therefore it would have been obvious to one of ordinary skill in art to use a solder layer with protrusion as taught in Oida in the device of Lee such that the device includes a second initial metal sub-layer, wherein the second initial metal sub-layer includes a plurality of first metal protrusions because such a modification would allow for high soldering reliability (¶[0008] of Lee).
Lee as modified does not explicitly disclose bonding (Fig. 11) the first initial metal sub-layer, the second initial metal sub-layer and the third initial metal sub-layer to form a first bonding layer, the first bonding layer including a first metal sub-layer formed by the first initial metal sub-layer, a second metal sub-layer formed by a portion of the first initial metal sub-layer contacting with the second initial metal sub-layer, the second initial metal sub-layer and a portion of the third initial metal sub-layer contacting with the second initial metal sub-layer, and a third metal sub-layer formed by the third initial metal sub-layer, wherein the second metal sub-layer is a eutectic alloy layer connecting the first metal sub-layer and the third metal sub-layer.
However, Yin discloses a first substrate (Fig. 2, 10) and a second substrate (20) are provided, wherein a surface of the first substrate is covered by a first layer (18) and a surface of the second substrate (20) is covered by a second layer (24) and a first Sn layer (28). A bonding process (Fig. 3) is performed by aligning the first and second substrates followed by bringing the first Sn layer (30) into contact with the first layer in order to form intermetallic compounds (30). As shown in Fig. 3, portions of the first layer (18) and second layer (24) react with the first Sn layer in a controlled bonding process to form the junction (30), while a second portion the first layer (18) and second layer (24) remain (as shown in Fig. 3). This bonding process results in increase bonding strength but also would further reduce gradient stress caused by the bonding because of the symmetric arrangement of the metallic film stacks (50) (¶[0019] of Yin).
Therefore it would have been obvious to one of ordinary skilled in the art before the effective filing date of the invention to use a bonding process such that only a portion of the barrier layer is bonded as taught in Yin in the device of Lee as modified such that bonding (Fig. 11) the first initial metal sub-layer, the second initial metal sub-layer and the third initial metal sub-layer to form a first bonding layer, the first bonding layer including a first metal sub-layer formed by the first initial metal sub-layer, a second metal sub-layer formed by a portion of the first initial metal sub-layer contacting with the second initial metal sub-layer, the second initial metal sub-layer and a portion of the third initial metal sub-layer contacting with the second initial metal sub-layer, and a third metal sub-layer formed by the third initial metal sub-layer, wherein the second metal sub-layer is a eutectic alloy layer connecting the first metal sub-layer and the third metal sub-layer because such a modification would allow for an increase bonding strength of the junction (¶[0019] of Yin).
Claim 25 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. [US 2019/0189876 A1], “Lee” in view of Oida et al.[US 2003/0089923 A1], “Oida” and further in view of Yin et al. [US 2013/0285248 A1], “Yin” as applied in claim 24 and further in view of Cha et al. [US 2017/0250318 A1], “ Cha”.
Regarding claim 25, Lee as modified discloses claim 24, Lee as modified the plurality of sub-pixel light-emitting functional layers (Fig. 10). Lee as modified does not discloses forming the initial chip wafer unit, includes: providing a second substrate; forming a plurality of sub-pixel light-emitting functional layers and a common cathode layer; forming the temporary substrate on a side, away from the second substrate, of the plurality of sub-pixel light-emitting functional layers and the common cathode layer; and peeling off the second substrate.
However, Cha discloses a method of manufacturing a light emitting device package. The forming the initial chip wafer unit (Fig. 16A – 16L) includes providing a second substrate (Fig. 16A, 101); forming a plurality of sub-pixel light-emitting functional layers (Fig. 16B) and a common cathode layer (Fig. 16H, 145); forming the temporary substrate on a side (153), away from the second substrate (101), of the plurality of sub-pixel light-emitting functional layers and the common cathode layer (as shown in Fig. 16I); and peeling off the second substrate (Fig. 16J). The substrate with the plurality of sub-pixel light-emitting functional layers and common cathode layer with the wavelength conversion substrate (Fig. 16L).
Therefore it would have been obvious to one of ordinary skilled in the art before the effective filing date of the invention to form the initial chip wafer unit, by providing a second substrate; forming a plurality of sub-pixel light-emitting functional layers and a common cathode layer; forming the temporary substrate on a side, away from the second substrate, of the plurality of sub-pixel light-emitting functional layers and the common cathode layer; and peeling off the second substrate as taught by Cha in the device of Lee as modified because these are known semiconductor methods of forming light emitting devices and electrodes in order to form compact light emitting device package capable of emitting various colors of light (¶[0005] of Cha).
Allowable Subject Matter
Claims 12-14 and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Onuma et al. [US 2021/0043617 A1] disclose an image display element includes micro light emitting elements arranged in an array, a drive circuit substrate that includes a drive circuit for supplying a current to the micro light emitting elements to cause light to be emitted, and an antenna arranged on a light emitting surface of each of the micro light emitting elements, in which the antenna includes isolated convex portions.
Yoo et al. [US 2020/0013759 A1] disclose the first vertical LED chip, the second vertical LED chip, and the third vertical LED chip may be a blue LED chip, a green LED chip, and a red LED chip, respectively.
Suzuki [US 2012/0208308 A1] discloses a stacked body in which a gallium nitride (GaN) buffer layer, an n-type GaN layer, a light emitting layer, and a p-type GaN layer are sequentially stacked.
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PRIYA M. RAMPERSAUD
Examiner
Art Unit 2897
/PRIYA M RAMPERSAUD/Examiner, Art Unit 2897
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