DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5, 7- 9, 16-20, 23, 28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chu et al. [US 2015/0362165 A1], “Chu” in view of Lee et al. [US 2019/0189876 A1], “Lee”.
Regarding claim 1, Chu discloses a chip structure (Fig. 1-40, specifically Fig. 35* annotated for easier referencing – see below), comprising:
a chip wafer unit (Fig. 35*, UV emission region) and a color conversion layer substrate unit (CCL) arranged on a light-exit side of the chip wafer unit (as shown), wherein the chip wafer unit includes a plurality of sub-pixel light-emitting functional layers (as shown in Fig. 2A, 11);
the color conversion layer substrate unit (CCL) includes a color conversion layer (wavelength conversion layer (WCL)) arranged on the light- exit side of the chip wafer unit (as shown); and
the chip wafer unit further includes a first bonding layer (top dam array +seal material), arranged between the sub- pixel light-emitting functional layers and the color conversion layer, and configured to bond the chip wafer unit and the color conversion layer substrate unit (as shown in Fig. 34 to 35 shows the bonding between the two units) ;
the chip wafer unit further includes a first sub-pixel light-emitting functional layer (Fig. 35*, 1SP) and a second sub-pixel light-emitting functional layer (2SP);
the chip wafer unit further includes a second bonding layer (Fig. 35*, bottom dam array), and the second bonding layer includes a first bonding portion (1BP) and a second bonding portion (2BP);
wherein the first bonding portion is stacked between the first p-type gallium nitride portion and the first anode; and the second bonding portion is stacked between the second p-type gallium nitride portion and the second anode (as shown in Fig 3*).
the first sub-pixel light-emitting functional layer includes a first active layer (using Fig. 2A for referencing, active layer), a first p-type gallium nitride portion (p-type layer and ¶[0053] ) and a first anode (anode) that are stacked along a first direction (as shown); and
the second sub-pixel light-emitting functional layer includes a second active layer, a second p-type gallium nitride portion and a second anode that are stacked along the first direction (as shown in Fig. 2);
wherein the first direction is a direction from the color conversion layer substrate unit to the chip wafer unit (as shown in Fig. 2);
Chu does not explicitly disclose the active regions are quantum well regions.
However, Lee discloses an LED structure a light emitting structure (Fig. 5, 110) in which epitaxial layers, such as a first conductivity-type semiconductor layer (111), an active layer (112) and a second conductivity-type semiconductor layer (113). The active layer (112) may have a multiple quantum well (MQW) structure in which a quantum well layer and a quantum barrier layer are alternately stacked. For example, the active layer (122) may have a nitride-based MQW structure (e.g., InGaN/GaN or GaN/AlGaN).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have a quantum well structure as an active layer as taught in Lee in the device of Chu because such a modification would produce light emitting device packages capable of emitting mixed red (R), green (G) and blue (B) light (¶[0020] of Lee).
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Regarding claim 2, Chu as modified discloses claim 1, Chu discloses the first bonding layer includes a first metal sub-layer, a second metal sub-layer and a third metal sub-layer that are stacked, wherein the third metal sub-layer is closer to the color conversion layer substrate unit than the first metal sub-layer, and the second metal sub-layer is provided as a eutectic alloy layer connecting the first metal sub-layer and the third metal sub-layer; or the first bonding layer (Fig. 35, top dam array +seal material) includes a first bonding sub-layer (top dam array) and a second bonding sub- layer (seal material) that are stacked.
Regarding claim 4, Chu as modified discloses claim 1, Chu discloses the chip wafer unit includes a third sub-pixel light-emitting functional layer (3SP); and the first bonding layer (top dam array +seal material) includes a first opening area (1SP_1O) corresponding to the first sub- pixel light-emitting functional layer (as shown), a second opening area (2SP_2O) corresponding to the second sub-pixel light-emitting functional layer (as shown) and a third opening area (3SP_3O) corresponding to the third sub-pixel light-emitting functional layer (as shown).
Regarding claim 5, Chu as modified discloses claim 4, Chu discloses the chip wafer unit of Fig. 35* discloses the third sub-pixel light-emitting functional layer (3SP) includes a third active layer, a third p-type gallium nitride portion and a third anode that are stacked along the first direction (as shown in Fig. 2) wherein the first direction is a direction from the color conversion layer substrate unit to the chip wafer unit. Further, Chu discloses an electrical conductive connection is to form a row common-cathode array (¶[0059] and Fig. 2D).
Chu does not explicitly disclose the active region are quantum well regions.
However, Lee discloses an LED structure a light emitting structure (Fig. 5, 110) in which epitaxial layers, such as a first conductivity-type semiconductor layer (111), an active layer (112) and a second conductivity-type semiconductor layer (113). The active layer (112) may have a multiple quantum well (MQW) structure in which a quantum well layer and a quantum barrier layer are alternately stacked. For example, the active layer (122) may have a nitride-based MQW structure (e.g., InGaN/GaN or GaN/AlGaN).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to have a quantum well structure as an active layer as taught in Lee in the device of Chu as modified because such a modification would produce light emitting device packages capable of emitting mixed red (R), green (G) and blue (B) light (¶[0020] of Lee).
Chu as modified does not explicitly disclose in Fig. 35 and 2A the common cathode layer includes a cathode metal layer and a cathode electrode that are stacked along the first direction.
However, Chu discloses an alternative design arrangement for the LED array. Specifically, Chu discloses in Fig. 3 a vertical type light engine array (300) on the backplane (30). Light engine array (300) comprises: multiple light engines (31) arranged into an array, multiple dams (32) located on a first surface of the light engines (31). Further, the light engine array (300) has a common cathode region (see Fig. 3). For the cathode part, a common cathode region could be formed to provide the whole n-type of the light engine array (300) conductive connecting to the common cathode. The common cathode region could be arranged to the side of the edge of the light engine (31). For the anode (33) parts, a sub-pixel array region could be formed to provide an individual light engine (31) as a sub-pixel light engine (11) controlling by each individual anode array unit controller on the backplane (30). Chu discloses the vertical type LED array with the dam array can be used as an alternative to the light emitting array unit module (¶[0060]-¶[0083]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to use an alternative vertical type light engine array (chip wafer unit) as disclosed in embodiment of Fig. 3 in the embodiment of Fig. 35 of Chu as modified such that vertical type light engine array such that the chip wafer unit further includes a common cathode layer; the first sub-pixel light-emitting functional layer includes a first quantum well, a first p-type gallium nitride portion and a first anode that are stacked along a first direction; the second sub-pixel light-emitting functional layer includes a second quantum well, a second p-type gallium nitride portion and a second anode that are stacked along the first direction; the third sub-pixel light-emitting functional layer includes a third quantum well, a third p-type gallium nitride portion and a third anode that are stacked along the first direction; and the common cathode layer includes a cathode metal layer and a cathode electrode that are stacked along the first direction, wherein the first direction is a direction from the color conversion layer substrate unit to the chip wafer unit because the vertical type light engine array is a suitable alternative way to control to each LED to light up only in the sub-pixel array region to display a mono-color image (¶[0065]).
Regarding claim 7, Chu as modified discloses claim 5, Chu as modified discloses the second bonding layer (40,36,35,33), the second bonding layer including a third bonding portion (3BP) and a fourth bonding portion (4BP), wherein the third bonding portion is stacked between the third p-type gallium nitride portion and the third anode; and the cathode metal layer of the common cathode layer includes the fourth bonding portion (as shown in Fig 3* above).
Regarding claim 8, Chu as modified discloses claim 5, Chu as modified discloses the second bonding layer (40,36,35,33) includes including a fourth metal sub-layer (36), a fifth metal sub-layer (35) and a sixth metal sub-layer (33) that are stacked, wherein the sixth metal sub-layer is farther from the color conversion layer substrate unit than the fourth metal sub-layer, and the fifth metal sub-layer is provided as a eutectic alloy layer connecting the sixth metal sub-layer and the fourth metal sub-layer (as shown in Fig. 3*).
Regarding claim 9, Chu as modified discloses claim 1, Chu discloses the first bonding layer includes a first metal sub-layer, a second metal sub-layer and a third metal sub-layer that are stacked, and a range of a maximum thickness of the first bonding layer is equal to a range of a thickness of the second bonding layer; or the first bonding layer (Fig. 35, top dam array + seal material) includes a first bonding sub-layer (top dam array) and a second bonding sub- layer (seal material ) that are stacked, and a range of a thickness of the first bonding layer is less than a range of a thickness (as shown) of the second bonding layer (bottom dam array).
Regarding claim 16, Chu as modified discloses claim 5, Chu as modified discloses the chip wafer unit (with reference to the modification of using the alternative chip wafer unit from Fig. 3* (see annotated below for labeling) – see claim 5) further includes a reflective metal layer (40, ¶[0066]), the reflective metal layer including a first reflective portion, a second reflective portion and a third reflective portion, wherein the first reflective portion is stacked between the first p-type gallium nitride portion and the first anode; the second reflective portion is stacked between the second p-type gallium nitride portion and the second anode; and the third reflective portion is stacked between the third p-type gallium nitride portion and the third anode (as shown in Fig. 3).
Regarding claim 17, Chu as modified discloses claim 16, Chu as modified discloses the second bonding layer (40,36,35,33) future includes a third bonding portion (3BP) and a fourth bonding portion (4BP), wherein the first reflective portion is stacked on a side of the first bonding portion facing the color conversion layer substrate unit; the second reflective portion is stacked on a side of the second bonding portion facing the color conversion layer substrate unit; and the third reflective portion is stacked on a side of the third bonding portion facing the color conversion layer substrate unit (as shown in Fig. 3 and the modification of Fig. 35).
Regarding claim 18, Chu as modified discloses claim 17, Chu as modified discloses the second bonding layer (40,36,35,33) includes a fourth metal sub-layer (36), a fifth metal sub-layer (35) and a sixth metal sub-layer (33) that are stacked, wherein the sixth metal sub-layer is farther from the color conversion layer substrate unit than the fourth metal sub-layer, and the fifth metal sub-layer is provided as a eutectic alloy layer connecting the sixth metal sub-layer and the fourth metal sub-layer (as shown in Fig. 3*); and of the first bonding portion (1BP), the second bonding portion (2BP), the third bonding portion (3BP), and the fourth bonding portion (4BP), each bonding portion includes a respective portion of the fourth metal sub-layer, a respective portion of the fifth metal sub- layer and a respective portion of the sixth metal sub-layer; and
the chip structure further comprises a first insulating layer (Fig. 3, 43) arranged a side of the second bonding layer facing the color conversion layer substrate unit, the first insulating layer(43) being provided therein with a first via hole (Fig. 3*, 1VH), a second via hole (2VH), a third via hole (3VH) and a fourth via hole (4VH), wherein
a respective portion of the fourth metal sub-layer (36) included in the first bonding portion (1BP) fills the first via hole and is connected to the first reflective portion (40) (as shown in Fig. 3*);
a respective portion of the fourth metal sub-layer (36) of included in the second bonding portion (2BP) fills the second via hole and is connected to the second reflective portion (40);
a respective portion of the fourth metal sub-layer (36) of included in the third bonding portion fills the third via hole (3BP) and is connected to the third reflective portion (40); and
a respective portion of the fourth metal sub-layer (36) included in the fourth bonding portion (4BP) fills the fourth via hole (4VH)and is connected to an n-type gallium nitride conductive layer (n-type layer).
Regarding claim 19, Chu as modified discloses claim 1, Chu discloses wherein the chip wafer unit further includes a third sub-pixel light-emitting functional layer (3SP); and
the color conversion layer (CCL) includes a limiting dam layer (BM array), and a fourth opening area (4O), a fifth opening area (5O) and a sixth opening area (6O) that are defined by the limiting dam layer (BM array).
The embodiment of Fig. 35* discloses the color conversion layer have a plurality of color filters and white color conversion positioned over each opening. The color conversion layer further includes: a first color filter (R) part, located in the fourth opening area (4O) and corresponding to the first sub-pixel light-emitting functional layer (1SP); a second color filter (B) part, located in the fifth opening area (5O) and corresponding to the second sub-pixel light-emitting functional layer (2SP); and a third color filter (G) part, located in the sixth opening area (6O)and corresponding to the third sub-pixel light- emitting functional layer (3SP). The embodiment of Fig. 33 does not disclose wherein the color conversion layer further includes: a first quantum dot conversion part, a scattering particle part, and a third quantum dot conversion part.
However, Chu discloses an alternative color conversion layer substrate in embodiment of Fig. 33, the color conversion layer further includes: a first quantum dot conversion part (wavelength conversion layer (R)) (¶[0149]), located in the fourth opening area; a scattering particle part (transparent polymer) (¶[0149] teaches the transparent particles could be selected to mix into the transparent polymer to enhance the transparent polymer structure stability), located in the fifth opening area; and a third quantum dot conversion part (wavelength conversion layer (G)) (¶[0149]), located in the sixth opening area. Using the color conversion layer substrate of embodiment 33, will produce a display with full color images (¶[0149]).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date the invention to use the quantum dot conversion substrate of embodiment Fig. 33 in the embodiment of Fig. 35 of Chu as modified such that the color conversion layer further includes: a first quantum dot conversion part, a scattering particle part, and a third quantum dot conversion part because such a modification is a suitable alternative way to convert light to produce a display with full color images (¶[0149]).
Regarding claim 20, Chu as modified discloses claim 19, Chu as modified discloses an orthographic projection of the first sub-pixel light-emitting functional layer (1SP) on the color conversion layer substrate unit (modified with Fig. 33) is within an orthographic projection of the fourth opening area (4O) on the color conversion layer substrate unit (as shown Fig. 35*);
an orthographic projection of the second sub-pixel light-emitting functional layer (2SP) on the color conversion layer substrate unit (modified with Fig. 33) is within an orthographic projection of the fifth opening area (5O) on the color conversion layer substrate unit (as shown Fig. 35*); and
an orthographic projection of the third sub-pixel light-emitting functional layer (3SP) on the color conversion layer substrate unit (modified with Fig. 33) is within an orthographic projection of the sixth opening area (6O) on the color conversion layer substrate unit (as shown Fig. 35*); and/or
the color conversion layer substrate unit further includes alight-gathering layer, the light-gathering layer being arranged on a side of the color conversion layer proximate to the chip wafer unit, wherein the light-gathering layer includes a first light-gathering portion corresponding to the first quantum dot conversion part, a second light-gathering portion corresponding to the scattering particle part, and a third light-gathering portion corresponding to the third quantum dot conversion part; and/or the color conversion layer substrate unit further includes a first substrate and a color filter layer; and the first substrate, the color filter layer and the color conversion layer are stacked along a second direction, the second direction being a direction from the chip wafer unit to the color conversion layer substrate unit, wherein the color filter layer includes a black matrix, and a first light-filtering film corresponding to the first quantum dot conversion part, a second light-filtering film corresponding to the scattering particle part and a third light-filtering film corresponding to the third quantum dot conversion part that are defined by the black matrix.
Regarding claim 23, Chu as modified discloses claim 1, Chu discloses a display substrate (backplane), comprising the chip structure according to claim 1 (as shown in Fig. 35 and ¶[0053]).
Regarding claim 28, Chu as modified discloses claim 23, Chu discloses a display substrate, comprising the chip structure according to claim 23 (as shown in Fig. 35 and ¶[0053]).
Response to Arguments
Applicants’ arguments filed 08/07/2026 have been fully considered but they are not persuasive. Applicant has argued, “that the first anode and the second anode are internal electrodes of the sub-pixel light-emitting functional layers and form part of the chip wafer unit. That is, the first anode and the second anode are part of the chip structure. The first bonding section and the second bonding section included in the second bonding layer bond to the first anode and the second anode within the chip structure,” which the prior art does not disclose - see remarks on pages 18-21.
The Examiner respectfully disagrees. The specification nor the claims as current written does not disclose the electrode as “internal electrode”. Further Cha does disclose the electrodes are part of the packaging for the sub-pixel light-emitting functional layers. It is unclear exactly what makes the electrode “internal”. As such the rejection under 35 USC § 103 is maintained.
Allowable Subject Matter
Claims 12-14 are objected to as being dependent upon a rejected base claim but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 24, 24 and 28 are allowed.
Claim 24, none of the prior art teaches or suggests, alone or in combination, all of the structural features of the claims, specifically including but not limited to, “forming the initial chip wafer unit, includes: providing a second substrate; forming a plurality of sub-pixel light-emitting functional layers and a common cathode layer; forming the temporary substrate on a side, away from the second substrate, of the plurality of sub-pixel light-emitting functional layers and the common cathode layer; and peeling off the second substrate; wherein forming the plurality of sub-pixel light-emitting functional layers and the common cathode layer, and forming the temporary substrate on the side, away from the second substrate, of the plurality of sub-pixel light-emitting functional layers and the common cathode layer, include: forming an initial gallium nitride buffer layer, an initial n-type gallium nitride layer, an initial quantum well layer and an initial p-type gallium nitride layer on the side of the second substrate sequentially, and patterning the initial quantum well layer and the initial p-type gallium nitride layer to form a quantum well layer and a p-type gallium nitride layer of the initial chip wafer unit; forming a first preliminary insulating layer on a side of the p-type gallium nitride layer away from the quantum well layer, the first preliminary insulating layer being provided therein with a plurality of via holes; forming a fourth initial metal sub-layer and a fifth initial metal sub-layer on a side of the first preliminary insulating layer away from the second substrate, wherein the plurality of via holes provided in the first preliminary insulating layer are filled with the fourth initial metal sub-layer, and the fifth initial metal sub-layer includes a plurality of second-type metal protrusions; providing the temporary substrate; forming a sixth initial metal sub-layer of the initial chip wafer unit on a side of the temporary substrate; and bonding the sixth initial metal sub-layer, the fifth initial metal sub-layer and the fourth initial metal sub-layer to form a second bonding layer, the second bonding layer including a fourth metal sub-layer formed by the fourth initial metal sub-layer, a fifth metal sub-layer formed by a portion of the fourth initial metal sub-layer contacting with the fifth initial metal sub-layer, the fifth initial metal sub-layer and a portion of the sixth initial metal sub-layer contacting with the fifth initial metal sub-layer and a sixth metal sub-layer formed by the sixth initial metal sub-layer, wherein the fifth metal sub-layer is arranged as a eutectic alloy layer connecting the sixth metal sub-layer and the fourth metal sub-layer, and a portion of the second bonding layer is formed as the common cathode layer,” as required by the claim.
Claim 26 is allowed by virtues of their dependencies on claim 24.
Claim 29, none of the prior art teaches or suggests, alone or in combination, all of the structural features of the claims, specifically including but not limited to, “wherein forming the plurality of sub-pixel light-emitting functional layers and the common cathode layer, and forming the temporary substrate on a side, away from the second substrate, of the plurality of sub-pixel light-emitting functional layers and the common cathode layer, include: forming an initial gallium nitride buffer layer, an initial n-type gallium nitride layer, an initial quantum well layer and an initial p-type gallium nitride layer on the side of the second substrate sequentially, and patterning the initial quantum well layer and the initial p-type gallium nitride layer to form a quantum well layer and a p-type gallium nitride layer of the initial chip wafer unit; forming a cathode metal layer of the common cathode layer; forming a second preliminary insulating layer on a side, away from the color conversion layer substrate unit, of the p-type gallium nitride layer and the cathode metal layer, the second preliminary insulating layer being provided therein with a plurality of via holes; forming electrodes, the electrodes including a cathode electrode and anode electrodes, and the cathode electrode and the anode electrodes each fill a corresponding via hole of the plurality of via holes in the second preliminary insulating layer, so as to form the plurality of sub-pixel light-emitting functional layers and the common cathode layer of the initial chip wafer unit; and bonding the plurality of sub-pixel light-emitting functional layers and the common cathode layer on the temporary substrate; and after peeling off the second substrate, forming the initial chip wafer unit, further includes: patterning the initial gallium nitride buffer layer, the initial n-type gallium nitride layer and the second preliminary insulating layer to form a gallium nitride buffer layer, an n-type gallium nitride layer and a second insulating layer of the initial chip wafer unit, forming the first initial metal sub-layer and the second initial metal sub-layer on the gallium nitride buffer layer, and roughening a surface of the gallium nitride buffer layer to form the initial chip wafer unit,” as required by the claim.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Onuma et al. [US 2021/0043617 A1] disclose an image display element includes micro light emitting elements arranged in an array, a drive circuit substrate that includes a drive circuit for supplying a current to the micro light emitting elements to cause light to be emitted, and an antenna arranged on a light emitting surface of each of the micro light emitting elements, in which the antenna includes isolated convex portions.
Yoo et al. [US 2020/0013759 A1] disclose the first vertical LED chip, the second vertical LED chip, and the third vertical LED chip may be a blue LED chip, a green LED chip, and a red LED chip, respectively.
Suzuki [US 2012/0208308 A1] discloses a stacked body in which a gallium nitride (GaN) buffer layer, an n-type GaN layer, a light emitting layer, and a p-type GaN layer are sequentially stacked.
Applicants’ amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRIYA M RAMPERSAUD whose telephone number is (571)272-3464. The examiner can normally be reached Mon-Wed 9am-6pm.
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PRIYA M. RAMPERSAUD
Examiner
Art Unit 2897
/P.M.R/Examiner, Art Unit 2897
/MARK W TORNOW/Primary Examiner, Art Unit 2891
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