Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
2. The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
3. The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office Action.
4. This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitations are: “a learning unit” in claim 3, “a software generation unit” in claim 4, “an input conversion unit” in claims 5-7, “a conversion step for ...” in claims 9-10, “a conversion step for ...” and “a computation step for ...” in claim 11, and “a computation step for ...” in claim 12 .
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. Hardware support is found for example in [0031], [0033], and [0047] of Applicants’ published specification.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 103
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office Action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claims 1-3, 5-7, and 9-12 are rejected under 35 U.S.C. 103 as being unpatentable over U.S. Patent Application Publication No. 2020/0226444 (“Sharma”) in view of WO 2020/248424 A (“Liu”).
Regarding claim 1, SHARMA teaches A neural network generation device that generates a neural network execution model for performing operations of a neural network (Abstract: “... a hardware accelerator with a heterogenous architecture for training quantized neural networks is described.”, where an accelerator as mentioned is defined as a hardware/software component per [0052]), wherein:
the neural network execution model converts input data including elements with 8 bits or more to converted values with fewer bits than the elements ... ([0080]: “Inference phase 201 includes operations 202, 204, 206, 208, 210, 212, and 214. Data is quantized in operations 202, 208, and 214. At operation 202, the method includes receiving input data for an input layer with the input data being quantized (e.g., quantized from a first precision datatype for input data into a second precision datatype). ... ” where the precision range is a flexible precision range per [0106] such that inputs can be of the following precision: “The CU supports a flexible range of precision for the floating point or fixed point inputs 601-608 (e.g., floating point 32 bit 601, fixed point 2 bit 602, floating point 32 bit 603, fixed point 2 bit 604, floating point 32 bit 605, fixed point 2 bit 606, floating point 32 bit 607, fixed point 2 bit 608)—activations in the forward phase and the gradients in the backward phase.”, where precisions of 32 bits satisfies the recitation for “8 bits or more” and 2 bits satisfies the recitation for “fewer bits”).
Sharma does not teach it’s conversion, as discussed above, is based on comparisons with multiple threshold values. Rather, the Examiner relies upon LIU to teach what Sharma otherwise lacks, see e.g., Liu’s page 18, 1st and 2nd full paragraphs as marked by the Examiner with arrow annotations, the reference teaching the adjustment of data bit width based on error thresholds.
Liu and Sharma both relate to flexible-precision architectures as applied to machine-learning / neural network tasks. Hence, they are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Liu’s threshold-based precision adjustment into a framework such as Sharma’s, with a reasonable expectation of success, such as to balance any tradeoffs that might exist between accuracy in modeling and its resource demands/constraints that are mitigatable via precision adjustments (as contemplated by Liu but also more generally by Sharma).
Regarding claim 2, Sharma in view of Liu teach the neural network generation device according to claim 1, as discussed above. The aforementioned references further teach the additional limitations wherein: the neural network execution model converts at least some of the elements of the input data to the converted values with 2 bits or fewer (Sharma as discussed per claim 1 above: the precision range is a flexible precision range per [0106] such that inputs can be of the following precision: “The CU supports a flexible range of precision for the floating point or fixed point inputs 601-608 (e.g., floating point 32 bit 601, fixed point 2 bit 602, floating point 32 bit 603, fixed point 2 bit 604, floating point 32 bit 605, fixed point 2 bit 606, floating point 32 bit 607, fixed point 2 bit 608)—activations in the forward phase and the gradients in the backward phase.”, and from this, the Examiner understands that precision may be mixed / quantized differently based on the particular operations within the architecture as taught). The motivation for combining the references is as discussed above in relation to claim 1.
Regarding claim 3, Sharma in view of Liu teach the neural network generation device according to claim 1, as discussed above. The aforementioned references further teach the additional limitations
comprising: a learning unit that learns learned parameters of the neural network execution model (Sharma: [0067] and [0082]-[0085] discussing the determination of weights and other parameters as a function of the training phase); and wherein the learning unit generates the threshold values and weights used in convolution operations implemented by the neural network (Sharma: [0081] discussing the computation/operation to be a convolution operation). The motivation for combining the references is as discussed above in relation to claim 1.
Regarding claim 5, SHARMA teaches A neural network computing device comprising:
an input conversion unit that converts input data including elements with 8 bits or more to converted values with fewer bits than the elements ... ([0080]: “Inference phase 201 includes operations 202, 204, 206, 208, 210, 212, and 214. Data is quantized in operations 202, 208, and 214. At operation 202, the method includes receiving input data for an input layer with the input data being quantized (e.g., quantized from a first precision datatype for input data into a second precision datatype). ... ” where the precision range is a flexible precision range per [0106] such that inputs can be of the following precision: “The CU supports a flexible range of precision for the floating point or fixed point inputs 601-608 (e.g., floating point 32 bit 601, fixed point 2 bit 602, floating point 32 bit 603, fixed point 2 bit 604, floating point 32 bit 605, fixed point 2 bit 606, floating point 32 bit 607, fixed point 2 bit 608)—activations in the forward phase and the gradients in the backward phase.”, where precisions of 32 bits satisfies the recitation for “8 bits or more” and 2 bits satisfies the recitation for “fewer bits”); and
a convolution operation circuit to which the converted values are input (Sharma: [0081] discussing the computation/operation to be a convolution operation).
Sharma does not teach the input conversion unit’s conversion, as discussed above, is based on comparisons with multiple threshold values. Rather, the Examiner relies upon LIU to teach what Sharma otherwise lacks, see e.g., Liu’s page 18, 1st and 2nd full paragraphs as marked by the Examiner with arrow annotations, the reference teaching the adjustment of data bit width based on error thresholds.
Liu and Sharma both relate to flexible-precision architectures as applied to machine-learning / neural network tasks. Hence, they are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Liu’s threshold-based precision adjustment into a framework such as Sharma’s, with a reasonable expectation of success, such as to balance any tradeoffs that might exist between accuracy in modeling and its resource demands/constraints that are mitigatable via precision adjustments (as contemplated by Liu but also more generally by Sharma).
Regarding claim 6, Sharma in view of Liu teach the neural network computing device according to claim 5, as discussed above. The aforementioned references further teach the additional limitation wherein: the input conversion unit converts at least some of the elements of the input data to the converted values with 2 bits or fewer (Sharma as discussed per claim 1 above: the precision range is a flexible precision range per [0106] such that inputs can be of the following precision: “The CU supports a flexible range of precision for the floating point or fixed point inputs 601-608 (e.g., floating point 32 bit 601, fixed point 2 bit 602, floating point 32 bit 603, fixed point 2 bit 604, floating point 32 bit 605, fixed point 2 bit 606, floating point 32 bit 607, fixed point 2 bit 608)—activations in the forward phase and the gradients in the backward phase.”, and from this, the Examiner understands that precision may be mixed / quantized differently based on the particular operations within the architecture as taught). The motivation for combining the references is as discussed above in relation to claim 5.
Regarding claim 7, Sharma in view of Liu teach the neural network computing device according to claim 6, as discussed above. The aforementioned references further teach the additional limitation wherein: the input conversion unit has multiple conversion units that convert the input data to the converted values; and the number of the multiple conversion units is equal to or greater than a difference in bit precision before and after conversion by the conversion units (Sharma’s [0077]: “The compute intensive convolution and fully-connected layers, which require a large number of simple MAC operations, are interleaved with resource intensive quantization transformations, which perform fewer operations but need more FPGA resources for implementing the complex operations.”). The motivation for combining the references is as discussed above in relation to claim 5.
Regarding claim 9, SHARMA teaches A neural network control method for controlling neural network hardware for performing operations of a neural network (Abstract: “... a hardware accelerator with a heterogenous architecture for training quantized neural networks is described.”, where an accelerator as mentioned is defined as a hardware/software component per [0052], and where the neural network as trained is used in inference per [0080] for example), the method comprising:
a conversion step for converting input data including elements with 8 bits or more to converted values with fewer bits than the elements ... ([0080]: “Inference phase 201 includes operations 202, 204, 206, 208, 210, 212, and 214. Data is quantized in operations 202, 208, and 214. At operation 202, the method includes receiving input data for an input layer with the input data being quantized (e.g., quantized from a first precision datatype for input data into a second precision datatype). ... ” where the precision range is a flexible precision range per [0106] such that inputs can be of the following precision: “The CU supports a flexible range of precision for the floating point or fixed point inputs 601-608 (e.g., floating point 32 bit 601, fixed point 2 bit 602, floating point 32 bit 603, fixed point 2 bit 604, floating point 32 bit 605, fixed point 2 bit 606, floating point 32 bit 607, fixed point 2 bit 608)—activations in the forward phase and the gradients in the backward phase.”, where precisions of 32 bits satisfies the recitation for “8 bits or more” and 2 bits satisfies the recitation for “fewer bits”); and
a computation step for implementing convolution operations on the converted values (Sharma: [0081] discussing the computation/operation to be a convolution operation).
Sharma does not teach the conversion step, as discussed above, is based on comparisons with multiple threshold values. Rather, the Examiner relies upon LIU to teach what Sharma otherwise lacks, see e.g., Liu’s page 18, 1st and 2nd full paragraphs as marked by the Examiner with arrow annotations, the reference teaching the adjustment of data bit width based on error thresholds.
Liu and Sharma both relate to flexible-precision architectures as applied to machine-learning / neural network tasks. Hence, they are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Liu’s threshold-based precision adjustment into a framework such as Sharma’s, with a reasonable expectation of success, such as to balance any tradeoffs that might exist between accuracy in modeling and its resource demands/constraints that are mitigatable via precision adjustments (as contemplated by Liu but also more generally by Sharma).
Regarding claim 10, Sharma in view of Liu teach the neural network control method according to claim 9, as discussed above. The aforementioned references teach the additional limitation wherein: the conversion step is processed in advance by a device other than the neural network hardware (Sharma’s [0080]: “Inference phase 201 includes operations 202, 204, 206, 208, 210, 212, and 214. Data is quantized in operations 202, 208, and 214. At operation 202, the method includes receiving input data for an input layer with the input data being quantized (e.g., quantized from a first precision datatype for input data into a second precision datatype). ... ”, for which the Examiner reasons that the quantization could be performed on the inputs as received or prior to the inputs being provided to the network’s entry/input layer as a matter of design choice). The motivation for combining the references is as discussed above in relation to claim 9.
Regarding claim 11, the claim includes the same or similar limitations as discussed above per claim 5, and is therefore rejected under the same rationale.
Regarding claim 12, the claim includes the same or similar limitations as discussed above per claim 5, and is therefore rejected under the same rationale.
9. Claims 4 and 8 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma in view of Liu and further in view of Non-Patent Literature “ML Inference on Edge devices with ONNX Runtime using Azure DevOps” (“Goswami”).
Regarding claim 4, Sharma in view of Liu teach the neural network generation device according to claim 1, as discussed above. The aforementioned references teach neural network training and development for applied inference, as discussed above with respect to claim 1, and where the neural network is a hardware-software implementation (see e.g., Sharma’s [0052]). However, they do not teach the further limitations of a a software generation unit that generates software for operating neural network hardware in which the neural network execution model is at least partially installed in the hardware and wherein the software generation unit generates the software, which converts the input data to the converted values, and which inputs the converted values to the neural network hardware. At best, Sharma teaches or at least implies a training/development environment for its explicitly taught training for its neural network, which the Examiner reasons could be the equivalent of the recited software generation unit. However, to the extent that Sharma’s training environment is not sufficient, the Examiner further relies upon GOSWAMI to teach what Sharma etc. otherwise lack, see e.g., Goswami’s page 2, bottom paragraph, discussing a model development framework using Azure DevOps, which the Examiner understands to be an explicit software environment/platform for model training, development, and deployment.
Liu and Sharma both relate to flexible-precision architectures as applied to machine-learning / neural network tasks. More general to them, Goswami teaches a development environment that uses such an architecture, or similar, to create models for a similar purpose. Hence, they are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Sharma’s modified framework into a development environment, such as Goswami’s, with a reasonable expectation of success, to streamline and manage all the steps that go into model creation and deployment and related functions.
Regarding claim 8, Sharma in view of Liu teach the neural network computing device according to claim 5, as discussed above. However, the aforementioned references do not teach the additional limitations of An edge device comprising the neural network computing device according to claim 5 and
a power supply for operating the neural network computing device. Rather, the Examiner relies upon GOSWAMI to teach what Sharma etc. otherwise lack, see e.g., Goswami’s page 2, bottom paragraph, discussing a model development framework to create a model comparable to Sharma’s that can then be deployed per Goswami to an edge device for inference. The Examiner understands both Goswami and also Sharma to feature devices, both in the model development/training and inference phases, that necessarily feature and involve power supply elements so as to function as intended. Said another way, these device as discussed need electrical power to operate generally and more specifically to perform the model-related aspects discussed here.
Liu and Sharma both relate to flexible-precision architectures as applied to machine-learning / neural network tasks. More general to them, Goswami teaches a development environment that uses such an architecture, or similar, to create models for a similar purpose. Hence, they are similarly directed and therefore analogous. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Sharma’s modified framework into a development environment, such as Goswami’s, with a reasonable expectation of success, to streamline and manage all the steps that go into model creation and deployment and related functions.
Conclusion
10. The prior art made of record and not relied upon is considered pertinent to Applicants’ disclosure:
CN-109947573-A Zhang
CN-111783974-A Zhang
Non-Patent Literature “Efficient Deep Learning Inference on Edge Devices” (Jiang)
Non-Patent Literature “A Review of Recent Advances of Binary Neural Networks for Edge Computing” (Zhao)
Non-Patent Literature “Quantizing deep convolutional networks for efficient inference: A whitepaper” (Krishnamoorthi)
Non-Patent Literature “Deep Learning Optimization for Edge Devices: Analysis of Training Quantization Parameters” (Kwasniewska)
11. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHOURJO DASGUPTA whose telephone number is (571)272-7207. The examiner can normally be reached M-F 8am-5pm CST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tamara Kyle can be reached at 571 272 4241. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHOURJO DASGUPTA/Primary Examiner, Art Unit 2144
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