DETAILED ACTION
The present application is being examined under the pre-AIA first to invent provisions.
Response to Amendment
This Office Action responses to the Applicant’s Amendment filed on 10/15/2025 in which claims 10 and 27 have been amended.
Claims 1-29 are pending for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2003/0210573).
Regarding independent claim 1, Lee discloses a method of memory storage (see Abstract), comprising: programming a first data node operatively coupled to a first charge trap transistor to a first level (Vtp, figures 3 and 4) above a threshold (VTEC, figures 1-4, also see para.[0021] discloses: Embodiments of the present invention may be used with an electrically erasable charge trap nonvolatile memory cell structure of FIG. 1, which includes a transistor in an integrated circuit substrate 1 and para.[0037] discloses: ); decreasing, below the threshold (VTEC, figure 4), a first voltage (VTe, figure 3) at the first charge trap transistor (Fig 1-4 para.[0037] discloses: a pair of first curves 1p and 1e correspond to the result of an endurance test performed by applying the initial erase time interval. The curve 1p indicates program threshold voltages V.sub.Tp measured whenever each program operation is completed during the endurance test. The curve 1e indicates erase threshold voltages V.sub.Te measured whenever each erase operation is completed during the endurance testThe curve 1e indicates erase threshold voltages V.sub.Te measured whenever each erase operation is completed during the endurance test. As can be seen from the curves 1p and 1e, in a case where the endurance test is performed by applying the initial erase time interval, a maximum erase threshold voltage V.sub.TEMX is lower than a critical erase threshold voltage V.sub.TEC and a minimum program threshold voltage V.sub.TPMN is lower than a critical program threshold voltage V.sub.TPC. Thus, the endurance of a newly programmed cell is tested by applying a second erase time interval that is shorter than the initial erase time interval..); increasing, above the threshold (VTEC), the first voltage at the first charge trap transistor (e.g., programming back to VTp in subsequent program cycles) (figures 1-4, para.[0031], “.. number of the erease/program cycles.. “para.[0037], also figure 4 shows multiple program and erase cycles are provided) ; and reprogramming, the first data node to the first level (VTp), in response to an interruption of the first voltage (Vte) at the first charge trap transistor caused by the decreasing and the increasing (figures 1-4, para.[0031], “the program threshold voltage VTp and the erase threshold voltage VTe vary as the erase/program cycles increase in number.. “para.[0037], note subsequent programming cycles are deemed equivalent to reprogramming the transistor data node to first level VTp after an “interruption” which in interpreted to correspond to a previous program/erase cycle}.
Regarding claim 2, Lee discloses the limitation of claim 1.
Lee further discloses further comprising: programming the first charge trap transistor at the first level in a store mode (figures 1-4, para.[0024] discloses: It will be understood that the initial threshold voltage is defined when charge is not stored in the charge trapping region and the program threshold voltage is defined when charge is stored in the charge trapping region).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evide
nce present in the application indicating obviousness or nonobviousness.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2003/0210573) in view of Lee et al. (US 2008/0205140).
Regarding claim 3, Lee discloses the limitation of claim 1.
However, Lee is silent with respect to wherein the first level corresponds to a first digital state.
Lee et al. disclose wherein the first level corresponds to a first digital state (figure 1 a, and figure 1b, para.[0049] discloses: The dual-sided flash memory cell stores the digital data bits as trapped charge within the charge trapping layer 35 above the channel 25 that is formed between drain 15 and source 20).
Since Lee and Lee et al. are both from the same field of endeavor, the purpose disclosed by Lee et al. would have been recognized in the pertinent art of Lee.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Lee to teaching of Lee et al. for purpose of providing the first level to correspond to a first digital state to facilitate nonvolatile memory storage.
Claim(s) 4, 5 and 7-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2003/0210573) in view of Anand et al. (US 10,468,104).
Regarding claim 4, Lee discloses the limitation of claim 1.
However, Lee is silent with respect to wherein the programming the first data node comprises setting a first node voltage at the first data node to the first level based on a first transistor voltage across a drain and a source of the first charge trap transistor.
Anand et al. disclose wherein the programming the first data (Program 73, figure 5 below) node comprises setting a first node voltage at the first data node (first input, figure 5 below) to the first level based on a first transistor voltage (73, figure 5 below) across a drain and a source of the first charge trap transistor (71, figure 5 below).
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Since Lee and Anand et al. are both from the same field of endeavor, the purpose disclosed Anand et al. would have been recognized in the pertinent art of Lee.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Lee to teaching of Anand et al. for purpose of providing the first level to correspond to a first digital state to facilitate nonvolatile memory storage.
Regarding claim 5, Lee discloses the limitation of claim 1.
However, Lee is silent with respect programming a second data node operatively coupled to a second charge trap transistor to a second level.
Anand et al. disclose programming (Program, figure 5 above) a second data node (second data node, figure 5 above) operatively coupled to a second charge trap transistor to a second level (72, figure 5 above, also see figure 6).
Since Lee and Anand et al. are both from the same field of endeavor, the purpose disclosed Anand et al. would have been recognized in the pertinent art of Lee.
It would have been obvious to one of ordinary skill in the art before the earliest effective filing date to apply the teaching of Lee to teaching of Anand et al. for purpose of providing the first level to correspond to a first digital state to facilitate nonvolatile memory storage.
Regarding claim 7, the combination of Lee and Anand et al. disclose the limitation of claim 5.
Anand et al. further disclose programming the second charge trap transistor (72, figure 5) at the second level in a store mode (figure 6 below).
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Regarding claim 8, the combination of Lee and Anand et al. disclose the limitation of claim 5.
Anand et al. further disclose wherein the second level (see figure 6 above) corresponds to a second digital state (para.(34) discloses: he one time programmable memory differential current sense amplifier 103 will convert the differential current into a full digital “1” or full digital “O” level (e.g., a Vdd level “1” or a ground level “0”) and latch an amplified differential voltage through the first latch 96 and the second latch 97 to provide a full digital output level. After a result is latched, an ISOLATEP signal will be set, which will isolate the one time programmable memory twin cell 102 from the one time programmable memory differential current sense amplifier 103. By isolating these circuits, it is possible to prevent changes to a value of the latched result).
Regarding claim 9, Anand et al. disclose the limitation of claim 7.
Anand et al. further discloses wherein the programming the second data node (second node, figure 5 above) comprises setting a second node voltage (figure 5 above) at the second data node to the second level (figure 6 above) based on a second voltage across a drain and a source of the second charge trap transistor (72, figure 5).
Allowable Subject Matter
Claim 6 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 6, the prior art made of record and considered pertinent to the applicant’s disclosure does not teach the claim limitation of reprogramming, the second data node to the second level, in response to an interruption of the second voltage at the second charge trap transistor caused by the decreasing and the increasing in combination with the other limitations thereof as is recited in the claim.
Claims 10-29 are allowed.
Regarding independent claim 10, the prior does not teach or suggest the claimed invention having “a first charge trap transistor; a second charge trap transistor; and first and second [[a]] memory arrays operatively coupled to the first charge trap transistor and the second charge trap transistor, respectively”, in combination of other limitations thereof as recited in the claim.
Regarding claims 11-26, the claims have been found allowable due to their dependencies to claim 10 above.
Regarding independent claim 27, the prior does not teach or suggest the claimed invention having “wherein each of the charge trap transistor devices is operable to :program, to a first level above a threshold, a plurality of the data nodes operatively coupled to corresponding ones of the charge trap transistors; decrease, below the threshold, a plurality of voltages at the charge trap transistors; increase, above the threshold, the voltages at the charge trap transistors; and reprogram, in response to an interruption of the voltages at the charge trap transistors, the data nodes to the first level”, in combination of other limitations thereof as recited in the claim.
Regarding claims 28 and 29, the claims have been found allowable due to their dependencies to claim 27 above.
Conclusion
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/MINH D DINH/ Examiner, Art Unit 2827
/HUAN HOANG/ Primary Examiner, Art Unit 2154