Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Election/Restrictions
Applicant's election with traverse of Figs. 7A-9, 13-18 and claims 1-7, 18 and 22 in the reply filed on 5/8/2026 is acknowledged. The traversal is on the ground(s) that all the claims are sufficiently related to each other such that an undue burden would not be placed and that the election is burdensome for the Applicant and the public. Examiner respectfully disagrees. This is not found persuasive because the different embodiments presented in the current application require different field of searches and corresponding consideration. The embodiments present multiple permutations of circuit structure that are not necessarily shared or repeatable with each other. In order to fully consider these embodiments and find pertinent prior arts for each embodiment and scenario, different search queries are necessary in case by case manner.
The requirement is still deemed proper and is therefore made FINAL.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 and 22 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhao et al (PGPUB 2019/0347987 A1).
As to claim 1, Zhao (Figs. 2 and 7) teaches, a pixel circuit (pixel circuit 31), comprising a first light emitting control circuit (first control transistor M11’), a light emitting element (light-emitting element 32), a driving circuit (driving transistor M22’) and a light emitting gating circuit (first processing circuit 41, second processing circuit 42, and second control transistor M33’)(¶ 84, 91);
the first light emitting control circuit is electrically connected to a first light emitting control terminal (i.e. gate electrode M11’), a first voltage terminal (i.e. upper terminal of M11’ in Fig. 7 that receives power signal PVDD) and a first terminal (i.e. upper terminal of M22’) of the driving circuit respectively, and is configured to control to connect the first voltage terminal and the first terminal of the driving circuit under the control of a first light emitting control signal (light emission control signal from EMIT(N)) provided by the first light emitting control terminal during a light emitting phase (i.e. time period T2, which has low level / enabling level of Emit1)(¶ 31),
a second terminal (i.e. lower terminal of M22’) of the driving circuit is electrically connected to a first electrode (i.e. upper terminal of light-emitting element 32 via M33’) of the light emitting element, and the driving circuit is configured to drive the light emitting element (¶ 89);
the light emitting gating circuit is configured to, under the control of a first control
signal (i.e. signal from first control signal terminal CS1) provided by a first control terminal(first control signal terminal CS1)(¶ 57), according to a light emitting data voltage (i.e. voltage from Emit) provided by a light emitting data voltage terminal (first control signal terminal Emit(N)), in the light emitting phase (¶ 32, 35), generate a current path (i.e. path from PVDD to PVEE by turning on M11’, M22’, M33’, and through light-emitting element 32) between the second terminal of the driving circuit and the light emitting element under the control of a light emitting control voltage (second light emission control signal Emit2) provided by a light emitting control voltage terminal (i.e. output of second processing circuit 42), to control the driving circuit (i.e. drives M22’ by controlling M11’) to control the light emitting element to emit light, or, to generate the current path between the second terminal of the driving circuit and the light emitting element in the light emitting phase, to control the driving circuit to control the light emitting element to emit light (i.e. controls M22’ by turning M11’ and M33’ on or off)(¶ 35).
As to claim 22, Zhao (Figs. 2 and 7) teaches, a display device (display device) comprising the pixel circuit according to any one of claims 1-18 (Fig. 13).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhao et al in view of Yue et al (PGPUB 2021/0233461 A1).
As to claim 18, Zhao teaches the pixel circuit according to any one of claims 1 to 12, but does not specifically teach a micro light emitting diode or a miniature light emitting diode.
Yue (Fig. 4) teaches wherein the light emitting element is a micro light emitting diode or a miniature light emitting diode (microLED, ¶ 22 and claim 14).
It would have been obvious to a person of ordinary skilled in the art before the effective filing date of the claimed invention to incorporate Cong’s diode display into Zhao’s display, so as to alleviate display defects caused by light-emitting diode whose characteristics are easily drifted with current density and improve display performance of related display products (¶ 218).
Allowable Subject Matter
Claim 2 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Applicant’s claimed invention regard a LED pixel circuit that comprises a first gating control circuit that generates the control signal for one of the light emitting control transistor in the pixel circuit. Further, the basis of the LED pixel circuit involves two light emitting control transistors. One of the light emitting control transistor is connected to one of the source or drain terminal of the driving transistor and the high power voltage. The other one of the light emitting control transistor is connected to the other of the source or the drain terminal of the driving transistor and the anode of the light emitting diode.
Regarding this structure, claim 2 recites the following limitations, “
wherein the light emitting gating circuit comprises a second light emitting control circuit and a first gating control circuit; the first gating control circuit is electrically connected to the first control terminal, the light emitting data voltage terminal, a gating control terminal, a second light emitting control terminal, the light emitting control voltage terminal and a first light emitting control terminal, is configured to write the light emitting data voltage provided by the light emitting data voltage terminal into the gating control terminal under the control of the first control signal, and under the control of a potential of the gating control terminal, control to connect the second light emitting control terminal and the light emitting control voltage terminal, or control to connect the second light emitting control terminal and the first light emitting control terminal; the second light emitting control circuit is electrically connected to the second light emitting control terminal, the second terminal of the driving circuit and the first electrode of the light emitting element respectively, and is configured to control to connect the second terminal of the driving circuit and the first electrode of the light emitting element under the control of a potential of the second light emitting control terminal; the second electrode of the light emitting element is electrically connected to a
second voltage terminal”.
Examiner conducted a search to find the prior arts that would teach these limitations alone or in combination but could not find them. In view of Fig. 7A of Applicant’s disclosure, the structure of the light emitting gating circuit includes the first gating control circuit. The first gating control circuit specifically generates the second light emitting control signal EM2 using the light emitting data voltage terminal DT and the first light emitting control signal EM1, which controls the other light emitting control transistor. Further, the underlined claim limitation describes the operation of first gating control circuit 122 as shown in Fig. 7A. None of these features were found in the prior arts and related references from the search. Followings are the most relevant prior arts that teaches the circuit for controlling the light emitting control transistor of a pixel. However, in many of the prior arts, the circuit is external to the pixel circuit, which is contrary to Applicant’s claimed invention. In other words, none of the prior arts teach these discussed limitations in claim 2 while requiring the circuit to be comprised by the pixel circuit itself.
Yue et al (PGPUB 2021/0233461 A1) – Yue teaches transistors T5, T6, T8 that control the operation of light emitting control transistors within a pixel.
Xuan (PGPUB 2021/0158757 A1) – Xuan teaches duration data voltage writing circuit 142 that controls switch control circuit 141, which operates similar to a light emitting control transistor as shown in Figs. 3-5.
Yue et al (PGPUB 2019/0005878 A1) – Yue teaches the short circuit control circuit 3 that controls the transistor Q3 as shown in Fig. 3.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SANGHYUK PARK whose telephone number is (571)270-7359. The examiner can normally be reached on 10:00AM - 6:00 M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chanh Nguyen can be reached on ((571) 272-7772. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/SANGHYUK PARK/Primary Examiner, Art Unit 2623
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