Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. DETAILED ACTION 2. This action is in response to the original filing on 08/07/2023 . Claims 1-10 are pending and have been considered below. Information Disclosure Statement 3. The information disclosure statement (IDS (s) ) submitted on 08/07/2023 is /are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Rejections – 35 USC § 103 4 . The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made . 5 . Claims 1, 6, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (U.S. Patent Application Pub. No. US 2 0210319293 A1) in view of Lin et al. (U.S. Patent Application Pub. No. US 20180174053 A1) , in view of Sinyavskiy et al. (U.S. Patent Application Pub. No. US 20130325768 A1) , and further in view of Cruz-Albrecht et al. (U.S. Patent Pub. No. US 8977578 B 1) . Claim 1: Lee teaches a neuromorphic circuit implementing a pulsed neural network, the neuromorphic circuit (i.e. each of the neuron circuits 240 may output a spike when an accumulated value of the received computation results is greater than or equal to a predetermined threshold. The spikes output from the neuron circuits 240 may correspond to activations input to axons of the next stage through the network 260; para. [0036]) comprising: synapses produced by a set of memristors (i.e. Each of the synaptic circuits 220 may be a circuit that simulates a synapse between neurons. The synaptic circuits 220 may store weights corresponding to the connection strengths between neurons. Each of the synaptic circuits 220 may include a memory element for storing the weight or may be connected to a memory element already having the weight. In an example embodiment, such a memory element may be or include a memristor; para. [0035]) arranged in the form of an array network (i.e. The neuromorphic device 200 may include first-direction lines (or axon lines) extending in a first direction from the axon circuits 210 and second-direction lines (or dendrite lines) extending in a second direction and corresponding to the dendrite circuits 230. The first direction lines and the second direction lines intersect each other, and the synaptic circuits 220 may be disposed on intersections of the first-direction lines and the second-direction lines; para. [0033]) , each synapse having a value (i.e. Each of the synaptic circuits 220 may be implemented with a memory element such as the memristor element 250. The memristor element 250 may store weights therein through a memristor-based design and perform multiplication (i.e., an AND operation) at the intersection; para. [0038]) ; neurons, each neuron firing spikes at a rate (i.e. each of the neuron circuits 240 may output a spike when an accumulated value of the received computation results is greater than or equal to a predetermined threshold; para. [0036]) , each neuron being connected to one or to a plurality of neurons, via one of said synapses (i.e. The weight is a parameter used to calculate the activation in each neuron, and may be a value assigned to a connection relationship between neurons. The weight may be stored in a synapse that connects neurons; para. [0029]) , the neurons being arranged in layers of successive neurons, the layers of neurons comprising: an input layer; at least one hidden layer; and an output layer (i.e. The artificial neural network may be a deep neural network (DNN) including two or more hidden layers or an n-layer neural network. For example, as illustrated in FIG. 1, the artificial neural network may be the DNN including an input layer Layer 1, two hidden layers Layer 2 and Layer 3, and an output layer Layer 4; para. [0024]) ; said synapses being for the neurons of the at least one hidden layer and of the output layer (i.e. The neuron circuits 240 may be located at a rear end with respect to the synaptic circuits 220, and thus may be referred to as post-synaptic neuron circuits. The axon circuits 210 may be located at a front end with respect to the synaptic circuits 220, and thus may be referred to as pre-synaptic neuron circuits; para. [0037]) ; and a training module of the neural network, the training module comprising, for at least one synapse connecting a first neuron to a second neuron (i.e. when learning of the next artificial neural network is required, the value stored in the latch circuit 750 may be input to the synaptic array 720 and the next artificial neural network computation may be performed; para. [0078]) . Lee does not explicitly teach firing spike s at a variable rate; synapses being bidirectional; for the first neuron and the second neuron, an estimation unit obtaining an estimation of the time derivative of the fired spike rate of the first neuron and of the second neuron; an interconnection between the at least one bidirectional synapse and each neuron, the interconnection having at least two positions; and a controller sending a control signal to said interconnection when the first neuron has fired a spike, the control signal modifying the position of the said interconnection so that said estimation unit of the second neuron is connected to the at least one bidirectional synapse. However, Lin teaches each neuron firing spikes at a variable rate (i.e. An input provided to the M neurons may be represented as a vector I 1 , which may produce spikes (fed recurrently to the neurons in the network) firing at respective spiking rates (represented by an M×1 vector a 1 ); para. [0052]) ; synapses being bidirectional (i.e. synapses may be defined which connect the neuron bi-directionally with other neurons (e.g., between neurons 315, 320) … a recurrently connected SNN may provide a layer of neurons where each neuron layer connects to the other bi-directionally (i.e., by two synapses each, one synapse in each direction); para. [0042, 0056]) ; an interconnection between the at least one bidirectional synapse and each neuron, the interconnection having at least two positions (i.e. where the instructions are further to determine a first steady state condition of the SNN with the respective input vector provided and the third subset of synapses disabled and determine a second steady state condition of the SNN with the third subset of synapses enabled and based on the respective input vector, where the first steady state spiking rates are determined in association with the first steady state condition, and the second steady state spiking rates are determined in association with the second steady state condition; para. [0109]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Lee to include the feature of Lin . One would have been motivated to make this modification because it improves computational capability, stability, and programmability of neuromorphic networks. However, Sinyavskiy teaches an estimation unit obtaining an estimation of the time derivative of the fired spike rate of the first neuron and of the second neuron (i.e. to adjust a learning parameter associated with a computerized spiking neuron configured to produce output spike signal y consistent with (i) an input spike signal x, and (ii) a learning task, the instructions configured to, when executed construct time derivative representation of a trace S of a neuron state, based at least in part on the input spike signal x and a state parameter q; obtain a realization of the trace S, based at least in part in integrating the time derivative representation; and determine adjustment dw of the parameter w, based at least in part on the trace S; and the adjustment dw may be configured to transition the neuron state towards a target state, the target state associated with the neuron generating the output spike signal y; para. [0041]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Lee and Lin to include the feature of Sinyavskiy . One would have been motivated to make this modification because it improves training of spiking networks implemented in neuromorphic hardware. However, Cruz-Albrecht teaches a controller sending a control signal to said interconnection when the first neuron has fired a spike, the control signal modifying the position of the said interconnection (i.e. According to various examples, the plurality of switches 114 in FIG. 2 provide selectable pathways or connections between nodes 112 within the neural fabric 110, as noted above. In particular, closing one or more switches 114 of the neural fabric 110 establishes a link between an output of a neuron in a first node 112 and an input of a second node 112. The input may be an input of a synapse of the second node 112, for example. In various examples, a switch 114 of the plurality may be realized using any of a variety of technologies. For example, the switch 114 may comprise metal-oxide semiconductor (MOS) transistors that are configured to function as switches; col. 10, lines 22-34) so that said estimation unit of the second neuron is connected to the at least one synapse (i.e. the STDP learning module comprises a first gated signal path to integrate the pre-synaptic spike signal using a first leaky integrator, and comprises a second gated signal path to integrate the post-synaptic spike signal using a second leaky integrator. The STDP learning module further comprises an output integrator to integrate a difference between an output signal of the first gated signal path and an output signal of the second gated signal path. The integrated difference is the weight signal W(t). The first gated signal path is gated according to the post-synaptic spike signal and the second gated signal path is gated according to the pre-synaptic spike signal, according to various examples; col. 10, lines 10-21) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Lee, Lin, and Sinyavskiy to include the feature of Cruz-Albrecht . One would have been motivated to make this modification because it reduces scalability and routing complexity. Claim 6 : Lee, Lin, Sinyavski y , and Cruz -Albrecht teach t he neuromorphic circuit according to claim 1 . Lee does not explicitly teach wherein said interconnection comprises a sub-circuit for each neuron to which the at least one bidirectional synapse is connected, each sub-circuit comprising two switches. However, Lin further teaches the at least one bidirectional synapse (i.e. synapses may be defined which connect the neuron bi-directionally with other neurons (e.g., between neurons 315, 320) to create a feedback loop, among other examples … a recurrently connected SNN may provide a layer of neurons where each neuron layer connects to the other bi-directionally (i.e., by two synapses each, one synapse in each direction); para. [0042, 0056]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Lee, Sinyavski y , and Cruz -Albrecht to include the feature of Lin . One would have been motivated to make this modification because it improves computational capability, stability, and programmability of neuromorphic networks. However, Cruz-Albrecht further teaches wherein said interconnection comprises a sub-circuit for each neuron to which the at least one synapse is connected (i.e. FIG. 3 illustrates a node 210 of the neural fabric 200. The node 210 comprises a neuron 212 surrounded by a plurality of synapses 214. Specifically as illustrated, the neuron 212 of the node 210 is surrounded by four synapses 214, by way of example and not limitation … Further illustrated in FIG. 3 is a plurality of switches 220. The plurality of switches 220 may be substantially similar to the plurality of switches 114 of the neural fabric 110, described above with respect to the STM neuromorphic network 100; col. 10, lines 39-65) , each sub-circuit comprising two switches (i.e. the plurality of switches 220 may comprise a node input switch 222 configured to selectively connect an adjacent signal path 230 to an input of the node 210. The signal path 230 may be a wire, a transmission line or a member of a signal transmission channel, according to various examples. As illustrated, the node 210 has four node input switches 222, one for each of four inputs to the node 210, for example. Selective activation of the node input switch 222′ facilitates routing a signal 240 on the adjacent signal path 230 into the input of the node 210 and to a synapse 214 of the node 210. The signal 240 may be an output signal produced by a neuron 212 of the node 210; col. 10, lines 60-67) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Lee, Lin, and Sinyavskiy to include the feature of Cruz-Albrecht . One would have been motivated to make this modification because it reduces scalability and routing complexity. Claim 10 is similar in scope to Claim 1 and is rejected under a similar rationale. 6 . Claims 2 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Lin, Sinyavskiy , Cruz-Albrecht , and further in view of Patwardhan et al. (U.S. Patent Application Pub. No. US 20150278684 A1) . Claim 2 : Lee, Lin, Sinyavski y , and Cruz -Albrecht teach t he neuromorphic circuit according to claim 1 . Lee does not explicitly teach wherein said controller synchronizes the first and second neurons so that the first and second neurons issue control signals modifying the value of the at least one bidirectional synapse according to the estimation of the time derivative of the fired spike rate of the second neuron. However, Lin further teaches the first and second neurons so that the first and second neurons issue control signals modifying the value of the at least one bidirectional synapse (i.e. synapses may be defined which connect the neuron bi-directionally with other neurons (e.g., between neurons 315, 320) to create a feedback loop, among other examples … a recurrently connected SNN may provide a layer of neurons where each neuron layer connects to the other bi-directionally (i.e., by two synapses each, one synapse in each direction); para. [0042, 0056]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the invention of Lee to include the feature of Lin . One would have been motivated to make this modification because it improves computational capability, stability, and programmability of neuromorphic networks. However, Sinyavskiy further teaches the estimation of the time derivative of the fired spike rate of the second neuron (i.e. to adjust a learning parameter associated with a computerized spiking neuron configured to produce output spike signal y consistent with (i) an input spike signal x, and (ii) a learning task, the instructions configured to, when executed construct time derivative representation of a trace S of a neuron state, based at least in part on the input spike signal x and a state parameter q; obtain a realization of the trace S, based at least in part in integrating the time derivative representation; and determine adjustment dw of the parameter w, based at least in part on the trace S; and the adjustment dw may be configured to transition the neuron state towards a target state, the target state associated with the neuron generating the output spike signal y; para. [0041]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Lee, Lin, and Cruz-Albrecht to include the feature of Sinyavskiy . One would have been motivated to make this modification because it improves training of spiking networks implemented in neuromorphic hardware. However, Patwardhan teaches wherein said controller synchronizes the first and second neurons so that the first and second neurons issue control signals modifying the value of the at least one synapse (i.e. each processing node implementing a neuron model, communicating via the exchange of spike packets carrying information regarding spike information for artificial neurons and providing a mechanism for maintaining relative spike-timing between the processing nodes … it is important to ensure that all nodes are synchronized, for example, running in lock-step mode to maintain relative spike-timing. Because the time required for each node to process a time-step may vary (e.g. based on factors like firing rate), it may be desirable to have a mechanism that helps ensure lock-step operation; para. [0007, 0077-0080]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Lee, Lin, Sinyavskiy , and Cruz-Albrecht to include the feature of Patwardhan . One would have been motivated to make this modification because it improves neuron timing and reliable application of control signals to modify synaptic values. Claim 5 : Lee, Lin, Sinyavski y , Cruz -Albrecht , and Patwardhan teach t he neuromorphic circuit according to claim 2. Lee does not explicitly teach wherein said controller controls both neurons so that both control signals are issued simultaneously. However, Patwardhan further teaches wherein said controller controls both neurons so that both control signals are issued simultaneously (i.e. each processing node implementing a neuron model, communicating via the exchange of spike packets carrying information regarding spike information for artificial neurons and providing a mechanism for maintaining relative spike-timing between the processing nodes … it is important to ensure that all nodes are synchronized, for example, running in lock-step mode to maintain relative spike-timing. Because the time required for each node to process a time-step may vary (e.g. based on factors like firing rate), it may be desirable to have a mechanism that helps ensure lock-step operation; para. [0007, 0077-0080]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Lee, Lin, Sinyavskiy , and Cruz-Albrecht to include the feature of Patwardhan . One would have been motivated to make this modification because it improves neuron timing and reliable application of control signals to modify synaptic values. 7. Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Lin, Sinyavskiy , Cruz-Albrecht , Patwardhan , and further in view of Nishitani et al. (U.S. Patent Application Pub. No. US 20150269483 A1) . Claim 4 : Lee, Lin, Sinyavski y , Cruz -Albrecht , and Patwardhan teach t he neuromorphic circuit according to claim 2. Lee does not explicitly teach wherein the second neuron issues as a control signal, a pulse proportional to the estimation of the time derivative of the spike rate obtained by said estimation unit. However, Sinyavskiy further teaches wherein the second neuron issues as a control signal, to the estimation of the time derivative of the spike rate obtained by said estimation unit (i.e. to adjust a learning parameter associated with a computerized spiking neuron configured to produce output spike signal y consistent with (i) an input spike signal x, and (ii) a learning task, the instructions configured to, when executed construct time derivative representation of a trace S of a neuron state, based at least in part on the input spike signal x and a state parameter q; obtain a realization of the trace S, based at least in part in integrating the time derivative representation; and determine adjustment dw of the parameter w, based at least in part on the trace S; and the adjustment dw may be configured to transition the neuron state towards a target state, the target state associated with the neuron generating the output spike signal y; para. [0041]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Lee, Lin , Cruz -Albrecht , and Patwardhan to include the feature of Sinyavskiy . One would have been motivated to make this modification because it improves training of spiking networks implemented in neuromorphic hardware. However, Nishitani teaches a pulse proportional to the estimation (i.e. The error voltage signal V error is fed back to the error input terminal 52 of the neural network circuit element 40 included in the output layer 4. The error voltage signal V error input to the error input terminal 52 serves as a multiplier coefficient of the analog multiplier circuit 333 of the neuron circuit 30 and is multiplied by the second waveform. As a result, the weight change pulse voltage signal V POST1 generated by the neuron circuit 30 of the neural network circuit element 40 included in the output layer 4 becomes a signal having an amplitude that is proportional to the amplitude of the error voltage signal; para. [0157]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Lee, Lin, Sinyavskiy , Cruz-Albrecht , and Patwardhan to include the feature of Nishitani . One would have been motivated to make this modification because it a way to drive synaptic modification without additional complex paths. 8 . Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Lin, Sinyavskiy , Cruz-Albrecht , and further in view of Cruz-Albrecht et al. (U.S. Patent Application Pub. No. US 20200356344 A1) . Claim 9 : Lee, Lin, Sinyavski y , and Cruz -Albrecht teach t he neuromorphic circuit according to claim 1 . Lee does not explicitly teach wherein said neurons are pulse relaxation oscillators. However, Cruz-Albrecht ‘344 teaches wherein said neurons are pulse relaxation oscillators (i.e. The first and second voltage sources (36, 42) are arranged to bring the first and second NDR devices (X1, X2) close to their respective Mott Insulator-to-Metal Transition; and the voltage biases can be adjusted to set desired levels of voltage or current threshold for the neuron action potential generation (spike firing) and desired signal gains. The first load resistor, the first NDR device, the first voltage source and the first grounded capacitor are arranged to form a first relaxation oscillator; and the second load resistor, the second NDR device, the second voltage source and the second grounded capacitor are arranged to form a second relaxation oscillator; para. [0053, 0063]) . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the combination of Lee, Lin, Sinyavskiy , Cruz-Albrecht , and Patwardhan to include the feature of Cruz-Albrecht ‘344 . One would have been motivated to make this modification because it a way to simplify hardware and improve suitability for dense neuromorphic integration. Allowable Subject Matter Claims 3, 7, and 8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure. Park et al. (Pub. No. US 20220149200 A1) , the neuromorphic system according to an embodiment of the present invention forms a cross-bar array structure to realize a neural network structure composed of neurons according to an embodiment of the present invention and connection between the neurons, thereby being capable of realizing artificial intelligence hardware with improved efficiency in terms of data processing, transmission speed, and energy consumption due to operation through interaction between the neurons according to an embodiment of the present invention. It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck , 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson , 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)). Any inquiry concerning this communication or earlier communications from the examiner should be directed to TAN TRAN whose telephone number is (303)297-4266. The examiner can normally be reached on Monday - Thursday - 8:0 0 am - 5 :00 pm MT . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccess ful, the examiner’s supervisor, Matt Ell can be reached on 571-270-3264 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TAN H TRAN/ Primary Examiner, Art Unit 2141