Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
2. Claims 1-8 and 12-13 are pending in Instant Application.
Election/Restrictions
Applicant’s election without traverse of Group I (claims 1-8 and 12-13) in the reply filed on 10/27/2025 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/07/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Priority
Examiner acknowledges that this application Claims priority to Chinese patent application No. 202111637854.7, filed to the CNIPA on December 30, 2021 and entitled "Method for Operation on a Proof of Work, Chip of Proof of Work and Upper Computer”, and the entire disclosure of which is hereby incorporated by reference.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation(s) for example are: “the central control unit is configured to receive direct acyclic graph (DAG) data”, “the unit for processing an external DAG is configured to store the DAG data”, “the calculating unit is configured to perform an operation” in claim 1. However, based on Fig. 1, it appears they have structure are they are part of upper computer.
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Note: claim 7 contains “feed back” as two words. Correction is requested.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 4-8, and 12-13 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by
CN108536642A issued to Ying et al. (Ying) (Applicant IDS).
As per claim 1, Ying teaches a chip of proof of work, comprising a processor and a memory, wherein the memory stores processor-executable programs (Ying: Abstract - the big data operation acceleration system and the chip have the advantages that each core can gain high-capacity memory by reading the storage units connected with the core, and the storage units connected with the other cores), and the programs comprise a central control unit, wherein the central control unit is configured to receive direct acyclic graph (DAG) data sent by an upper computer (Ying: Pg 11, 1st Para - The chip is applied to the field of encrypted digital currency such as Ethereum. The UART control unit (40) stores the block information sent by the external host (equivalent to a hypervisor) into the DDR memory cells (storage units) DDR0...DDR7 (equivalent to a central control unit for receiving directed acyclic graph DAG data sent by the hypervisor)); a storage unit, the storage unit is configured to store the DAG data (Ying: Pg. 11, 1st Para - the data generation unit (406) generates the DAG in the Ethereum algorithm, writes the DAG into storage units DDR0 ... DDR7 (equivalent to storage units for holding DAG data)); a unit for processing an external DAG (Ying: Pg. 11, 1st Para - DDR control units in the kernel for accessing data (equivalent to external DAG processing units for saving said DAG data to storage units)); and a calculating unit, the unit for processing an external DAG is configured to store the DAG data into the storage unit; and the calculating unit is configured to perform an operation on a proof of work according to the stored DAG data (Ying: Pg. 11, 1st Para - and sending the data to a computation unit for proof operation (a proof-of-work operation) (equivalent to a computation unit configured to perform a proof-of-work operation based on said saved DAG data), which feeds back the result of the computation to an external host via the UART control unit (40) (said chip is equivalent to a proof-of-work chip)).
As per claim 2, Ying teaches the chip of proof of work according to claim 1, wherein the programs further comprise a unit for selecting a DAG generation mode, wherein the central control unit is further configured to receive a first command sent by the upper computer and schedule the unit for selecting a DAG generation mode (Ying: Pg. 10, 3rd Para - an external host can initialize configuration DDR parameters through a UART control unit to unify addressing multiple DDR particles. The external host sends the addressing commands through the UART interface (401), the first AXI (Advanced eXtensible Interface) unit (402), the second AXI unit (403) and the AHB interface (404) to the DDR storage units DDR0 ... DDR7, which perform address allocation in accordance with the addressing commands); and the unit for selecting a DAG generation mode is configured to open a channel between the central control unit and the unit for processing an external DAG according to scheduling of the central control unit, enabling the unit for processing an external DAG to acquire the DAG data received by the central control unit (Ying: Pg. 10, 4th Para - an external host can write data to DDR storage units DDR0 ... DDR7 through the UART control unit; the external host sends the data and its stored address through the UART interface (401), the first AXI unit (402) and the data proofreading unit (405) to the DDR storage units DDR0 ... DDR7, which store in accordance with the data and its stored address. The first AXI unit (402) receives the data sent by the UART interface (401) over the MO interface and over the SO ... S7 interfaces to the data proofreading unit ( 405), which sends the data to the connected DDR storage units. The external host can also read the data stored in DDR storage units DDR0 ... DDR7 over the reverse link (basically the UART control unit addresses and schedules storage units and transmits data that the UART control unit accepts from outside through the UART interface (401), the first AXI unit (402), and the data proofreading unit (405)).
As per claim 4, Ying teaches the chip of proof of work according to claim 1, wherein the programs further comprise a storage data access selection interface unit, wherein: the central control unit is further configured to receive a second command sent by the upper computer and schedule the storage data access selection interface unit (Ying: Pg. 10, 3rd Para - an external host can initialize configuration DDR parameters through a UART control unit to unify addressing multiple DDR particles. The external host sends the addressing commands through the UART interface (401), the first AXI (Advanced eXtensible Interface) unit (402), the second AXI unit (403) and the AHB interface (404) to the DDR storage units DDR0 ... DDR7, which perform address allocation in accordance with the addressing commands); the storage data access selection interface unit is connected with the storage unit and is configured to provide an access authority of the storage unit to the calculating unit according to scheduling of the central control unit (Ying: Pg. 10, 4th Para - an external host can write data to DDR storage units DDR0 ... DDR7 through the UART control unit; the external host sends the data and its stored address through the UART interface (401), the first AXI unit (402) and the data proofreading unit (405) to the DDR storage units DDR0 ... DDR7, which store in accordance with the data and its stored address. The external host can also read the data stored in DDR storage units DDR0 ... DDR7 over the reverse link (basically the UART control unit addresses and schedules storage units and transmits data that the UART control unit accepts from outside through the UART interface (401), the first AXI unit (402), and the data proofreading unit (405)).
As per claim 5, Ying teaches the chip of proof of work according to claim 2, wherein that the unit for selecting a DAG generation mode is configured to open a channel between the central control unit and the unit for processing an external DAG, comprises: the unit for selecting a DAG generation mode is configured to open a part of an address space in the central control unit to the unit for processing an external DAG, wherein the opened part of the address space comprises one or more pieces of following information: write data, configured for storing the DAG data; a write address, configured for storing an address of the DAG data; a write signal, which is configured to a value indicating that the DAG data has been written or a value indicating that the DAG data has not been written; and a whether-or-not writable signal, which is configured to a value indicating that DAG data is allowed to be writable or a value indicating that DAG data is not allowed to be writable; wherein values of the write data, the write address and the write signal are set by the upper computer, and a value of the whether-or-not writable signal is set by the unit for processing an external DAG (Ying: Pg. 8, 1st Para, Pg. 10, 4th Para - the computing unit (120 ... 127) may also send a write data command to the storage control unit (110 ... 117) connected thereto, the storage control unit (110 ... 117) according to the command will be in the computing unit (120 ... 127), also the external host can write data to the DDR memory cells DDR0...DDR7 through the UART control unit; the external host sends the data and its stored address through the UART interface (401), the first AXI unit (402), and the data collation unit (405) and Ying: Pg. 2, 4th Para - teaches the storage control unit is configured to control a data read and write operation of the storage control unit to connect at least one storage unit (basically the data command is the signal that will determine whether something is needed to be written or not)).
As per claim 6, Ying teaches the chip of proof of work according to claim 5, wherein the address space comprises following information: write data, a write address, a write signal, and a whether-or-not writable signal; that the unit for processing an external DAG is configured to store the DAG data into the storage unit, comprises: the unit for processing an external DAG is configured to, when determining that the DAG data has been written according to the write signal, set the whether-or- not writable signal to a value indicating that DAG data is not allowed to be writable, write DAG data in the address space in the central control unit and an address of the DAG data into the storage unit, and after the writing, set the whether-or-not writable signal to a value indicating that DAG data is allowed to be writable (Ying: Pg. 8, 1st Para, Pg. 10, 4th Para - the computing unit (120 ... 127) may also send a write data command to the storage control unit (110 ... 117) connected thereto, the storage control unit (110 ... 117) according to the command will be in the computing unit (120 ... 127), also the external host can write data to the DDR memory cells DDR0...DDR7 through the UART control unit; the external host sends the data and its stored address through the UART interface (401), the first AXI unit (402), and the data collation unit (405) and Ying: Pg. 2, 4th Para - teaches the storage control unit is configured to control a data read and write operation of the storage control unit to connect at least one storage unit (basically the data command is the signal that will determine whether something is needed to be written or not)).
As per claim 7, Ying teaches the chip of proof of work according to claim 1, wherein the central control unit is further configured to, after the calculating unit calculates a result that conforms to a requirement, feed back the result to the upper computer (Ying: Pg. 11, 1st Para - the DDR control unit in the kernel is used to access the data, and the data is sent to the calculation unit for the workload proof operation, and the calculation unit feeds the calculation result to the external host through the UART control unit (40) (equivalent to the central control unit, further configured to feed back the result to the hypervisor after the compute unit has computed the result in compliance)).
As per claim 8, Ying teaches a method for operation on a proof of work, applied to a chip of proof of work according to claim 1, the method comprising: receiving direct acyclic graph (DAG) data sent by an upper computer (Ying: Pg 11, 1st Para - The chip is applied to the field of encrypted digital currency such as Ethereum. The UART control unit (40) stores the block information sent by the external host (equivalent to a hypervisor) into the DDR memory cells (storage units) DDR0...DDR7 (equivalent to a central control unit for receiving directed acyclic graph DAG data sent by the hypervisor)); storing the DAG data into a storage unit (Ying: Pg. 11, 1st Para - the data generation unit (406) generates the DAG in the Ethereum algorithm, writes the DAG into storage units DDR0 ... DDR7 (equivalent to storage units for holding DAG data)); and performing an operation on a proof of work according to the stored DAG data (Ying: Pg. 11, 1st Para - and sending the data to a computation unit for proof operation (a proof-of-work operation) (equivalent to a computation unit configured to perform a proof-of-work operation based on said saved DAG data), which feeds back the result of the computation to an external host via the UART control unit (40) (said chip is equivalent to a proof-of-work chip)).
As per claim 12, Ying teaches a computer program product, comprising computer programs, wherein when the computer programs are executed by a processor, the computer programs perform the method for operation on a proof of work of claim 8 (Ying: Pg. 11, 1st Para - and sending the data to a computation unit for proof operation (a proof-of-work operation) (equivalent to a computation unit configured to perform a proof-of-work operation based on said saved DAG data), which feeds back the result of the computation to an external host via the UART control unit (40) (said chip is equivalent to a proof-of-work chip) while Ying also teaches “computer program product" intended to encompass a computer program (Ying: Col. 12, 1st Para)).
As per claim 13, Ying teaches a non-transitory computer readable storage medium storing computer programs, which when executed by a processor, perform the method for operation on a proof of work of claim 8 (Ying: Pg. 11, 1st Para - and sending the data to a computation unit for proof operation (a proof-of-work operation) (equivalent to a computation unit configured to perform a proof-of-work operation based on said saved DAG data), which feeds back the result of the computation to an external host via the UART control unit (40) (said chip is equivalent to a proof-of-work chip) while Ying also teaches "computer program product" intended to encompass a computer program that is permanently or temporarily stored on a non-transitory medium that can be used by any computer (Ying: Col. 12, 1st Para)).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over CN108536642A issued to Ying et al. (Ying) (Applicant IDS) in view CN113485949A issued to Nan et al. (Nan).
As per claim 3, Ying teaches the chip of proof of work according to claim 2 however does not explicitly teach wherein the programs further comprise a unit for generating an internal Cache and a unit for generating an internal DAG, wherein: the central control unit is further configured to receive block information sent by the upper computer and schedule the unit for selecting a DAG generation mode; the unit for selecting a DAG generation mode is further configured to open a channel between the central control unit and the unit for generating an internal Cache according to scheduling of the central control unit, enabling the unit for generating an internal Cache to acquire the block information received by the central control unit; the unit for generating an internal Cache is configured to generate Cache data according to the received block information and store the Cache data into the storage unit; the storage unit is further configured to store the Cache data; and the unit for generating an internal DAG is configured to perform a calculation of DAG data according to the Cache data stored in the storage unit, and store the calculated DAG data obtained into the storage unit.
Nan however explicitly teaches wherein the programs further comprise a unit for generating an internal Cache and a unit for generating an internal DAG, wherein: the central control unit is further configured to receive block information sent by the upper computer and schedule the unit for selecting a DAG generation mode; the unit for selecting a DAG generation mode is further configured to open a channel between the central control unit and the unit for generating an internal Cache according to scheduling of the central control unit, enabling the unit for generating an internal Cache to acquire the block information received by the central control unit; the unit for generating an internal Cache is configured to generate Cache data according to the received block information and store the Cache data into the storage unit; the storage unit is further configured to store the Cache data; and the unit for generating an internal DAG is configured to perform a calculation of DAG data according to the Cache data stored in the storage unit, and store the calculated DAG data obtained into the storage unit (Nan: Pg. 12, last 3 Para - the processing module contains the determining submodule 321 is configured to determine whether DAG data exists at a data cache position corresponding to the second DAG request index in the history request record data; the first processing submodule 322 is configured to wait to return DAG data corresponding to the second DAG request index when no DAG data exists in the data cache location corresponding to the second DAG request index; the second processing submodule 323 is configured to, when DAG data exists at a data cache position corresponding to the second DAG request index, extract DAG data at the data cache position corresponding to the second DAG request index; Nan: Pg. 13, 8th Para - also teaches the first calculating module 31 and the processing module 32 are further configured to: continuously executing an updating process on the basis of the updated first parameter and DAG data corresponding to the updated first DAG request index, and then circularly updating the process until the updating times reach preset times and target DAG data is obtained).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the teaching of Ying in view of Nan to teach wherein the programs further comprise a unit for generating an internal Cache and a unit for generating an internal DAG, wherein: the central control unit is further configured to receive block information sent by the upper computer and schedule the unit for selecting a DAG generation mode; the unit for selecting a DAG generation mode is further configured to open a channel between the central control unit and the unit for generating an internal Cache according to scheduling of the central control unit, enabling the unit for generating an internal Cache to acquire the block information received by the central control unit; the unit for generating an internal Cache is configured to generate Cache data according to the received block information and store the Cache data into the storage unit; the storage unit is further configured to store the Cache data; and the unit for generating an internal DAG is configured to perform a calculation of DAG data according to the Cache data stored in the storage unit, and store the calculated DAG data obtained into the storage unit. One would be motivated to do so as the submodule under processing module will determine whether DAG data exists at a cache position by checking index of the data and when it is in a position to cache, it will cache and continuously update the process (Nan: Pg. 12, last 3 Para; Pg. 13, 8th Para).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SM AZIZUR RAHMAN whose telephone number is (571)270-7360. The examiner can normally be reached on M-F Telework;
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ali Shayanfar can be reached on 571-270-1050. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SM A RAHMAN/Primary Examiner, Art Unit 2434