No n-Final Rejection The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claims 1-12 are pending. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim s 1-4 and 12 are rejected under 35 U.S.C. 103 as being unpatentable over US 11,374,381 (“Kriman”) in view of US 5,448,114 (“Kondoh”), and further in view of JP 2005-216508 (“JP ‘508”) as evidenced by JP 2011-216475 (“JP ‘475”) . Regarding claim 1, K riman in Figs. 3A-G, see Fig. 3G for finished product, shows a n electronic device, comprising: a semiconductor ( silicon col. 4 line 1) substrate 22 ; a chip 20 +56 ; a bump 58 that connects a plurality of connection pads 44,32 provided on opposing main surfaces of the semiconductor substrate and the chip . Col. 6 lines 15-57. There is not shown a sidewall portion annularly surrounding a region where a plurality of the bumps is provided, and connects the semiconductor substrate and the chip. Kondoh Figs. 1-2 and discussion thereof starting at col. 9 line 1 shows a semiconductor device where chip 1 is bonded to substrate 2 via solder bumps 4. There is also a solder wall 3 that annularly surrounds the region where the other bumps are provided. It would have been obvious to a person of ordinary skill in the art to include such an annular wall as it isolates the inner region from outside air, which can be advantageous in some applications, as taught by Kondoh. Col. 9 lines 44-54. Including the wall also greatly increases the contact area, providing more heat dissipation, as taught by Kondoh. Col. 10 lines 1-15 It is also not disclosed that the sidewall is a porous metal layer. Note Kondoh uses solder as just mentioned, and Kriman also uses solder for the bumps. Col. 6 lines 20-23. Kondoh further teaches that the bumps 4 and the annular wall member being the same material is advantageous, as it avoids thermal expansion issues from using different materials. Col. 11 lines 11-15. JP ‘508 shows that it was known to attach a chip to a board by bumps, and often these bumps were made using plating. [0002]-[0003]. Note Kondoh’s bumps are formed by electro plating. Col. 11 lines 61-63. JP ‘508 teaches that instead bumps may be made of a porous metal material. It would have been obvious to a person of ordinary skill in the art to do so as it avoids impurities that reduce hardness and may be less complicated and expensive, as taught by JP ‘508. [0003]-[0004]. This also would have been a simple substitution of one known element for another to yield predictable results. MPEP 2143 I.B. The claim differs in the bump material, but that material is shown in JP ‘508. A person skilled in the art could have used the JP ‘508 material and the result would have been predictable because the bumps will still just do what they are supposed to do, they will just be a different material. See also MPEP 2144.07 (selecting known materials for their intended purpose is generally obvious; here the porous metal is known to be used for bumps). Regarding claim 2, as noted above the substrate is silicon, and the chip is GaAs (col. 3 line 65, col. 4 lines 51-52) , so they have a thermal expansion coefficient that differ by 0.1 ppm/°C. or more. Regarding claim 3 , in Kriman the substrate 22 is a driver die and the chip 20 is VCSELs, a semiconductor laser . Col. 3 line 62-col. 4 line 10. Regarding claims 4 and 12, the JP ‘508 porous metal layer contains metal particles having a particle diameter of 0.005 μm to 1.0 μm , and may be gold or silver with purity of 99.9 wt % or more. [0008]. Claims 5-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kriman , Kondoh, and JP ‘508 as evidenced by JP ‘475 as applied to claim 1, and further in view of JP H11-168116 (“JP ‘116”) . Regarding claim s 5 and 8 , a s described in JP ‘116 (paragraphs [0009] - [0019] and Figs. 1-3), in an elastic bump such as a porous structure (see [0010], bump made from similar process as JP ‘508) , it is a well-known technique to provide a metallic film on the side surface of the bump and between the bump and the connection pad . It would have been obvious to a person of ordinary skill in the art to do this as the porous material has more flexibility, mitigating thermal expansion problems, but the metal film layers maintain good connection, as taught by JP ‘116. [0015], [0004]. This also would have been a simple substitution of one known element for another to yield predictable results. MPEP 2143 I.B. The claim differs in the bump material, but that material is shown in JP ‘ 116 . A person skilled in the art could have used the JP ‘ 116 material and the result would have been predictable because the bumps will still just do what they are supposed to do, they will just be a different material. See also MPEP 2144.07 (selecting known materials for their intended purpose is generally obvious; here the porous metal is known to be used for bumps). Regarding Claims 6-7 and 9-10, JP ‘116 further describes that the thickness (1.3 to 3 micrometers) of the metal films (6, 7) is 5% or less of the thickness (100 to 300 micrometers) of the bump (paragraph [0011]). Again, Kondoh teaches that what applies to a bump applies also to the sidewall. Regarding Claim 11, JP ‘508 uses Au for the porous material ([0008]), and JP ‘116 also uses Au as the metal film ([0012]). Also, JP ‘116 uses Ni for each ([0010], [0012]). It would have been obvious to a person of ordinary skill in the art that they can be the same material, as each is recognized by the art as suitable for this use. See MPEP 2144.07. Double Patenting The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto- processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer . Claims 1-10 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over the claims as listed below of copending Application No. 18/006,004 in view of Kondoh . Claim 11 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over the claims as listed below of copending Application No. 18/006,004 in view of Kondoh , and further in view of JP ‘116 . Claim 11 is provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over the claims as listed below of copending Application No. 18/006,004 in view of Kondoh, and further in view of JP ‘ 508 . These rejections are provisional nonstatutory double patenting rejections as the claims are not yet patented. However, it is noted that the application is allowed and this rejection will change to a regular rejection upon the issuance of the patent. This application 18/006,004, claims filed 11/19/2025 1. An electronic device, comprising: a semiconductor substrate; a chip; a bump that connects a plurality of connection pads provided on opposing main surfaces of the semiconductor substrate and the chip; and 1. An electronic device, comprising: a semiconductor substrate; a chip … a bump that connects connection pads provided on opposing principal surfaces of the semiconductor substrate and the chip, wherein the bump includes: a porous metal layer a sidewall portion that includes a porous metal layer annularly surrounding a region where a plurality of the bumps is provided, and connects the semiconductor substrate and the chip. Th is is not claimed. Kondoh Figs. 1-2 and discussion thereof starting at col. 9 line 1 shows a semiconductor device where chip 1 is bonded to substrate 2 via solder bumps 4. There is also a solder wall 3 that annularly surrounds the region where the other bumps are provided. It would have been obvious to a person of ordinary skill in the art to include such an annular wall as it isolates the inner region from outside air, which can be advantageous in some applications, as taught by Kondoh. Col. 9 lines 44-54. Including the wall also greatly increases the contact area, providing more heat dissipation, as taught by Kondoh. Col. 10 lines 1-15 . Kondoh further teaches that the bumps 4 and the annular wall member being the same material is advantageous, as it avoids thermal expansion issues from using different materials. Col. 11 lines 11-15. Claim 1 already claims the bumps as a porous metal, so combined with Kondoh this teaches that the sidewall may also be the same porous metal material. 2. The electronic device according to claim 1, wherein the chip has a thermal expansion coefficient different from a thermal expansion coefficient of the semiconductor substrate by 0.1 ppm/° C. or more. 2. The electronic device according to claim 1, wherein the chip has a thermal expansion coefficient different from that of the semiconductor substrate by 0.1 ppm/°C or more. 3. The electronic device according to claim 1, wherein the chip is a semiconductor laser, and the semiconductor substrate includes a drive circuit that drives the semiconductor laser. 3. The electronic device according to claim 1, wherein the chip is a semiconductor laser, and the semiconductor substrate has a drive circuit that drives the semiconductor laser. 4. The electronic device according to claim 1, wherein the porous metal layer contains metal particles having a particle diameter of 0.005 μm to 1.0 μm. 4. The electronic device according to claim 1, wherein the porous metal layer contains metal particles having a particle diameter of 0.005 pm to 1.0 pm. Again, while this is claiming the bump material as opposed the sidewall, Kondoh teaches they should be the same material. 5. The electronic device according to claim 1, wherein the sidewall portion includes a metal film provided at least one of between the porous metal layer and the connection pad provided on the semiconductor substrate and between the porous metal layer and the connection pad provided on the chip, and on a side surface of the porous metal layer. 1… the bump includes: a porous metal layer; anda metal film provided on at least one of a portion between the connection pad provided on the semiconductor substrate and the porous metal layer and a portion between the connection pad provided on the chip and the porous metal layer, and on side surfaces of the porous metal layer. Again, while this is claiming the bump material as opposed the sidewall, Kondoh teaches they should be the same material. 6. The electronic device according to claim 5, wherein the metal film provided at least one of between the porous metal layer and the connection pad provided on the semiconductor substrate and between the porous metal layer and the connection pad provided on the chip has a proportion of a film thickness to a thickness of the sidewall portion in a direction orthogonal to the main surface of less than 10%. 5. The electronic device according to claim 1, wherein a ratio of a film thickness of the metal film provided between the connection pad and the porous metal layer to a thickness of the bump in the direction orthogonal to the principal surface is less than 10%. Again, while this is claiming the bump material as opposed the sidewall, Kondoh teaches they should be the same material. 7. The electronic device according to claim 5, wherein the metal film provided at least one of between the porous metal layer and the connection pad provided on the semiconductor substrate and between the porous metal layer and the connection pad provided on the chip has a proportion of a film thickness to half of a thickness of the sidewall portion in a direction orthogonal to the main surface of less than 10%. 6. The electronic device according to claim 1, wherein, a ratio of a film thickness of the metal film provided between the connection pad and the porous metal layer to half of the thickness of the bump in the direction orthogonal to the principal surface is less than 10%. Again, while this is claiming the bump material as opposed the sidewall, Kondoh teaches they should be the same material. 8. The electronic device according to claim 1, wherein the bump includes a porous metal layer formed of a same material as the porous metal layer of the sidewall portion, Again as discussed above Kondoh suggests the bump and sidewall should be the same material. and a metal film provided at least one of between the porous metal layer and the connection pad provided on the semiconductor substrate and between the porous metal layer and the connection pad provided on the chip, and on a side surface of the porous metal layer. 1…a nd a metal film provided on at least one of a portion between the connection pad provided on the semiconductor substrate and the porous metal layer and a portion between the connection pad provided on the chip and the porous metal layer, and on side surfaces of the porous metal layer. 9. The electronic device according to claim 8, wherein in the metal film provided between the porous metal layer and the connection pad, a proportion of a film thickness to a thickness of the bump in a direction orthogonal to the main surface is less than 10%. 5. The electronic device according to claim 1, wherein a ratio of a film thickness of the metal film provided between the connection pad and the porous metal layer to a thickness of the bump in the direction orthogonal to the principal surface is less than 10%. 10. The electronic device according to claim 8, wherein in the metal film provided between the porous metal layer and the connection pad, a proportion of a film thickness to half of a thickness of the bump in a direction orthogonal to the main surface is less than 10%. 6. The electronic device according to claim 1, wherein, a ratio of a film thickness of the metal film provided between the connection pad and the porous metal layer to half of the thickness of the bump in the direction orthogonal to the principal surface is less than 10%. 11. The electronic device according to claim 5, wherein materials of the porous metal layer and the metal film are a same kind of metal. This is not claimed, but JP ‘116 shows a similar device with bumps made of porous material and a metal film thereon, and uses the same materials for each. [0010], [0012]. It would have been obvious to a person of ordinary skill in the art to choose these known materials that are recognized in the art as suitable for this use. MPEP 2144.07. 12. The electronic device according to claim 1, wherein a material of the porous metal layer is a porous metal including gold, silver, platinum, or copper having a purity of 99.9 wt % or more. 17. The electronic device according to claim 1, wherein the metal particles include gold, silver, platinum or copper. The purity is not claimed. The purity is not given. JP ‘508 teaches that in such a connector bumps made of porous metal the purity of the metal should be 99.9 weight pct or more. [0008]. It would have been obvious to a person of ordinary skill in the art to use such high purity because if less the required conductivity cannot be ensured, as taught by JP ‘508. Conclusion US 6,455,878 also has an annular solder layer surrounding an active device. Fig. 4. US RE 47,708 also shows plating layers on the outside of electrode layers for bonding members. US 2009/0039507 also shows porous metal bumps between a chip and substrate. US 2024 / 0038706 is the publication of 18/006,004. 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