Final Rejection
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Following a non-final action, claims 1 and 6-8 are amended, claims 5 and 11 cancelled, and claims 13-14 added. Claims 1-4, 6-10, and 12-14 are pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-10, 12, and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US 5,448,114 (“Kondoh”) in view of US 11,374,381 (“Kriman”), and further in view of JP 2005-216508 (“JP ‘508”) as evidenced by JP 2011-216475 (“JP ‘475”), and further in view of JP H11-168116 (“JP ‘116”).
Regarding claim 1:
An electronic device, comprising: a semiconductor substrate; a chip;
Kondoh shows in Figs. 1-2 and discussion thereof an electronic device with chip 1 on substrate 2. The substrate is just said to be a circuit board, and while semiconductors are often used it is not said to be a semiconductor substrate. Kriman shows a similar device in Figs. 3A-G, see Fig. 3G for finished product, an electronic device with a chip 20/56 on a semiconductor (silicon col. 4 line 1) substrate 22. It would have been obvious to a person of ordinary skill in the art to use a semiconductor circuit board as it is common and known in the art as shown in Kriman. It is generally obvious to use known materials that are suitable for their intended use. MPEP 2144.07. This is also as simple substitution of a known element for another to obtain predictable results. MPEP 2143 I.B. The substrate is known in Kondoh, but not its material; this however is found in Kriman. It would have been obvious to a person of ordinary skill in the art to substitute a semiconductor substrate for an unspecified one. Kondoh must use some type of substrate, so it is natural to look to known ones. The substrate will operate in its normal way after the combination, so the combination is predictable.
a first plurality of connection pads, wherein connection pads included in the first plurality of connection pads are provided on a main surface of the semiconductor substrate; a second plurality of connection pads, wherein connection pads included in the second plurality of connection pads are provided on a main surface of the chip, wherein the main surface of the semiconductor substrate faces the main surface of the chip, and wherein each connection pad included in the first plurality of connection pads is opposite one connection pad in the second plurality of connection pads;
Kondoh shows pads 8 on the main surface of the substrate 2 and pads 5 on the main surface of chip 1, the main surfaces and the pads are facing and opposite each other
a plurality of bumps, wherein each bump connects a connection pad included in the first plurality of connection pads to a connection pad included in the second plurality of connection pads;
Bumps 4 connect the pads 5 and 8.
at least one of: a first annular connection pad, wherein the first annular connection pad is provided on the main surface of the semiconductor substrate, and wherein the first annular connection pad surrounds a first region in which the first plurality of connection pads is formed;
or a second annular connection pad, wherein the second annular connection pad is provided on the main surface of the chip, and wherein the second annular connection pad surrounds a second region in which the second plurality of connection pads is formed;
Kondoh shows annular pads 6 and 7 on the main surface of the chip and substrate, surrounding the regions where the pads 5 and 8 are formed.
and a sidewall portion that includes a porous metal layer annularly surrounding the first and second regions, wherein the sidewall portion is connected to the at least one of the first annular connection pad and the second annular connection pad,
Sidewall portion 3 of Kondoh annularly surrounds the regions where pads 5,8 are formed, and connects to pads 6,7. This sidewall is said to be solder, and is not said to be a porous metal layer. Kondoh further teaches that the bumps 4 and the annular wall member 3 being the same material is advantageous, as it avoids thermal expansion issues from using different materials. Col. 11 lines 11-15. JP ‘508 shows that it was known to attach a chip to a board by bumps, and often these bumps were made using plating. [0002]-[0003]. Note Kondoh’s bumps are formed by electroplating. Col. 11 lines 61-63. JP ‘508 teaches that instead bumps may be made of a porous metal material.1 It would have been obvious to a person of ordinary skill in the art to do so as it avoids impurities that reduce hardness and may be less complicated and expensive, as taught by JP ‘508. [0003]-[0004]. This also would have been a simple substitution of one known element for another to yield predictable results. MPEP 2143 I.B. The claim differs in the bump material, but that material is shown in JP ‘508. A person skilled in the art could have used the JP ‘508 material and the result would have been predictable because the bumps will still just do what they are supposed to do, they will just be a different material. See also MPEP 2144.07 (selecting known materials for their intended purpose is generally obvious; here the porous metal is known to be used for bumps). Again, as Kondoh teaches the bumps and annular wall should be the same material, both will be made this way.
wherein the sidewall portion includes a metal film provided between the porous metal layer and at least one of the first annular connection pad provided on the semiconductor substrate or the second annular connection pad provided on the chip, and on first and second side surfaces of the porous metal layer,
and wherein materials of the porous metal layer and the metal film are a same kind of metal.
The metal film is not shown in Kondoh, Kriman, or JP ‘508. As described in JP ‘116 (paragraphs [0009] - [0019] and Figs. 1-3), in an elastic bump such as a porous structure (see [0010], bump made from similar process as JP ‘508), it is a well-known technique to provide a metallic film on the side surface of the bump and between the bump and the connection pad. It would have been obvious to a person of ordinary skill in the art to do this as the porous material has more flexibility, mitigating thermal expansion problems, but the metal film layers maintain good connection, as taught by JP ‘116. [0015], [0004]. This also would have been a simple substitution of one known element for another to yield predictable results. MPEP 2143 I.B. The claim differs in the bump material, but that material is shown in JP ‘116. A person skilled in the art could have used the JP ‘116 material and the result would have been predictable because the bumps will still just do what they are supposed to do, they will just be a different material. See also MPEP 2144.07 (selecting known materials for their intended purpose is generally obvious; here the porous metal is known to be used for bumps). JP ‘508 uses Au for the porous material ([0008]), and JP ‘116 also uses Au as the metal film ([0012]). Also, JP ‘116 uses Ni for each ([0010], [0012]). It would have been obvious to a person of ordinary skill in the art that they can be the same material, as each is recognized by the art as suitable for this use. See MPEP 2144.07.
Regarding claims 2-3, these are not shown in Kondoh. In Kriman as noted above the substrate is silicon, and the chip is GaAs (col. 3 line 65, col. 4 lines 51-52), so they have a thermal expansion coefficient that differ by 0.1 ppm/°C. or more. Furthermore in Kriman the substrate 22 is a driver die and the chip 20 is VCSELs, a semiconductor laser. Col. 3 line 62-col. 4 line 10. It would have been obvious to a person of ordinary skill in the art to use the Kondoh base device with the specific device types and materials of Kriman as the use of a known technique to improve similar devices in the same way. MPEP 2143 I.C. Kondoh shows the base device, and Kriman may be considered an improvement as it uses different materials and types of device. One could use Kondoh’s base device with the Kriman materials/device and the result would have been predictable. Kondoh and Kriman each show how their devices operate and it would happen in substantially the same way when combined, therefore the result of the combination is predictable.
Regarding claims 4 and 12, the JP ‘508 porous metal layer contains metal particles having a particle diameter of 0.005 μm to 1.0 μm, and may be gold or silver with purity of 99.9 wt % or more. [0008].
Regarding Claims 6-7 and 9-10, JP ‘116 further describes that the thickness (1.3 to 3 micrometers) of the metal films (6, 7) is 5% or less of the thickness (100 to 300 micrometers) of the bump (paragraph [0011]). Again, Kondoh teaches that what applies to a bump applies also to the sidewall.
Regarding claim 8, the bumps have this structure as described above re: claim 1. Again, Kondoh teaches that what applies to a bump applies also to the sidewall.
Regarding claim 13, there is no indication in Kondo that the annular ring is connected to a circuit, it is said to be for isolation and heat dissipation. Col. 9 lines 44-54, col. 10 lines 1-15.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1-4, 6-10, and 13 are rejected on the ground of nonstatutory double patenting as being unpatentable over the claims as listed below of US 12,609,507 in view of Kondoh, and further in view of JP ‘116.
Claim 12 is rejected on the ground of nonstatutory double patenting as being unpatentable over the claims as listed below of US 12,609,507 in view of Kondoh and JP ‘116, and further in view of JP ‘508.
This application
US 12,609,507
1. An electronic device, comprising:
a semiconductor substrate;
a chip;
“1. An electronic device, comprising:
a semiconductor substrate;
a chip”
a first plurality of connection pads, wherein connection pads included in the first plurality of connection pads are provided on a main surface of the semiconductor substrate; a second plurality of connection pads, wherein connection pads included in the second plurality of connection pads are provided on a main surface of the chip, wherein the main surface of the semiconductor substrate faces the main surface of the chip, and wherein each connection pad included in the first plurality of connection pads is opposite one connection pad in the second plurality of connection pads; a plurality of bumps, wherein each bump connects a connection pad included in the first plurality of connection pads to a connection pad included in the second plurality of connection pads;
“1… a bump that connects connection pads provided on opposing principal surfaces of the semiconductor substrate and the chip,”
Arguably there are not a plurality as claimed. Kondoh is a similar device and includes a plurality of such pads on each main surface. It would have been obvious to a person of ordinary skill in the art to use multiple bumps because often times multiple different electrical connections are needed.
at least one of: a first annular connection pad, wherein the first annular connection pad is provided on the main surface of the semiconductor substrate, and wherein the first annular connection pad surrounds a first region in which the first plurality of connection pads is formed; or a second annular connection pad, wherein the second annular connection pad is provided on the main surface of the chip, and wherein the second annular connection pad surrounds a second region in which the second plurality of connection pads is formed; and
a sidewall portion that includes a porous metal layer annularly surrounding the first and second regions, wherein the sidewall portion is connected to the at least one of the first annular connection pad and the second annular connection pad wherein the sidewall portion includes a metal film provided between the porous metal layer and at least one of the first annular connection pad provided on the semiconductor substrate or the second annular connection pad provided on the chip, and on first and second side surfaces of the porous metal layer,
“1… wherein the bump includes: a porous metal layer; and a metal film provided on at least one of a portion between the connection pad provided on the semiconductor substrate and the porous metal layer and a portion between the connection pad provided on the chip and the porous metal layer, and on side surfaces of the porous metal layer.”
The annular pads and sidewall are not claimed. Kondoh Figs. 1-2 and discussion thereof starting at col. 9 line 1 shows a semiconductor device where chip 1 is bonded to substrate 2 via solder bumps 4. There is also a solder wall 3 that annularly surrounds the region where the other bumps are provided and connects to pads on the chip and substrate. See also 103 rejection above. It would have been obvious to a person of ordinary skill in the art to include such an annular wall as it isolates the inner region from outside air, which can be advantageous in some applications, as taught by Kondoh. Col. 9 lines 44-54. Including the wall also greatly increases the contact area, providing more heat dissipation, as taught by Kondoh. Col. 10 lines 1-15.
Kondoh further teaches that the bumps 4 and the annular wall member being the same material is advantageous, as it avoids thermal expansion issues from using different materials. Col. 11 lines 11-15. Claim 1 already claims the bumps as a porous metal with metal film as claimed, so combined with Kondoh this teaches that the sidewall may also be the same porous metal material with metal film.
and wherein materials of the porous metal layer and the metal film are a same kind of metal.
This is not claimed, but JP ‘116 shows a similar device with bumps made of porous material and a metal film thereon, and uses the same materials for each. [0010], [0012]. It would have been obvious to a person of ordinary skill in the art to choose these known materials that are recognized in the art as suitable for this use. MPEP 2144.07.
2. The electronic device according to claim 1, wherein the chip has a thermal expansion coefficient different from a thermal expansion coefficient of the semiconductor substrate by 0.1 ppm/° C. or more.
2. The electronic device according to claim 1, wherein the chip has a thermal expansion coefficient different from that of the semiconductor substrate by 0.1 ppm/°C or more.
3. The electronic device according to claim 1, wherein the chip is a semiconductor laser, and the semiconductor substrate includes a drive circuit that drives the semiconductor laser.
3. The electronic device according to claim 1, wherein the chip is a semiconductor laser, and the semiconductor substrate has a drive circuit that drives the semiconductor laser.
4. The electronic device according to claim 1, wherein the porous metal layer contains metal particles having a particle diameter of 0.005 μm to 1.0 μm.
4. The electronic device according to claim 1, wherein the porous metal layer contains metal particles having a particle diameter of 0.005 pm to 1.0 pm.
Again, while this is claiming the bump material as opposed the sidewall, Kondoh teaches they should be the same material.
6. The electronic device according to claim 5, wherein the metal film provided at least one of between the porous metal layer and the connection pad provided on the semiconductor substrate and between the porous metal layer and the connection pad provided on the chip has a proportion of a film thickness to a thickness of the sidewall portion in a direction orthogonal to the main surface of less than 10%.
5. The electronic device according to claim 1, wherein a ratio of a film thickness of the metal film provided between the connection pad and the porous metal layer to a thickness of the bump in the direction orthogonal to the principal surface is less than 10%.
Again, while this is claiming the bump material as opposed the sidewall, Kondoh teaches they should be the same material.
7. The electronic device according to claim 5, wherein the metal film provided at least one of between the porous metal layer and the connection pad provided on the semiconductor substrate and between the porous metal layer and the connection pad provided on the chip has a proportion of a film thickness to half of a thickness of the sidewall portion in a direction orthogonal to the main surface of less than 10%.
6. The electronic device according to claim 1, wherein, a ratio of a film thickness of the metal film provided between the connection pad and the porous metal layer to half of the thickness of the bump in the direction orthogonal to the principal surface is less than 10%.
Again, while this is claiming the bump material as opposed the sidewall, Kondoh teaches they should be the same material.
8. The electronic device according to claim 1, wherein the bump includes a porous metal layer formed of a same material as the porous metal layer of the sidewall portion,
Again as discussed above Kondoh suggests the bump and sidewall should be the same material.
and a metal film provided at least one of between the porous metal layer and the connection pad provided on the semiconductor substrate and between the porous metal layer and the connection pad provided on the chip, and on a side surface of the porous metal layer.
1…and a metal film provided on at least one of a portion between the connection pad provided on the semiconductor substrate and the porous metal layer and a portion between the connection pad provided on the chip and the porous metal layer, and on side surfaces of the porous metal layer.
9. The electronic device according to claim 8, wherein in the metal film provided between the porous metal layer and the connection pad, a proportion of a film thickness to a thickness of the bump in a direction orthogonal to the main surface is less than 10%.
5. The electronic device according to claim 1, wherein a ratio of a film thickness of the metal film provided between the connection pad and the porous metal layer to a thickness of the bump in the direction orthogonal to the principal surface is less than 10%.
10. The electronic device according to claim 8, wherein in the metal film provided between the porous metal layer and the connection pad, a proportion of a film thickness to half of a thickness of the bump in a direction orthogonal to the main surface is less than 10%.
6. The electronic device according to claim 1, wherein, a ratio of a film thickness of the metal film provided between the connection pad and the porous metal layer to half of the thickness of the bump in the direction orthogonal to the principal surface is less than 10%.
12. The electronic device according to claim 1, wherein a material of the porous metal layer is a porous metal including gold, silver, platinum, or copper having a purity of 99.9 wt % or more.
17. The electronic device according to claim 1, wherein the metal particles include gold, silver, platinum or copper. The purity is not claimed.
The purity is not given. JP ‘508 teaches that in such a connector bumps made of porous metal the purity of the metal should be 99.9 weight pct or more. [0008]. It would have been obvious to a person of ordinary skill in the art to use such high purity because if less the required conductivity cannot be ensured, as taught by JP ‘508.
13. The electronic device according to claim 1, wherein the first annular connection pad is not connected to a circuit included in the semiconductor substrate.
Kondoh does not show the annular connection as part of the circuit, as it is used for isolation and heat dissipation. See 103 rejection. It would have been obvious to a person of ordinary skill in the art that it need not be part of the circuit as it simplifies the system.
Allowable Subject Matter
Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. There is not shown in the prior art the device of claim 1 wherein the metal film of the sidewall portion is a first metal film, the device further comprising a second metal film disposed between the first metal film and the at least one of the first annular connection pad and the second annular connection pad, wherein the first metal film and the second metal film are a same kind of metal. JP ‘116 shows two metal films but uses different metals, and there is no reason seen to modify this to meet the claim other than hindsight, particularly because JP ‘116 appears to use these metals for a reason. [0014].
Response to Arguments
Applicant's arguments filed 5/26/2026 have been fully considered but they are not persuasive. While applicant argued that the claimed material in general is not found in the art, applicant did not specifically explain why the art is lacking, and it is deemed to meet the claims as above. Note the primary and secondary reference are switched now as compared to the prior action, as this is deemed to better meet the claims after the extensive amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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1 While JP ‘508 does not say so explicitly, JP ‘475 recognizes that JP ‘508 is a porous bump: “Patent Document 2 [which is JP ‘508] proposes a bump made of a sintered material that is porous, relatively soft, and elastic as a material used for the bump.”
Prosecution Insights