Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 6-9 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Chen et al. (U. S. Pub. 2020/0309864), In view of Wyar et al. (U. S. Patent 8,222,906).
As for claim 1, Chen et al. discloses a system (see system as shown in Fig. 4 and [0067]—[0070]) for line (line 203) diagnostics using time domain reflectometry, comprising:
a driver (202) configured to drive a first pin and a second pin (i.e., the driver can be used to drive a first pin of a first electric line, or to drive a second pin of a second electric line when multiple TDR measurements are performed on multiple electric lines);
a analog front end comprising:
a first comparator (304, which may comprise two separate comparators, [0069]) configured to receive a first reference voltage (Vth1) and a first pin output;
a second comparator (i.e., separate comparators may be used to perform the two comparisons, see [0069], lines 6-7) configured to receive a second reference voltage (Vth2) and a second pin output; and
a buffer (counter 308) configured to store a first time at which a first comparator determines the first pin output crosses the at least one reference voltage, and a second time at which a second comparator determines the second pin output crosses the at least one reference voltage (i.e., for storing and determining the first signal transition 310 crosses Vth1 and when the second signal transition 311 crosses the second threshold Vth2); and
a digital front end configured to receive data from the buffer and further configured to identify faults using received data from the buffer (i.e., the digital processor and memory unit of the control circuit 302 for identify and determining the location of defect 204; see [0067]—[0070]).
Still referring to claim 1, Chen et al. does not specifically disclose that the driver is configured as a differential driver, to drive a first pin and a second pin, with the first pin and the second pin corresponding to respective complementary outputs of a port of a transmission line.
Wyar et al. discloses a conventional differential driver (22 in Fig. 5) used in a time domain reflectometer to drive a first pin and a second pin, with the first pin and the second pin corresponding to respective complementary outputs of a port of a transmission line (28).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Chen et al. to use a conventional differential driver, to drive a first pin and a second pin, with the first pin and the second pin corresponding to respective complementary outputs of a port of a transmission line, as taught by Wyar et al. for the purpose of more accurately testing the transmission line of a communication or telephone cable system with differential signaling, with improved noise rejection and lower EMI.
Still referring to claim 1, Chen et al. does not specifically disclose a third comparator configured to receive a third reference voltage and the first pin output, and a fourth comparator configured to receive a fourth reference voltage and the second pin output.
Chen et al. does however, suggest using a third reference voltage (Vth3) and a fourth reference voltage (Vth4), up to ten reference voltage (see [0079]—[0082]); and performing multiple TDR measurements in parallel by using a control circuit (each with two/separate comparators) for EACH of the electrical lines under test (see [0075]).
It would have been obvious to a person of ordinary skill in the art, before the effective fling date of the claimed invention to further modify Chen et al. to use a third and a fourth comparator as claimed, for the purpose of testing the same electric line using a third and fourth reference voltage for comparison purpose or for improving the resolution (see [0079]—[0082]), or for the purpose of using an additional control circuit with two additional comparators for testing multiple electric lines in parallel (see [0075]).
As for claim 2, Chen et al. in view of Wyar et al. discloses the system/method of claims 1 and 10, wherein the digital front end is configured to identify faults based on detecting rising edges and falling edges (i.e., the rising edges and falling edges in the received data corresponding to the defect) in the received data.
As for claim 4, Chen et al. in view of Wyar et al. discloses the system of claim 1, wherein the driver (driver 202) is configured to drive the pins one of differentially and single-endedly (i.e., single-endedly as in Fig. 4 or differentially as in Wyar).
As for claim 3, Chen et al. in view of Wyar et al. discloses the system of claim 1, wherein the first and second reference voltages can be set by a control circuit (see [0069]).
Chen et al. in view of Wyar et al. does not specifically disclose using one of a resistor ladder and a digital-to-analog converter to set the first reference voltage and the second reference voltage.
It would have been obvious to a person of ordinary skill in the art, before the effective fling date of the claimed invention to further modify the control circuit of Chen et al. to use any conventional resistor ladder or a digital-to-analog converter to set the first and second reference voltages according to the specific requirements of the different applications.
As for claim 6, Chen et al. in view of Wyar et al. discloses the system of claim 1, further comprising a counter (counter 308) configured to begin counting when the driver (202) is activated, and wherein the counter (308) is used to determine the first time and the second time (see [0070]).
As for claims 7 and 8, Chen et al. in view of Wyar et al. discloses the system of claim 1, further comprising a detect circuit configured to receive a first and second comparator output and determine when the first and second pin output crosse the first and second reference voltages (i.e., the control circuit for determining at which clock cycle the first signal transition crosses the first threshold, and at which clock cycle the second signal transition crosses the second threshold, see [0070]).
As for claim 9, Chen et al. in view of Wyar et al. discloses the system/method of claim 1, wherein identifying faults using the received data comprises identifying faults in a peripheral device in a two-wire bus/ communication system (i.e., the two wire communication cable 28 in Fig. 5 of Wyar et al.).
As for claim 19, Chen et al. in view of Wyar et al. discloses a system (see system as shown in Fig. 4 and [0067]—[0070]) for line diagnostics using time domain reflectometry, comprising:
a driver (driver 202) configured to drive a first pin and a second pin (i.e., the driver can be used to drive a first pin of a first electric line, or to drive a second pin of a second electric line when multiple TDR measurements are performed on multiple electric lines);
a counter (counter 308) configured to begin counting when the driver (202) is activated;
a circuit (control circuit for setting the value of the threshold, see [0069]) configured to set at least one reference voltage (Vth);
a first comparator (304) configured to receive at least one reference voltage and a first pin output;
a second comparator (i.e., separate comparators may be used to perform the two comparisons, see [0069], lines 6-7) configured to receive the at least one reference voltage and a second pin output;
a detect circuit configured to receive a first comparator output and a second comparator output, determine when the first pin output crosses the at least one reference voltage, and determine when the second pin output crosses the at least one reference voltage (i.e., the control circuit for determining at which clock cycle the first signal transition crosses the first threshold, and at which clock cycle the second signal transition crosses the second threshold, see [0070]); and
a buffer (counter 308) configured to store a first time at which a first comparator determines the first pin output crosses the at least one reference voltage, and store a second time at which a second comparator determines the second pin output crosses the at least one reference voltage; and
a digital front end configured to receive data from the detect circuit and further configured to identify faults using received data (i.e., the digital processor and memory unit of the control circuit 302 for identify and determining the location of defect 204; see [0067]—[0070]).
Still referring to claim 19, Chen et al. does not specifically disclose that the driver is configured as a differential driver, to drive a first pin and a second pin, with the first pin and the second pin corresponding to respective complementary outputs of a port of a two wire transmission line.
Wyar et al. discloses a conventional differential driver (22 in Fig. 5) used in a time domain reflectometer to drive a first pin and a second pin, with the first pin and the second pin corresponding to respective complementary outputs of a port of a two wire transmission line (28).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the claimed invention, to modify Chen et al. to use a conventional differential driver, to drive a first pin and a second pin, with the first pin and the second pin corresponding to respective complementary outputs of a port of a two wire transmission line, as taught by Wyar et al. for the purpose of more accurately testing the transmission line of a two wire communication or telephone cable system with differential signaling, for the advantage of improved noise rejection and lower EMI.
Still referring to claim 19, Chen et al. does not specifically disclose a third comparator configured to receive the at least one reference voltage and the first pin output, and a fourth comparator configured to receive the at least one reference voltage and the second pin output.
Chen et al. does however, suggest performing multiple TDR measurements in parallel by using an additional control circuit (with a third and fourth comparators) for EACH of the electrical lines under test (see [0075]).
It would have been obvious to a person of ordinary skill in the art, before the effective fling date of the claimed invention to further modify Chen et al. to use the additional control circuit with a third and a fourth comparator, for the purpose of testing multiple electric lines in parallel (see [0075]).
As for claim 20, Chen et al. in view of Wyar et al. discloses the system of claim 19, wherein the detect circuit (i.e., the control circuit for determining at which clock cycle the first signal transition crosses the first threshold, and at which clock cycle the second signal transition crosses the second threshold, see [0070])receives counter output from the counter (counter 308) and wherein the detect circuit is further configured to use the counter output to determine a first time at which the first pin output crosses the at least one reference voltage (i.e., the clock cycle the first signal transition crosses the first threshold).
Allowable Subject Matter
Claims 10-14 and 17-18 are allowed.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 10-14 and 17-18 are allowable because none of the prior art discloses or fairly suggests a method for line diagnostics using time domain reflectometry, comprising: driving at least one of a first pin or a second pin, with the first pin and the second pin corresponding to respective complementary outputs of a port of a transmission line; and identifying faults by determining a slew rate for at least one of the first comparator output or the second comparator output, and in the combination as claimed in claim 10.
Response to Arguments
Applicant’s arguments with respect to claims 1-4, 6-9 and 19-20 have been fully considered but they are not persuasive.
In response to applicant’s argument regarding claims 1 and 19, the examiner asserts that Chen et al. does suggest using a third reference voltage (Vth3) and a fourth reference voltage (Vth4), up to ten reference voltage (see [0079]—[0082]); and performing multiple TDR measurements in parallel by using an additional control circuit (with a third and fourth comparator) for EACH of the electrical lines under test (see [0075]).
Therefore, the person of ordinary skill in the art would find it obvious to further modify Chen et al. to use a third and a fourth comparator with the third and fourth reference voltages, for the purpose of testing the same electric line using the third and fourth reference voltage for comparison purpose, or for improving the resolution (see [0079]—[0082]), or for the purpose of testing a second electric line or multiple electric lines in parallel by using an additional control circuit (with a third and a fourth comparator) for each of the electric line under test (see [0075]).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMY HE whose telephone number is (571)272-2230. The examiner can normally be reached 9:00am--5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached at (571) 272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMY HE/Primary Examiner, Art Unit 2858
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