Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 12-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bian (CN 112447818 A, cited by Applicant, cited previously)
Regarding claims 1 and 13, Bian teaches a display panel for claim 1 (display device comprising a display panel for claim 13) (at least Fig.1-10), comprising a display area DA and a non-display area NDA1 located on at least one side of the display area, and further comprising: a substrate 100 ; a conductive structure 10, located on a side of the substrate and extending from the display area to the non-display area (see 10 in Fig.1;also see: The display device may further include a power supply voltage line located in the first non-display area, a power supply voltage line around a portion of the display area, wherein the second electrode extending to the first non-display area can be electrically connected to the power supply voltage line); a first planarization layer 109, covering the conductive structure and extending from the display area to the non-display area; a second planarization layer 111, located on a side of the first planarization layer away from the substrate and located in the display area and the non-display area;
a pixel definition layer 113, located on a side of the second planarization layer away from the substrate and located in the display area and the non-display area;
a cathode layer 330 (counter electrode 330), located on a side of the pixel definition layer away from the substrate; and a first spacing groove (groove above 20 in Fig.8 or 9), located in the non-display area and penetrating through the second planarization layer and the pixel definition layer, wherein a boundary of the cathode layer falls into the first spacing groove.
Regarding claim 12, Bian teaches a display panel, wherein when the first planarization layer, the second planarization layer, and the pixel definition layer are etched with a same etching liquid, an etching rate of the first planarization layer is less than an etching rate of the second planarization layer and an etching rate of the pixel definition layer (the limitations are drawn to the method of making the device and is therefore not germane to the device claims).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action;
A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at effective filing date to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
Claims 2 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Bian
Regarding claims 2 and 14, Bian teaches a display panel, further comprising a first barrier dam and a second barrier dam located in the non-display area at intervals (indicated by 110 and 120), wherein the second barrier dam 120 is located on a side of the first barrier dam away from the first spacing groove, and a second spacing groove (between 110 and 120) is defined between the first barrier dam and the second barrier dam; wherein the first barrier dam comprises the second planarization layer and the pixel definition layer (113a and 111a in 110), but does not teach the second barrier dam comprises the pixel definition layer and does not comprise the second planarization layer in the embodiment of Fig.8 or 9.
However, in the embodiment of Fig.11, Bian teaches the feature of the second barrier dam (indicated by element TH3, SP1, SP2 and 115-3) that comprises the pixel definition layer (dotted section in the left most dam in Fig.11) and does not comprise the second planarization layer.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to vary the design wherein the second dam does not possess the second planarization layer in order to achieve easy manufacturing and robust packaging.
Claims 3-5 ,9-10 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Bian in view of Li (CN 111725257 A, cited previously)
Regarding claims 3 and 15, Bian teaches the invention set forth in claims 1 and 13, above but is silent regarding an etching barrier layer located on the side of the first planarization layer away from the substrate and located in the non-display area, wherein an orthographic projection of the etching barrier layer on the substrate at least covers an orthographic projection of the first spacing groove on the substrate.
However, it is well-known in the art to use etch barrier layers for protection of passivation or other layers, during etching process, wherein the etch barrier layer can be located in specific regions wherein etching is performed.
Li teaches an etch barrier layer (250 in Fig.8) which covers the groove G in the non-display area and from the teachings of Li, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to form an etch barrier layer on the side of the first planarization layer away from the substrate and located in the non-display area, wherein an orthographic projection of the etching barrier layer on the substrate at least covers an orthographic projection of the first spacing groove on the substrate, in order to protect the surrounding layers during etching process (see in Li: As described above with reference to FIG. 9 A, the second hole 209H formed by etching the first portion of the first organic insulating layer 209 in the first opening ILS-OP to form a second hole. The lower metal layer 250 may be used as an etching barrier for an etching process to form a second hole 209H The bottom surface of the groove G may be in the same horizontal surface as the upper surface of the lower metal layer 250. The bottom surface of the groove G may be on the same surface as the upper surface of the lower metal layer 250. The upper surface of the lower metal layer 250 may be the bottom surface of the groove G)
Regarding claims 4 and 16, Bian in view of Li teaches the display panel, wherein an orthographic projection of a boundary of the etching barrier layer away from the display area on the substrate is within an orthographic projection of the second barrier dam on the substrate (from the teachings of Li wherein the etch barrier layer 250 that extends underneath of dams and grooves).
Regarding claims 5 and 17, Bian in view of Li teaches the display panel, wherein
the etching barrier layer is made of metal (see in Li: The bottom surface of the groove G may be in the same horizontal surface as the upper surface of the lower metal layer 250).
Regarding claim 9, Bian in view of Li teaches the display panel, wherein the cathode layer (counter electrode/cathode layer 223 in in Fig.8 of Li) contacts the etching barrier layer (250) in the first spacing groove (see ibn Li: The counter electrode 223 may be formed of a conductive material having a low work function).
Regarding claim 10, Bian in view of Li teaches the display panel, further comprising an encapsulation layer (400 in Fig.8 of Bian) disposed on a side of the cathode layer away from the substrate, wherein the encapsulation layer comprises a first inorganic (410 in Bian; see in Bian: The first inorganic encapsulation layer 410 may completely cover the counter electrode 330) encapsulation layer, an organic encapsulation layer (see in Bian: the organic encapsulation layer 420 can be formed on the first inorganic encapsulation layer 410 by spin coating process), and a second inorganic encapsulation layer (see in Bian: The second inorganic encapsulation layer 430 may cover the organic encapsulation layer 420) arranged and stacked in a thickness direction of the display panel and extending from the display area to the non-display area; wherein the first inorganic encapsulation layer contacts the etching barrier layer in the first spacing groove (from the combined teaches of Bian in view of Li, and from the teachings of Li wherein 250 is the etching barrier layer, 230 is the encapsulation/capping layer and gap G shows the features of wherein the first inorganic encapsulation layer contacts the etching barrier layer in the first spacing groove).
Claims 6-7 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Bian in view of Li and further in view of JP (JP 2023029445 A, cited previously )
Regarding claims 6 and 18, Bian in view of Li teaches the invention set forth in claims 5 and 17 above but is silent regarding and the etching barrier layer is provided with a plurality of exhaust holes in the first spacing groove, and the first planarization layer is exposed by the plurality of exhaust holes.
Formation of exhaust holes over a planarization layer is a well-known technique, to outgas the planarization layer during manufacturing.
JP teaches this feature, wherein a plurality of exhaust holes 750 are formed over the planarization layer 150 to release gases formed during making of the planarization layer (see in JP: A planarization layer 150 may be disposed on the gate driver 300 in the active area (AA), and a metal layer made of the same material as the anode electrode 240 may be disposed on the planarization layer 150. A metal layer formed by the anode electrode 240 can be referred to as a connection electrode 740. The connection electrode 740 may be provided with a gas exhaust pattern 750. The gas exhaust pattern 750 may be disposed in a non-display area, but is a hole for exhausting hydrogen (. sub.H2 ) gas that may be generated in the planarization layer 150 during heat treatment during the manufacturing process of the display panel 100).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to use the etching barrier layer over the planarization layer, with exhaust holes formed above the planarization layer, from the teachings of JP, in the device of Bian in view of Li in order to degas/release gases from the planarization layer.
Regarding claim 7 and 19, Bian in view of Li and JP teaches the display panel, wherein a plurality of planarization blocks (160 on top of exhaust holes 750 in Fig.3 of JP) corresponding to the plurality of exhaust holes 750 are disposed in the first spacing groove and are disposed in a same layer as the second planarization layer (that is equivalent to 160 above the exhaust holes 750), and an orthographic projection of each of the plurality of planarization blocks 160 (in JP) on the substrate covers an orthographic projection of a corresponding one of the plurality of exhaust holes 750 (in JP) on the substrate. Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to use the same technique and location of the exhaust holes with respect to the planarization blocks as disclosed in JP, in the device of Bian in view of Li, in order to exhaust the gases formed during the manufacturing.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Bian in view of Li and JP further in view of Lu (CN 113363264 A, cited previously)
Regarding claim 8, Bian in view of Li and JP teaches the invention set forth in claim 7 above, but is silent regarding an aperture of each of the plurality of exhaust holes ranges from 12 microns to 18 microns, and a width of each of the plurality of planarization blocks ranges from 12 microns to 18 microns.
Lu teaches: Preferably, the diameter of the exhaust hole is 5-15 microns, preferably 10 microns, the number of the exhaust hole is determined according to the second passivation layer 107 and the first resin layer 106 of the contact.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to use the size of the exhaust openings as disclosed in Lu, in the device of Bian in view of Li and JP, in order to quickly exhaust gas or liquid and not store them.
Claims 11 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Bian in view of Li2 (CN 111490073 A; herein after Li2, cited previously)
Regarding claims 11 and 20, Bian teaches the invention set forth in claims 1 and 13 above, but is silent regarding the conductive structure comprises a first conductive layer and a second conductive layer arranged and stacked in a thickness direction of the display panel; wherein the display panel further comprises a third planarization layer located in the display area and covering part of the first conductive layer and the substrate in the display area, and part of the second conductive layer in the display area is located on a side of the third planarization layer away from the substrate.
Li2 teaches an OLED wherein the conductive structure comprises a first conductive layer and a second conductive layer (top dome shaped portion of 210 or 230 and lower vertical portion of 210 or 230) arranged and stacked in a thickness direction of the display panel; wherein the display panel further comprises a third planarization layer 400 located in the display area and covering at least a side of a part of the first conductive layer and a side of a part of the substrate 110 located in the display area 10 (Fig.6), and part of the second conductive layer located in the display area is located on a side of the third planarization layer away from the substrate.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to use the additional third planarization layer as disclosed in Li2, in the display device of Bian, in order to accommodate/cover the TFT elements.
Other art
Cited previously: WO 2022087903 A1, CN 113644104 A, CN 112909028 A
Response to Arguments
The arguments filed by the Applicant on 10/27/25 is acknowledged. However, they are not found to be persuasive. Applicant has argued that the conductive lines 10 is not in the display area.
Bian discloses: The first power supply voltage ELVDD can be provided to each pixel P by a drive voltage line PL connected to the first power supply voltage line 10.
Unless the power supply voltage line does not have a conductive extension into the display area or Pixel as cited above, its purpose is not served.
The same applies to voltage line 20, wherein Bian discloses: and the second power supply voltage line 20 may provide the second power supply voltage ELVSS (see FIG. 2 A and FIG. 2B) to each pixel P.
The power supply voltage lines 10 and 20 penetrate into the display area and upto the Pixels, in order to provide power, and they cannot provide power unless they are conductive, upto the pixel area.
Also see, “The relative electrode (such as cathode) of the organic light emitting diode OLED is configured to receive the second power supply voltage ELVSS (or common power supply voltage)”.
Further, Applicant argues that the boundary of the cathode layer does not fall into the first spacing groove, because the cathode extends into the dam 110.
The arguments are not found to be persuasive because the groove is the entire well as shown below:
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379
267
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The channel in its entirety is considered as the groove and the cathode is seen to end at the boundary where the entire groove shape ends in the above figure.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Fatima Farokhrooz whose telephone number is (571)-272-6043. The examiner can normally be reached on Monday- Friday, 9 am - 5 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, James Greece can be reached on (571) 270-3711. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http;//pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free).
/Fatima N Farokhrooz/
Examiner, Art Unit 2875