Prosecution Insights
Last updated: September 17, 2026
Application No. 18/267,112

COMMUNICATION LINK OPERATING CHARACTERISTIC TESTING SYSTEM AND TESTING METHOD THEREOF

Non-Final OA §103
Filed
Sep 06, 2024
Priority
Jan 19, 2022 — CN 202210059599.0 +1 more
Examiner
KIM, WON TAE C
Art Unit
Tech Center
Assignee
Shanghai Tosun Technology Ltd.
OA Round
1 (Non-Final)
89%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
264 granted / 297 resolved
+28.9% vs TC avg
Minimal -3% lift
Without
With
+-2.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
33 currently pending
Career history
313
Total Applications
across all art units

Statute-Specific Performance

§101
1.2%
-38.8% vs TC avg
§103
54.0%
+14.0% vs TC avg
§102
15.4%
-24.6% vs TC avg
§112
26.1%
-13.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 297 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-8 are pending. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The IDS statements filed to date have been considered by the examiner. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim(s) 1-2 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Olgaard et al., US 2010/0123471, (“Olgaard”), in view of Lakkavalli, US 2017/0264524, (“Lakkavalli”). Regarding claim 1, Olgaard teaches “A communication link operating characteristic testing system (see, e.g., Fig. 3; note that other examples are disclosed such as Fig. 1 and Figs. 2a, 2b), comprising: a relay combination circuit board (Fig. 3, switch/relay 104aa, 104ab … 104bb, 106aa … 106bb; the switches are implicitly on a circuit board – however, see below for an explicit teaching), a simulation assembly, wherein the simulation assembly is arranged on the relay combination circuit board (Fig. 3, VSA 110aa, VSA ba, signal combiners 102a, 102b; see also, Fig. 1, VSG 20ag, VSG 20bg; these devices which form in part a simulation assembly are implicitly arranged on the circuit board as the switches/relays – however, see below for an explicit teaching); and an interface assembly, wherein the interface assembly is arranged on the relay combination circuit board, and the interface assembly is configured for connecting a device under test (DUT) (Fig. 2A, attenuators 109aa, 109ab, 109ac serve as an interface to the DUT such as DUT1; the attenuators are implicitly arranged on the circuit board – however, see below for an explicit teaching; note that in Fig. 3, an implicit interface, e.g., at switches/relays 106aa, 106ab must exist to connect the switches to the DUT such as DUT1); wherein relays on the relay combination circuit board are turned on/off to connect the DUT to required devices in the simulation assembly to test the DUT under a working environment simulated by the simulation assembly” (Fig. 3, switches/relays 104aa … 106bb are turned on/off to connect the DUTs to the simulation assembly including the signal combiners and the VSAs; see paragraph nos. 0066-0068, 0072). While Olgaard teaches implicitly that the switches/relays are on a “circuit board” and the related associated “arranged … circuit board” limitations of claim 1, Lakkavalli teaches these limitations explicitly, see paragraph no. 0003, “In traditional telecommunications switches, a line card is a printed circuit board that includes all of the facilities for maintaining a telephone line. In the context of the wired and wireless communications test systems described herein, a line card or module is a printed circuit board with various components mounted on the printed circuit board for performing a test and/or a communications function. Each line card is connected either physically (e.g., through a cable) or via electromagnetic coupling (e.g., using antennas) to one interface of the DUT”. It would have been obvious to one of ordinary skill in the art before the effective filing date of this claimed invention to modify Olgaard by including the switches/relays on a printed circuit board and the associated test devices (i.e., the simulation and interface assemblies) on the same circuit board as taught by Lakkavalli since this is typically done in wireless communication test systems, as suggested by Lakkavalli in paragraph no. 0003. In addition, the use of such circuit boards for testing during design and manufacturing of wireless devices improves the reliability of such wireless devices. Regarding claim 2, Olgaard teaches “wherein the simulation assembly comprises a waveform generator” (Fig. 1, VSGs) but not “a program-controlled oscilloscope, a multimeter, a programmable power supply device, a four-quadrant waveform amplifier, a program-controlled adjustable resistance/capacitance load, and an external sub-link.” However, these elements are all known in the art. It would have been obvious to one of ordinary skill in the art before the effective filing date of this claimed invention to modify Olgaard and Lakkavalli by including these known elements in the simulator assembly of Olgaard since each element is known, and the combination of these known elements is merely a design parameter readily within the skill of one of ordinary skill in the art. Regarding claim 4, Olgaard teaches “determining a working environment required for the DUT; and connecting corresponding devices according to the working environment to test the DUT” (see, e.g., Fig. 2A which shows either one of VSA or VSG being switched via a switch 110ab to DUT1 to test, e.g., a receive operation (“working environment”) of the DUT1, see paragraph nos. 0073, 0064, 0065). Allowable Subject Matter Claims 3 and 5-8 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art of record does not teach or fairly suggest each of the limitations recited in each of the claims 3 and 5-8. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WON TAE C. KIM whose telephone number is (571)270-1812. The examiner can normally be reached Monday-Friday 8:00 am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Edan Orgad can be reached at (571)272-7884. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WON TAE C KIM/Primary Examiner, Art Unit 2414
Read full office action

Prosecution Timeline

Sep 06, 2024
Application Filed
Sep 01, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
89%
Grant Probability
86%
With Interview (-2.9%)
2y 6m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 297 resolved cases by this examiner. Grant probability derived from career allowance rate.

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