DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Withdrawal of Restriction/Election Requirement
Applicant’s traversal of the restriction requirement set forth in the Office action mailed June 4, 2026 has been considered and is persuasive. Accordingly, the restriction requirement is withdrawn. Nonelected species II-V are reinstated and examined on the merits herein.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102 of this title, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negatived by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6 are rejected under 35 U.S.C. 103(a) as being unpatentable over Tanaka et al. (US 2010/0052656 A1) in view of Ono et al. (US 2013/0049760 A1) .
Re 1,Tanaka discloses a detection and gating module configured to detect a voltage of each battery in a battery pack containing batteries connected in series (CEL1-CELn), comprising a plurality of gating switches (SA0-SAn, SB0-SBn) connected between respective battery-voltage input nodes (NC0-NCn) and sense input nodes (NA, NB), wherein the gating switches are selectively turned on and off to detect the voltage of a selected battery (Fig. 1; paras. [0050]-[0053], [0077]-[0082]); protection circuits comprising constant-voltage elements (D1), such as Zener diodes, connected between the source and gate nodes of respective gating transistors (Qn1, Qn2) (Fig. 2A; paras. [0054]-[0056]); and voltage generation/drive circuits (CM1) configured to provide a gate-source bias for turning the respective gating transistors on (Figs. 2A-2B; paras. [0055]-[0062]).
Tanaka fails to expressly disclose generating both the claimed turn-on control voltage and the claimed lower turn-off control voltage.
However, Ono teaches a switch comprising first and second NMOS switching transistors (M8, M9) having their sources connected together at connection point N7 (paras. [0164]-[0166]), and gate-control circuitry comprising PMOS transistor M3/current source M5 and NMOS transistor M4/current source M6 (paras. [0168]-[0171]). Ono teaches generating a voltage above connection point N7 by Vgs3 to turn NMOS transistors M8 and M9 on (paras. [0169], [0175]-[0178]) and generating a voltage below connection point N7 by Vgs4 to turn NMOS transistors M8 and M9 off (paras. [0179]-[0180]).
Given the teachings of Ono, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the voltage generation circuitry of Tanaka with the gate-control circuitry taught by Ono to provide respective higher and lower gate-control voltages for selectively turning the gating transistors on and off.
Doing so would permit the gate-source control voltage to be selected according to the particular switching application and thereby increase design flexibility, as taught by Ono (para. [0178]).
Re 2, Tanaka as modified by Ono teaches, wherein when the voltage of the ith battery is detected, the voltages at two ends of the ith battery are connected to the sensing circuit by turning on respective gating switches, wherein control part 50 selects voltage input nodes NCk and NCk-1 corresponding to the terminals of a selected battery cell and turns on respective switches SAk/SBk-1 or SAk-1/SBk depending upon the selected connection pattern (Figs. 5A-5B; paras. [0077]-[0086]).
Re 3, Tanaka as modified by Ono teaches, wherein the ith gating switch comprises a first transistor and a second transistor (Qn1, Qn2), the sources of the first transistor and second transistor being connected in common and the opposite drain terminals forming respective switch terminals T1 and T2 (Fig. 2A; paras. [0054]-[0056]).
Re 4 Tanaka as modified by Ono teaches, wherein the ith protection circuit comprises a protection diode/constant-voltage element (D1), such as a Zener diode, connected between the common source node and common gate node of the first and second transistors (Qn1, Qn2), for limiting the gate-source voltage of Qn1 and Qn2 to a fixed value (Fig. 2A; paras. [0055]-[0056]).
Re 5, Tanaka as modified by Ono teaches a voltage generation circuit (CM1) configured to provide a gate-source bias to turn first and second gating transistors (Qn1, Qn2) on, wherein CM1 supplies drive current Ic1 from potential Vh, which is sufficiently higher than the potentials of switch terminals T1 and T2, thereby developing a gate-source voltage across Qn1 and Qn2 (Fig. 2A; paras. [0055]-[0056]). Tanaka further teaches selectively enabling and disabling generation of drive current Ic1 through transistor Qn5 (paras. [0058]-[0062]).
Tanaka fails to expressly disclose generating the claimed lower control voltage for turning the first and second transistors off.
However, Ono teaches first and second NMOS switching transistors (M8, M9) having common sources at connection point N7 (paras. [0164]-[0166]), wherein PMOS transistor M3 and current source M5 operate as a source follower to provide a voltage above N7 by Vgs3 and thereby turn M8 and M9 on (paras. [0168]-[0169], [0175]-[0178]), and NMOS transistor M4 and current source M6 operate as a source follower to provide a voltage below N7 by Vgs4 and thereby turn M8 and M9 off (paras. [0170]-[0171], [0179]-[0180]).
Given the teachings of Ono, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the voltage generation circuit of Tanaka to provide a respective higher gate-control voltage for turning the gating transistors on and a lower gate-control voltage for turning the gating transistors off.
Doing so would permit the gate-source voltage to be selected according to the desired switching operation and application, as expressly taught by Ono (para. [0178]).
Re 6 Tanaka as modified by Ono teaches a voltage generation circuit (CM1) selectively controlled to generate a gate-source bias for turning first and second gating transistors (Qn1, Qn2) on, wherein generation of drive current Ic1 is controlled by transistor Qn5 in response to control signal Sc (paras. [0055]-[0062]).
Tanaka fails to expressly disclose affirmatively generating both the claimed turn-on voltage and the claimed turn-off voltage.
However, Ono teaches gate-control circuitry for NMOS transistors M8 and M9 wherein PMOS transistor M3/current source M5 generates a first gate-control voltage that turns M8 and M9 on and NMOS transistor M4/current source M6 generates a second gate-control voltage that turns M8 and M9 off (paras. [0168]-[0171], [0175]-[0180]).
Given the teachings of Ono, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to modify the voltage generation circuitry of Tanaka with Ono's respective on-state and off-state gate-control circuitry.
Doing so would permit selective generation of gate-control voltages corresponding to conducting and non-conducting states of the semiconductor switch.
Claim 7 is rejected under 35 U.S.C. 103(a) as being unpatentable over Tanaka as modified by Ono as applied to claim 5 above, and further in view of Ishikawa et al (JP2005017289).
Tanaka's invention as modified by Ono discloses all of the claimed limitations from above except for the ith voltage generation circuit comprising a capacitor wherein the control voltage is provided through charging and discharging of the capacitor.
However, Ishikawa teaches a switching circuit comprising semiconductor switches, a resistor provided between the source and gate of the semiconductor switches, a drive capacitor connected across the resistor, and an oscillator circuit configured to apply an AC voltage across the resistor through the drive capacitor, whereby a source-gate bias is applied to turn the semiconductor switches on (paras. [0013]-[0014]).
Given the teachings of Ishikawa, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to further modify the voltage generation circuit of Tanaka as modified by Ono with the drive capacitor of Ishikawa for providing the gate-control bias to the switching transistors.
Doing so would DC-isolate the oscillator/drive circuitry from the assembled battery, thereby permitting the oscillator circuitry to operate from a separate low-voltage power supply and providing a simple, low-cost switching circuit.
Claims 16, 19, 20 are rejected under 35 U.S.C. 103(a) as being unpatentable over Tanaka in view of Ono, and further in view of Hartzog et al. (US 7,679,369 B2).
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Tanaka in view of Ono, and further in view of Hartzog et al. (US 7,679,369 B2).
Tanaka as modified by Ono teaches a battery management system comprising the detection and gating module according to claim 1, wherein the detection and gating module selectively detects the voltage of each battery in a battery pack containing series-connected batteries (CEL1-CELn; switch part 10; voltage sensing part 20; Fig. 1; Tanaka paras. [0050]-[0053], [0077]-[0086]).
Tanaka as modified by Ono fails to disclose the claimed voltage amplification module configured to receive the selected battery voltage and amplify and output the battery voltage.
However, Hartzog teaches a system (10) for measuring the voltages of series-connected cells (12) comprising a flying capacitor (22) and amplifier/operational amplifier (34), wherein operational amplifier 34 amplifies the voltage of capacitor 22 and outputs an amplified voltage signal proportionally corresponding to the voltage of capacitor 22 and the cell 12 that charged capacitor 22 (col. 5, ln. 49-67; col. 6, ln. 1-5). Hartzog further teaches an ADC 36 connected to the output of operational amplifier 34 for converting the analog voltage signal into digital data (col. 6, ln. 7-25).
Given the teachings of Hartzog, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to further modify the battery-voltage sensing system of Tanaka as modified by Ono with the voltage amplification module (operational amplifier 34).
Doing so would provide an analog voltage signal proportional to the selected battery-cell voltage for subsequent analog-to-digital conversion.
Re 19, Tanaka as modified by Ono and Hartzog teaches, wherein in the detection and gating module, when the voltage of the ith battery is detected, respective voltage nodes at the two ends of the selected battery cell are connected to the sensing circuit through respective gating switches, wherein control part 50 selects voltage input nodes NCk and NCk-1 and turns on switches SAk/SBk-1 or SAk-1/SBk depending upon the connection pattern (Figs. 5A-5B; Tanaka paras. [0077]-[0086]).
Re 20, Tanaka as modified by Ono and Hartzog teaches, wherein the ith gating switch comprises a first transistor and a second transistor (Qn1, Qn2), the sources of the first and second transistors being connected in common and the opposite drains forming respective switch terminals T1 and T2 (Fig. 2A; Tanaka paras. [0054]-[0056]).
Allowable Subject Matter
Claims 8-15, 17, 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the cited prior art disclose, teach, suggest at least ith voltage generation circuit structure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Christle I. Marshall whose telephone number is (571) 270-3086. The examiner can normally be reached on Monday – Friday 7:30AM - 4:00PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Paik can be reached on (571) 272-2404. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Christle I Marshall/
Primary Examiner, Art Unit 2876
Prosecution Insights