Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the amendment filed on 10/10/2025.
Claim Objections
Claims 21 and 22 are objected to because of the following informalities: Regarding claim 21, in line 13, “the voltage at the second node” appears that it should read as “a voltage at the second node”. Regarding claim 22, the claim appears to fail to further limit parent claim 21, as the limitations of claim 22 are recited verbatim in claim 21. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-15, 21, and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al. (US Patent Application Publication US 2005/0184713 A1, hereinafter “Xu”) in view of Achleitner et al. (WO 2007/124518, hereinafter “Achleitner”). Regarding claim 1, Xu discloses (see Fig. 11) a voltage converter (two-stage voltage regulator of Fig. 5), comprising: a first stage including (stage comprising Q11, Q12, L11, Cbus) first and second switches (Q11, Q12) having a first voltage rating (30V, see [0070]), the first switch connected between an input voltage (Vin) and a first node (common node of Q11 and Q12), and the second switch connected between the first node and a potential (ground); a first inductor (L11) connected between the first node and the second node (node of Vbus); a first capacitor (Cbus) connected between the second node and the potential (Cbus is connected between the node of Vbus and ground); a second stage including (comprising Q1, Q2, L1, Co) third and fourth switches (Q1, Q2) having a second voltage rating (12-15V, see [0070]) that is less than the first voltage rating (5-15V is less than 30V), the third switch connected between the second node and a third node (common node of Q1 and Q2), and the fourth switch connected between the third node and the potential (Q2 is connected between the common node of Q1 and Q2 and ground); and a switch control module (comprising 130, 160) configured to complementarily switch the first and second switches to regulate a voltage at the second node (Vbus) toward a target voltage (Vref; the first stage buck converter comprising Q11, Q12, L11, Cbus, and 130 is operated to convert Vin to Vbus by complementarily switching Q11 and Q12, where Vbus is regulated towards Vref). Xu does not disclose a bypass switch connected between the input voltage and a second node, wherein the switch control module is configured to, in response to the input voltage becoming greater than a predetermined voltage: open the bypass switch; and operate the first stage and the second stage in series. However, Achleitner teaches (see Fig. 1 and Fig. 2) a bypass switch (11) connected between the input voltage (UDC) and a second node (UDC’), wherein the method comprises: in response to the input voltage becoming greater than a predetermined voltage (see p. 1 lines 2-9 “The invention relates to a method for converting an input DC voltage generated by a solar cell into an AC voltage with the aid of an inverter, wherein a step-down converter with at least one switching element is activated when the input DC voltage rises above a limit value and in this case the DC input voltage is converted into a DC voltage, which is suitable for a downstream bridge circuit for converting this DC voltage into the AC voltage.”): open the bypass switch; and operate the first stage and the second stage in series (see p. 1 lines 2-9 “The invention relates to a method for converting an input DC voltage generated by a solar cell into an AC voltage with the aid of an inverter, wherein a step-down converter with at least one switching element is activated when the input DC voltage rises above a limit value and in this case the DC input voltage is converted into a DC voltage, which is suitable for a downstream bridge circuit for converting this DC voltage into the AC voltage.”). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage converter of Xu to include a bypass switch connected between the input voltage and a second node, wherein the switch control module is configured to, in response to the input voltage becoming greater than a predetermined voltage: open the bypass switch; and operate the first stage and the second stage in series, as taught by Achleitner, because it can help increase the overall conversion efficiency when the input voltage enters a certain range where bypassing/operating the first stage is more efficient than operating/bypassing the first stage.
Regarding claim 2, Xu discloses (see Fig. 11) further comprising a second capacitor (Co) and a second inductor (L1), wherein: the second inductor is connected between the third node and an output node (node of Vol L1 is connected between the common node of Q1 and Q2 and node of Vo); and the second capacitor is connected between the output node and the potential (Co is connected between Vo and ground).
Regarding claim 3, Xu dose not disclose wherein the predetermined voltage is greater than and equal to the target voltage.
However, Achleitner teaches (see Fig. 1 and Fig. 2) wherein the predetermined voltage is greater than and equal to the target voltage (see p. 1 lines 2-9 “The invention relates to a method for converting an input DC voltage generated by a solar cell into an AC voltage with the aid of an inverter, wherein a step-down converter with at least one switching element is activated when the input DC voltage rises above a limit value and in this case the DC input voltage is converted into a DC voltage, which is suitable for a downstream bridge circuit for converting this DC voltage into the AC voltage.”). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage converter of Xu wherein the predetermined voltage is greater than and equal to the target voltage, as taught by Achleitner, because it can help increase the overall conversion efficiency when the input voltage enters a certain range where bypassing/operating the first stage is more efficient than operating/bypassing the first stage.
Regarding claim 4, Xu discloses (see Fig. 11) wherein the predetermined voltage (Vbus is 3 V to 6V, see Fig. 12, Examiner’s Note: Vbus is the equivalent to the predetermined voltage of when the first stage operates in the buck mode, since the first stage being a buck converter only can convert the input voltage to the same or lower output voltage, i.e. the output voltage level (Vbus in Fig. 11) being the lowest the input voltage level (Vin in Fig. 11) can be for a buck converter to properly operate) is less than the second voltage rating of the third and fourth switches (12-15V, see [0072]; 3-6V is less than 12-15V).
Regarding claim 5, Xu discloses (see Fig. 11) wherein the switch control module (comprising 130) is configured to complementarily switch the first and second switches at a frequency (the first stage buck converter comprising Q11, Q12, L11, Cbus, and 130 is operated to convert Vin to Vbus by complementarily switching Q11 and Q12 at a frequency of RAMP GEN 155). Xu does not disclose wherein the frequency is at least 2 megahertz. However, Xu teaches the benefits of increased switching frequency, i.e. allowing for smaller output capacitors and inductors to reduce current ripple and offering faster transient response (see [0071] “This enormous increase in frequency provides other benefits such as allowing for smaller output capacitors and inductors to reduce current ripple, and offering faster transient response.”). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage converter of Xu wherein the switching frequency of the first and second switches is at least 2 megahertz, according to the teachings of Xu, because it can allow for smaller output capacitors and inductors to reduce current ripple and offer faster transient response. Further, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Regarding claim 6, Xu discloses (see Fig. 11) wherein the switch control module is configured to complementarily switch the first and second switches at a frequency that is less than or equal to 8 megahertz (the first stage is switched at 370 kHz, i.e. see Fig. 3A, which is less than 8 MHz).
Regarding claim 7, Xu does not disclose wherein the switch control module is configured to, when the input voltage is less than the predetermined voltage, open the first and second switches and close the bypass switch, thereby bypassing the first stage. However, Achleitner teaches (see Fig. 1 and Fig. 2) wherein the switch control module (12) is configured to, when the input voltage is less than the predetermined voltage, open the first and second switches and close the bypass switch, thereby bypassing the first stage (see p.2 line 25 – p.3 line 12 “if the input DC voltage is below a certain limit, the buck converter is not activated or switched through the switching element of the buck converter. However, the occurring losses of the switching element of the buck converter would reduce the efficiency. By bridging the at least one switching element of the buck converter according to the invention when it is inactivated, the efficiency can thus be increased in a simple manner by reducing the switching losses of the switching element.” And “The control of the bridging of the at least one switching element of the buck converter can be done by measuring the DC input voltage and bridging the at least one switching element of the buck converter when the DC input voltage is below the limit which is decisive for the activation or deactivation of the buck converter. ”). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage converter of Xu wherein the switch control module is configured to, when the input voltage is less than the predetermined voltage, open the first and second switches and close the bypass switch, thereby bypassing the first stage, as taught by Achleitner, because it can help increase the overall conversion efficiency when the input voltage enters a certain range where bypassing/operating the first stage is more efficient than operating/bypassing the first stage.
Regarding claim 8, Xu discloses (see Fig. 11) wherein the switch control module is further configured to complementarily switch the third and fourth switches based on adjusting a voltage at an output node (voltage at Vo) toward or to a target voltage (VID; 160 complementarily switches Q1 and Q2 to adjust the voltage at Vo towards VID).
Regarding claim 9, Xu discloses (see Fig. 11) wherein the switch control module is configured to complementarily switch the third and fourth switches based on adjusting the voltage at the output node toward or to the target voltage (160 complementarily switches Q1 and Q2 to adjust the voltage at Vo towards VID) while complementarily switching the first and second switches (while 130 complementarily switches Q11 and Q12 to generated Vbus from Vin).
Regarding claim 10, Xu discloses (see Fig. 11) wherein the target voltage is less than the second voltage rating (the target voltage is 1.29 V, i.e. see Fig. 12, which is less than 12-15V).
Regarding claim 11, Xu discloses (see Fig. 11) wherein the target voltage is between 1 and 9 volts, inclusive (the target voltage is 1.29 V, i.e. see Fig. 12, which is between 1 V and 9 V).
Regarding claim 12, Xu discloses (see Fig. 11) wherein the first voltage rating is at least 30 volts (30V, see [0070]) and the second voltage rating is at least 12 volts (12-15V, see [0070]).
Regarding claim 13, Xu discloses (see Fig. 11) wherein the first voltage rating is greater than the target voltage at the second node (Vref is the target voltage at the second node, i.e. target of Vbus, which is 3 – 6V, see Fig. 12, where the first voltage rating is 30 V – greater than 3 – 6V).
Regarding claim 14, Xu discloses (see Fig. 11) wherein the second voltage rating is greater than the target voltage at the second node (Vref is the target voltage at the second node, i.e. target of Vbus, which is 3 – 6V, see Fig. 12, where the second voltage rating is 12-15 V – greater than 3 – 6V).
Regarding claim 15, Xu discloses (see Fig. 11) wherein the first, second, third, and fourth switches are field effect transistors (FETs) (Q1, Q2, Q11, Q12 are MOSFETs, see Fig. 11).
Regarding claim 21, Xu discloses (see Fig. 11) a method of operating a voltage converter (two-stage voltage regulator of Fig. 5) a first stage including (stage comprising Q11, Q12, L11, Cbus) first and second switches (Q11, Q12) having a first voltage rating (30V, see [0070]), the first switch connected between an input voltage (Vin) and a first node (common node of Q11 and Q12), and the second switch connected between the first node and a potential (ground), a first inductor (L11) connected between the first node and the second node (node of Vbus); a first capacitor (Cbus) connected between the second node and the potential (Cbus is connected between the node of Vbus and ground); a second stage including (comprising Q1, Q2, L1, Co) third and fourth switches (Q1, Q2) having a second voltage rating (12-15V, see [0070]) that is less than the first voltage rating (5-15V is less than 30V), the third switch connected between the second node and a third node (common node of Q1 and Q2), and the fourth switch connected between the third node and the potential (Q2 is connected between the common node of Q1 and Q2 and ground); and a switch control module (comprising 130, 160), the method comprising: complementarily switching the first and second switches to regulate a voltage at the second node (Vbus) toward a target voltage (Vref; the first stage buck converter comprising Q11, Q12, L11, Cbus, and 130 is operated to convert Vin to Vbus by complementarily switching Q11 and Q12, where Vbus is regulated towards Vref). Xu does not disclose a bypass switch connected between the input voltage and a second node, and wherein the method comprises: in response to the input voltage becoming greater than a predetermined voltage: opening the bypass switch; and operating the first stage and the second stage in series; and in response to the input voltage being less than the predetermined voltage: opening the first and second switches; and closing the bypass switch, thereby bypassing the first stage. However, Achleitner teaches (see Fig. 1 and Fig. 2) a bypass switch (11) connected between the input voltage (UDC) and a second node (UDC’), and wherein the method comprises: in response to the input voltage becoming greater than a predetermined voltage (see p. 1 lines 2-9 “The invention relates to a method for converting an input DC voltage generated by a solar cell into an AC voltage with the aid of an inverter, wherein a step-down converter with at least one switching element is activated when the input DC voltage rises above a limit value and in this case the DC input voltage is converted into a DC voltage, which is suitable for a downstream bridge circuit for converting this DC voltage into the AC voltage.”): opening the bypass switch; and operating the first stage and the second stage in series (see p. 1 lines 2-9 “The invention relates to a method for converting an input DC voltage generated by a solar cell into an AC voltage with the aid of an inverter, wherein a step-down converter with at least one switching element is activated when the input DC voltage rises above a limit value and in this case the DC input voltage is converted into a DC voltage, which is suitable for a downstream bridge circuit for converting this DC voltage into the AC voltage.”); and in response to the input voltage being less than the predetermined voltage: opening the first and second switches; and closing the bypass switch, thereby bypassing the first stage (see p.2 line 25 – p.3 line 12 “if the input DC voltage is below a certain limit, the buck converter is not activated or switched through the switching element of the buck converter. However, the occurring losses of the switching element of the buck converter would reduce the efficiency. By bridging the at least one switching element of the buck converter according to the invention when it is inactivated, the efficiency can thus be increased in a simple manner by reducing the switching losses of the switching element.” And “The control of the bridging of the at least one switching element of the buck converter can be done by measuring the DC input voltage and bridging the at least one switching element of the buck converter when the DC input voltage is below the limit which is decisive for the activation or deactivation of the buck converter. ”). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Xu to include a bypass switch connected between the input voltage and a second node, and wherein the method comprises: in response to the input voltage becoming greater than a predetermined voltage: opening the bypass switch; and operating the first stage and the second stage in series; and in response to the input voltage being less than the predetermined voltage: opening the first and second switches; and closing the bypass switch, thereby bypassing the first stage, as taught by Achleitner, because it can help increase the overall conversion efficiency when the input voltage enters a certain range where bypassing/operating the first stage is more efficient than operating/bypassing the first stage.
Regarding claim 22, Xu discloses (see Fig. 11) further comprising: in response to the input voltage being less than the predetermined voltage: opening the first and second switches and close the bypass switch, thereby bypassing the first stage (see p.2 line 25 – p.3 line 12 “if the input DC voltage is below a certain limit, the buck converter is not activated or switched through the switching element of the buck converter. However, the occurring losses of the switching element of the buck converter would reduce the efficiency. By bridging the at least one switching element of the buck converter according to the invention when it is inactivated, the efficiency can thus be increased in a simple manner by reducing the switching losses of the switching element.” And “The control of the bridging of the at least one switching element of the buck converter can be done by measuring the DC input voltage and bridging the at least one switching element of the buck converter when the DC input voltage is below the limit which is decisive for the activation or deactivation of the buck converter. ”).
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over Xu in view of Achleitner, and further in view of Chang et al. (US Patent Application Publication US 2022/0166339 A1, hereinafter “Chang”). Regarding claim 16, Xu does not disclose further comprising a capacitor connected between the third node and a fifth node, wherein the fourth switch is connected between the fifth node and the potential. However, Chang teaches (see Fig. 4) further comprising a capacitor (CF) connected between the third node (common node of M21 and M22) and a fifth node (common node of M23 and M24), wherein the fourth switch (M23) is connected between the fifth node and the potential (ground) (M23 is connected between the common node of M23 and M24 and ground). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage converter of Xu to further comprise a capacitor connected between the third node and a fifth node, wherein the fourth switch is connected between the fifth node and the potential, as taught by Chang, because it can help implement a step-down converter without using an inductor which can help reduce the size of the circuit. Regarding claim 17, Xu does not disclose a fifth switch connected between the third node and an output node; and a sixth switch connected between the fifth node and the output node. However, Chang teaches (see Fig. 4) a fifth switch (M22) connected between the third node (common node of M21 and M22) and an output node (VCH); and a sixth switch (M24) connected between the fifth node (common node of M23 and M24) and the output node (VCH) (M24 is connected between the common node of M23 and M24 and VCH). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage converter of Xu to include a fifth switch connected between the third node and an output node; and a sixth switch connected between the fifth node and the output node, as taught by Chang, because it can help implement a step-down converter without using an inductor which can help reduce the size of the circuit. Regarding claim 18, Xu does not disclose further comprising an output capacitor connected between the output node and the potential. However, Chang teaches (see Fig. 4) further comprising an output capacitor (right-side capacitor of 206) connected between the output node (VCH) and the potential (ground). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage converter of Xu to further comprise an output capacitor connected between the output node and the potential, as taught by Chang, because it can help implement a step-down converter without using an inductor which can help reduce the size of the circuit. Regarding claim 19, Xu does not disclose wherein the fifth and sixth switches have the second voltage rating that is less than the first voltage rating. However, Chang teaches (see Fig. 4) fifth (M22) and sixth switches (M24). Further, Xu teaches wherein the second stage switch devices have lower ratings (12-15V) than the first stage (30V) (see [0070] “An important consequence of the present 2-stage regulator is that the second stage operates at a reduced voltage, and can therefore employ switches with a reduced voltage rating. For example, in a prior art single stage regulator, 30 volt switches may be required, which tend to have high internal resistance values (Rds-on values). By comparison, in the present invention, since the second stage regulator may operate at a nominal voltage in the range of 3-6 volts, lower voltage rating switches (e.g. rated at 12-15 volts) can be used. Low voltage rating switches tend to have much lower internal resistance values, and consequently lower conduction losses.”) Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage converter of Xu wherein the fifth and sixth switches have the second voltage rating that is less than the first voltage rating, as taught by Chang and the teaching of Xu, because it can help implement the voltage converter with lower voltage rating switches which tend to have much lower internal resistance values, and consequently lower conduction losses (see [0070] of Xu). Regarding claim 20, Xu does not disclose wherein the switch control module is configured to: open the third and sixth switches while the fourth and fifth switches are closed; and open the fourth and fifth switches while the third and sixth switches are closed. However, Chang teaches (see Fig. 4) wherein the switch control module is configured to: open the third (M21) and sixth switches (M24) while the fourth (M23) and fifth switches (M22) are closed; and open the fourth and fifth switches while the third and sixth switches are closed (see [0046] “More specifically, in this embodiment, the control circuit 207 controls the switching devices M21, M22, M23 and M24 of the capacitive switching power converter 206, so that one end of the conversion capacitor CF is switched periodically between the first voltage V1 in a first charging conversion interval (e.g., PH1) and the charging voltage VCH in a second charging conversion interval (e.g., PH2). In addition, the control circuit 207 controls the switching devices M21, M22, M23 and M24 of the capacitive switching power converter 206, so that another end of the conversion capacitor CF is switched periodically between the charging voltage VCH in the first charging conversion interval PH1 and the ground level in the second charging conversion interval PH2. As the result, the charging voltage VCH of the charging power is ½-fold of the first voltage V1 of the first power, whereas, the charging current ICH of the charging power is 2-fold of the first current Il of the first power.”). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the voltage converter of Xu wherein the switch control module is configured to: open the third and sixth switches while the fourth and fifth switches are closed; and open the fourth and fifth switches while the third and sixth switches are closed, as taught by Chang, because it can help implement a step-down converter without using an inductor which can help reduce the size of the circuit.
Response to Arguments
Applicant’s arguments with respect to the claims have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JYE-JUNE LEE/Examiner, Art Unit 2838
/JUE ZHANG/Primary Examiner, Art Unit 2838
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