DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
2. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claims 1, 4, 5, 7, 9, 13, 15, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Muchherla (US 20190066739) and in view of Padilla (US 20180374549) and further in view of Kumar (US 20190066809) and further in view of Chen (US 20180197619)
Claim 1. Muchherla discloses A memory device (eg., memory device 400, Fig 4) comprising:
a memory array including memory cells (eg., memory array 402 having a plurality of memory cells 404, 0050 Fig. 4);
a memory controller operatively coupled to the memory array and including a processor, the processor configured to: (eg., a memory controller 115 , 0025 Fig. 1; array controller 135 , 0030 Fig. 1))
initiate read operations to the memory array (eg., reading data from, or erasing one or more memory cells of the memory device 110, 0030 Fig. 1);
compare the number of read operations performed on a block of memory cells of the memory array, to a predetermined threshold number of read operations (eg., read tracker 646 can include a counter to count a number of read operations to read at least a portion of the memory device, 0069; Calibration controller 644 can be arranged to trigger a read level calibration of memory device 642 based on inputs from the one or more trackers 646, 648, and 649 and a determination of an occurrence of at least one event from a set of events…., the number of the read operations equal to or exceeding a predetermined threshold for a number of read operations, 0070);
in response to reaching the threshold number of read operations (eg., 0076 - If the current count of reads is greater than the predetermined threshold for reads, this status can be provided to calibration controller 744, and calibration controller 744 can trigger a read level calibration of NAND 742.)
and not scanning when the threshold number of read operations is not reached (eg., 0076 - If the current count of reads is not greater than the predetermined threshold for reads from NAND 742, this status need not be provided to calibration controller 744 and NAND read counter 746 continues to track the number of reads.)
Muchherla does not disclose, but Padilla discloses
scan first, second and third memory pages of the block of memory cells for errors … for the block, (eg., 0013 - word line scans to detect localized read disturb effects before they become problematic (e.g., before uncorrectable bit errors occur). The word line scan can determine an error count (e.g., an RBER) for each word line in a tracked subset of memory addresses (e.g., a single memory block, a group of memory blocks, a memory superblock, a group of word lines corresponding to less than a memory block, etc.) ; 0014, 0029 If, however, the evaluation (box 306) determines that the read count exceeds the first threshold value, the method can include performing a word line scan (box 308) of the tracked subset to determine an error count corresponding to each word line in the tracked subset),
wherein the first memory page is attached to a first activation line associated with a previous read operation included in the threshold number of read operations, and the second memory page and the third memory page are attached to different neighboring activation lines of the first activation line (eg., determining (block 402) a read count for a tracked subset of memory addresses corresponding to more than one word line (e.g., a subset of the memory addresses of the memory device corresponding to a single memory block, to multiple memory blocks, to a memory superblock, to a plurality of pages across a number of word lines comprising less than a memory block, etc.). , 0034 Fig. 4); and
iteratively change the threshold number to a new threshold number, perform the new threshold number of read operations on the block of memory cells, and error scan first, second and third memory pages associated with the last read operation of the new threshold number of read operations (eg., 0036 - adjusting (box 413) the first threshold value based on the determined error count. For example, if the determined error count is less than half of the second threshold value, the first threshold value may be increased by a larger amount (e.g., permitting another 10000 read operations to occur before the word line scan for the current tracked subset is performed again), whereas if the determined error count is greater than or equal to half of the second threshold value, the first threshold value may be increased by a smaller amount (e.g., only permitting another 2000 read operations to occur before the word line scan for the current tracked subset is performed again)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, providing the benefit of methods of read disturb mitigation and memory devices (see Padilla, 0001) all of the tracked subsets of memory addresses of a memory device, in other embodiments a memory device can track multiple first threshold values, each corresponding to one or more tracked subsets (0031).
Muchherla in view of Padilla does not disclose, but Kumar discloses
wherein the first memory page, and the second memory page are attached to different neighboring access lines of a first access line used in a last read operation of the threshold number of read operations, the third memory page is attached to an access line experiencing more errors than the first and neighboring access lines, and (eg., 0043 - et of initial test pages is referred to as such because those pages are the ones that are tested at first. the block begins (ends) with a single MSB page which is not in the set of initial test pages (shown in white), followed by 2 MSB pages which are in the set (shown in grey),; [0044] When a read (e.g., initiated by a host) is performed on a given page, the pages above and below are the most vulnerable to read disturb noise.; 0077 - If the number of bit errors reaches a multiple of a bit error threshold, also referred to as a read threshold, which can be obtained, for example, from registers 1014, which are programmable), then the test controller flags the tested page (e.g., the initial test page or the adjacent page) as a candidate for a read reclaim operation. )
wherein the first, second, and third memory pages are less than a number of memory pages tracked for the read operations; (eg., 0043 Fig. 3 - [0043] FIG. 3 illustrates an example of an initial set of test pages in a block … The set of initial test pages is referred to as such because those pages are the ones that are tested at first)(further, 0058 Fig. 8 - selecting a second read threshold as a target read threshold based on bit errors associated with the first block (812). ; 0062 - an adaptive read threshold value … an aggressive frequency of read checks and lower value of (Cth) are selected, if the number of errors in read check crosses a certain threshold and higher values are chosen leading to fewer read checks in a vice versa scenario. For example, the number of errors in the worst CSB pages in read check can be used to compare with certain thresholds.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, with Kumar, providing the benefit of desirable to reduce the overhead of testing every page (see Kumar, 0005) isolating only the cells which are being read… Improved read disturb detection and recovery (0004).
Muchherla in view of Padilla and Kumar does not disclose, but Chen discloses
when the threshold number is reached regardless of whether errors are found by the scan (eg., 0026 - read thresholds may be set dynamically for blocks or meta-blocks or other units of the memory to improve the optimization. Specifically, memory blocks or units may be organized and optimized dynamically with multiple read thresholds to avoid causing a high retry rate for different types of blocks (DR vs. RD blocks). The dynamic nature of the optimization takes feedback information and corrects the read threshold to minimize the retry rate.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, and Kumar with Chen, providing the benefit of improve the optimization (see Chen, 0026).
Claim 4. Muchherla does not disclose, but Padilla discloses
wherein the processor is configured to scan the memory page attached to the first access line (eg., 0013 - perform word line scans to detect localized read disturb effects).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, providing the benefit of methods of read disturb mitigation and memory devices (see Padilla, 0001) all of the tracked subsets of memory addresses of a memory device, in other embodiments a memory device can track multiple first threshold values, each corresponding to one or more tracked subsets (0031) Reducing the amount of data that is read from each word line during the word line scan can improve the speed of the scanning (0027).
Claim 5, Muchherla in view of Padilla does not disclose, but Kumar discloses
wherein the third memory page is attached to an access line included in a list of weaker activation lines Having an increase in errors greater relative to other access lines (eg., 0077 - If the number of bit errors reaches a multiple of a bit error threshold, also referred to as a read threshold, which can be obtained, for example, from registers 1014, which are programmable), then the test controller flags the tested page (e.g., the initial test page or the adjacent page) as a candidate for a read reclaim operation. )
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, with Kumar, providing the benefit of desirable to reduce the overhead of testing every page (see Kumar, 0005) isolating only the cells which are being read… Improved read disturb detection and recovery (0004).
Claim 7. Muchherla in view of Padilla and Kumar does not disclose, but Chen discloses
wherein the processor is configured to:monitor the number of erase operations of the block of memory cells; iteratively change the threshold number of read operations by iteratively selecting a random different number for the threshold number from a range of threshold numbers between a predetermined minimum threshold number and a predetermined maximum threshold number; and set the range of threshold numbers predetermined minimum threshold number and the predetermined maximum threshold number according to the number of erase operations (eg., optimize the setting of a read threshold or read level. A feedback mechanism may be used when there is a read retry error for dynamically providing the read threshold … range , 0020; the read thresholds may be set dynamically for blocks or meta-blocks or other units of the memory to improve the optimization. Specifically, memory blocks or units may be organized and optimized dynamically with multiple read thresholds to avoid causing a high retry rate for different types of blocks (DR vs. RD blocks). The dynamic nature of the optimization takes feedback information and corrects the read threshold to minimize the retry rate., 0026; 0073-0074).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, and Kumar with Chen, providing the benefit of to minimize the retry rate (see Chen, 0026) storage device with a memory may optimize the setting of a read threshold or read level (0020).
Claim 9. Muchherla discloses A method of operating a memory device (eg., memory device 400, Fig 4), the method comprising:
selecting a threshold number of read operations to be performed on a block of memory cells of the memory device, wherein the block of memory cells includes multiple pages of memory cells (eg., the number of the read operations equal to or exceeding a predetermined threshold for a number of read operations. for a read level calibration. The one or more trackers 646, 648, and 649, 0070; (e.g., read) one or more of the memory cells, planes, sub-blocks, blocks, or pages of the memory array. , 0027);
;and
in response to reaching the threshold number of read operations (eg., 0076 - If the current count of reads is greater than the predetermined threshold for reads, this status can be provided to calibration controller 744, and calibration controller 744 can trigger a read level calibration of NAND 742.)
and not scanning when the threshold number of read operations is not reached (eg., 0076 - If the current count of reads is not greater than the predetermined threshold for reads from NAND 742, this status need not be provided to calibration controller 744 and NAND read counter 746 continues to track the number of reads.)
Muchherla does not disclose, but Padilla discloses
scanning first, second and third pages of the multiple pages for errors, wherein the first page is attached to a first activation line associated with a last read operation of the threshold number of read operations, and the second page and the third page are attached to different neighboring activation lines of the first activation line (eg., If, however, the evaluation (box 306) determines that the read count exceeds the first threshold value, the method can include performing a word line scan (box 308) of the tracked subset to determine an error count corresponding to each word line in the tracked subset. T, 0029, 0014; Each word line can include one or more memory pages,, 0016),
wherein the first memory page is attached to a first activation line associated with a previous read operation included in the threshold number of read operations, and the second memory page and the third memory page are attached to different neighboring activation lines of the first activation line (eg., determining (block 402) a read count for a tracked subset of memory addresses corresponding to more than one word line (e.g., a subset of the memory addresses of the memory device corresponding to a single memory block, to multiple memory blocks, to a memory superblock, to a plurality of pages across a number of word lines comprising less than a memory block, etc.). , 0034 Fig. 4); and
iteratively change the threshold number to a new threshold number, perform the new threshold number of read operations on the block of memory cells, and error scan first, second and third memory pages associated with the last read operation of the new threshold number of read operations (eg., 0036 - adjusting (box 413) the first threshold value based on the determined error count. For example, if the determined error count is less than half of the second threshold value, the first threshold value may be increased by a larger amount (e.g., permitting another 10000 read operations to occur before the word line scan for the current tracked subset is performed again), whereas if the determined error count is greater than or equal to half of the second threshold value, the first threshold value may be increased by a smaller amount (e.g., only permitting another 2000 read operations to occur before the word line scan for the current tracked subset is performed again)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, providing the benefit of methods of read disturb mitigation and memory devices (see Padilla, 0001) all of the tracked subsets of memory addresses of a memory device, in other embodiments a memory device can track multiple first threshold values, each corresponding to one or more tracked subsets (0031).
Muchherla in view of Padilla does not disclose, but Kumar discloses
wherein the first page, and the second page are attached to different neighboring access lines of a first access line used in a last read operation of the threshold number of read operations, the third memory page is attached to an access line having more errors than the first and neighboring access lines, and (eg., 0043 - et of initial test pages is referred to as such because those pages are the ones that are tested at first. In the example shown, the block begins (ends) with a single MSB page which is not in the set of initial test pages (shown in white), followed by 2 MSB pages which are in the set (shown in grey),; [0044] When a read (e.g., initiated by a host) is performed on a given page, the pages above and below are the most vulnerable to read disturb noise. ; 0077 - If the number of bit errors reaches a multiple of a bit error threshold, also referred to as a read threshold, which can be obtained, for example, from registers 1014, which are programmable), then the test controller flags the tested page (e.g., the initial test page or the adjacent page) as a candidate for a read reclaim operation.)
wherein the first, second, and third memory pages are less than a number of memory pages tracked for the read operations; (eg., 0043 Fig. 3 - [0043] FIG. 3 illustrates an example of an initial set of test pages in a block … The set of initial test pages is referred to as such because those pages are the ones that are tested at first)(further, 0058 Fig. 8 - selecting a second read threshold as a target read threshold based on bit errors associated with the first block (812). ; 0062 - an adaptive read threshold value … an aggressive frequency of read checks and lower value of (Cth) are selected, if the number of errors in read check crosses a certain threshold and higher values are chosen leading to fewer read checks in a vice versa scenario. For example, the number of errors in the worst CSB pages in read check can be used to compare with certain thresholds.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, with Kumar, providing the benefit of desirable to reduce the overhead of testing every page (see Kumar, 0005) isolating only the cells which are being read… Improved read disturb detection and recovery (0004).
Muchherla in view of Padilla and Kumar does not disclose, but Chen discloses
when the threshold number is reached regardless of whether errors are found by the scan (eg., 0026 - read thresholds may be set dynamically for blocks or meta-blocks or other units of the memory to improve the optimization. Specifically, memory blocks or units may be organized and optimized dynamically with multiple read thresholds to avoid causing a high retry rate for different types of blocks (DR vs. RD blocks). The dynamic nature of the optimization takes feedback information and corrects the read threshold to minimize the retry rate.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, and Kumar with Chen, providing the benefit of improve the optimization (see Chen, 0026).
Claim 13 is rejected for reasons similar to Claim 7 above.
Claim 15. Muchherla discloses A non-transitory computer readable medium including instructions that, when performed by processing circuitry of a memory controller, cause the memory controller to perform acts (eg., memory device 400, Fig 4), comprising:
selecting a threshold number of read operations to be performed on a block of memory cells of a memory array operatively coupled to the memory controller, wherein the block of memory cells includes multiple pages of memory cells (eg., the number of the read operations equal to or exceeding a predetermined threshold for a number of read operations. for a read level calibration. The one or more trackers 646, 648, and 649, 0070; (e.g., read) one or more of the memory cells, planes, sub-blocks, blocks, or pages of the memory array. , 0027);
in response to reaching the threshold number of read operations (eg., 0076 - If the current count of reads is greater than the predetermined threshold for reads, this status can be provided to calibration controller 744, and calibration controller 744 can trigger a read level calibration of NAND 742.)
and not scanning when the threshold number of read operations is not reached (eg., 0076 - If the current count of reads is not greater than the predetermined threshold for reads from NAND 742, this status need not be provided to calibration controller 744 and NAND read counter 746 continues to track the number of reads.)
Muchherla does not disclose, but Padilla discloses
scanning first, second and third pages of the multiple pages for errors in response to reaching the threshold number of read operations, wherein the first page is attached to a first activation line associated with a last read operation of the threshold number of read operations, and the second page and the third page are attached to different neighboring activation lines of the first activation line (eg., If, however, the evaluation (box 306) determines that the read count exceeds the first threshold value, the method can include performing a word line scan (box 308) of the tracked subset to determine an error count corresponding to each word line in the tracked subset. T, 0029, 0014; Each word line can include one or more memory pages,, 0016),
wherein the first memory page is attached to a first activation line associated with a previous read operation included in the threshold number of read operations, and the second memory page and the third memory page are attached to different neighboring activation lines of the first activation line (eg., determining (block 402) a read count for a tracked subset of memory addresses corresponding to more than one word line (e.g., a subset of the memory addresses of the memory device corresponding to a single memory block, to multiple memory blocks, to a memory superblock, to a plurality of pages across a number of word lines comprising less than a memory block, etc.). , 0034 Fig. 4); and
iteratively change the threshold number to a new threshold number, perform the new threshold number of read operations on the block of memory cells, and error scan first, second and third memory pages associated with the last read operation of the new threshold number of read operations (eg., 0036 - adjusting (box 413) the first threshold value based on the determined error count. For example, if the determined error count is less than half of the second threshold value, the first threshold value may be increased by a larger amount (e.g., permitting another 10000 read operations to occur before the word line scan for the current tracked subset is performed again), whereas if the determined error count is greater than or equal to half of the second threshold value, the first threshold value may be increased by a smaller amount (e.g., only permitting another 2000 read operations to occur before the word line scan for the current tracked subset is performed again)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, providing the benefit of methods of read disturb mitigation and memory devices (see Padilla, 0001) all of the tracked subsets of memory addresses of a memory device, in other embodiments a memory device can track multiple first threshold values, each corresponding to one or more tracked subsets (0031).
Muchherla in view of Padilla does not disclose, but Kumar discloses
wherein the first page, and the second page are attached to different neighboring access lines of a first access line used in a last read operation of the threshold number of read operations, the third memory page is attached to an access line experiencing more errors than the first and neighboring access lines, and (eg., 0043 - et of initial test pages is referred to as such because those pages are the ones that are tested at first. In the example shown, the block begins (ends) with a single MSB page which is not in the set of initial test pages (shown in white), followed by 2 MSB pages which are in the set (shown in grey),; [0044] When a read (e.g., initiated by a host) is performed on a given page, the pages above and below are the most vulnerable to read disturb noise. ; 0077 - If the number of bit errors reaches a multiple of a bit error threshold, also referred to as a read threshold, which can be obtained, for example, from registers 1014, which are programmable), then the test controller flags the tested page (e.g., the initial test page or the adjacent page) as a candidate for a read reclaim operation. )
wherein the first, second, and third memory pages are less than a number of memory pages tracked for the read operations; (eg., 0043 Fig. 3 - [0043] FIG. 3 illustrates an example of an initial set of test pages in a block … The set of initial test pages is referred to as such because those pages are the ones that are tested at first)(further, 0058 Fig. 8 - selecting a second read threshold as a target read threshold based on bit errors associated with the first block (812). ; 0062 - an adaptive read threshold value … an aggressive frequency of read checks and lower value of (Cth) are selected, if the number of errors in read check crosses a certain threshold and higher values are chosen leading to fewer read checks in a vice versa scenario. For example, the number of errors in the worst CSB pages in read check can be used to compare with certain thresholds.)
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, with Kumar, providing the benefit of desirable to reduce the overhead of testing every page (see Kumar, 0005) isolating only the cells which are being read… Improved read disturb detection and recovery (0004).
Muchherla in view of Padilla and Kumar does not disclose, but Chen discloses
when the threshold number is reached regardless of whether errors are found by the scan (eg., 0026 - read thresholds may be set dynamically for blocks or meta-blocks or other units of the memory to improve the optimization. Specifically, memory blocks or units may be organized and optimized dynamically with multiple read thresholds to avoid causing a high retry rate for different types of blocks (DR vs. RD blocks). The dynamic nature of the optimization takes feedback information and corrects the read threshold to minimize the retry rate.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, and Kumar with Chen, providing the benefit of improve the optimization (see Chen, 0026).
Claim 19 is rejected for reasons similar to Claim 7 above.
9. Claims 2-3, 10-11, 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Muchherla (US 20190066739) and in view of Padilla (US 20180374549) and Kumar (cited above) and Chen (cited above) and further in view of Moshayedi (US 20090327804)
Claim 2. Muchherla does not disclose, but Padilla discloses
wherein the processor is configured to: compare a number of errors in the first, second, and third memory pages of the block of memory cells to a predetermined error count (eg., word line scans to detect localized read disturb effects before they become problematic (e.g., before uncorrectable bit errors occur). The word line scan can determine an error count (e.g., an RBER) for each word line in a tracked subset of memory addresses (e.g., a single memory block, a group of memory blocks, a memory superblock, a group of word lines corresponding to less than a memory block, etc.) and outputs a value corresponding to the error count of the word line with the highest error count (e.g. the word line that has experienced the largest amount of read disturb effects)… If the word line scan reveals an amount of errors that indicates that the data in the tracked subset is experiencing levels of read disturb effects that can cause errors, then a relocation operation can be performed, 0013); and
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, providing the benefit of methods of read disturb mitigation and memory devices (see Padilla, 0001) all of the tracked subsets of memory addresses of a memory device, in other embodiments a memory device can track multiple first threshold values, each corresponding to one or more tracked subsets (0031).
Muchherla in view of Padilla and Kumar and Chen does not disclose, but Moshayedi discloses
relocate valid data of the scanned first, second, and third pages to a different block of memory cells of the memory array when the error count of the first, second, and third pages reaches the predetermined error count (eg., only valid data segments are copied from one data block to another before the first data block is erased. Moreover, the valid data segments copied from the first data block to the destination data block may be combined with valid data segments from other data blocks, so that the destination data block is provided with enough valid data segments to fully populate the destination data block with valid data. The valid data segments may be copied from other data blocks that have been identified as containing dynamic or static data (e.g., as a result of a read error count of a time of last write operation), 0038).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, and Kumar and Chen with Moshayedi, providing the benefit of improved wear leveling in flash storage devices (see Moshayedi, 0002) providing improved wear leveling for flash storage devices. The wear leveling improves the lifespan of flash storage devices and improves the reliability of data access therefrom (0009).
Claim 3. Muchherla in view of Padilla and Kumar and Chen does not disclose, but Moshayedi discloses
wherein processor is configured to correct errors of the scanned first, second, and third pages, and relocate corrected data and (eg., Upon detecting the error, controller 101 may be configured to correct the data error in data segment 124 (e.g., by utilizing an error correction code, parity information, or the like). After correcting the data error, controller 101 may be configured to move the data from data segment 124 (or the entire data block 110.sub.1) to one or more data segments of an available data block, such as data block 110.sub.4., 0026).
the valid data to the different block of memory cells (eg., the valid data segments copied from the first data block to the destination data block may be combined with valid data segments from other data blocks, so that the destination data block is provided with enough valid data segments to fully populate the destination data block with valid data. The valid data segments may be copied from other data blocks that have been identified as containing dynamic or static data (e.g., as a result of a read error count of a time of last write operation), as appropriate, or may be copied from other data blocks based upon any one of a number of other selection criteria (e.g., data blocks containing the number of data segments necessary to fully populate the destination data block)., 0038).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, and Kumar and Chen with Moshayedi, providing the benefit of improved wear leveling in flash storage devices (see Moshayedi, 0002) providing improved wear leveling for flash storage devices. The wear leveling improves the lifespan of flash storage devices and improves the reliability of data access therefrom (0009)
Claim 10 is rejected for reasons similar to Claim 2 above.
Claim 11 is rejected for reasons similar to Claim 3 above.
Claim 16 is rejected for reasons similar to Claim 2 above.
Claim 17 is rejected for reasons similar to Claim 3 above.
10. Claims 6, 12, 18 are rejected under 35 U.S.C. 103 as being unpatentable over Muchherla (US 20190066739) and in view of Padilla (US 20180374549) and further in view of Kumar (cited above) and Chen (cited above) and Asano (US 20190287632)
Claim 6. Muchherla does not disclose, but Padilla discloses
wherein the processor is configured to iteratively change the value of the threshold number (eg., 0036 - adjusting (box 413) the first threshold value based on the determined error count. For example, if the determined error count is less than half of the second threshold value, the first threshold value may be increased by a larger amount (e.g., permitting another 10000 read operations to occur before the word line scan for the current tracked subset is performed again), whereas if the determined error count is greater than or equal to half of the second threshold value, the first threshold value may be increased by a smaller amount (e.g., only permitting another 2000 read operations to occur before the word line scan for the current tracked subset is performed again)).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, providing the benefit of methods of read disturb mitigation and memory devices (see Padilla, 0001) all of the tracked subsets of memory addresses of a memory device, in other embodiments a memory device can track multiple first threshold values, each corresponding to one or more tracked subsets (0031).
Muchherla in view of Padilla and Kumar and Chen does not disclose, but Asano discloses
of read operations by iteratively selecting different values of threshold numbers between a predetermined minimum and maximum value of threshold numbers (eg., 0051 - initial value setting circuit 221 randomly selects any number within a predetermined initial value range for each counting group; claim 6 - a threshold setting circuit configured to assign the threshold read count value for each group by randomly selecting numbers within the predetermined range.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, and Kumar, and Chen with Asano, providing the benefit of possible to prevent reliability reduction caused by the read disturb. It is also possible to significantly reduce the possibility that many counting groups will closely in time reach the refresh threshold (see Asano, 0075).
Claim 12 is rejected for reasons similar to Claim 6 above.
Claim 18 is rejected for reasons similar to Claim 6 above.
12. Claim 8, 14 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Muchherla (US 20190066739) and in view of Padilla (US 20180374549) and Kumar (cited above) and further in view of Chen (US 20180197619) and Asano (US 20190287632)
Claim 8. Muchherla in view of Padilla and Kumar does not disclose, but Chen discloses
wherein the processor is configured to:initialize the memory device; error scan, for a first N read operations after the initializing, memory cells of a page connected to an activation line of the read operation, and memory cells of pages connected to neighboring activation lines, wherein N is an integer greater than zero; and set the threshold number of read operation to after the N read operations (eg., optimize the setting of a read threshold or read level. A feedback mechanism may be used when there is a read retry error for dynamically providing the read threshold from the read retry. Specifically, recovery from a read failure can provide feedback information for dynamically optimizing read threshold values. The feedback information includes one or more candidate voltages that can be used as the read threshold value. This dynamic optimization may be referred to as Decision Assist Read Threshold adjustment (“DART”). DART candidate voltages start with the voltage level that is recovered from read failures but then a range around that value can be used. , 0020).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, and Kumar with Chen, providing the benefit of to minimize the retry rate (see Chen, 0026) storage device with a memory may optimize the setting of a read threshold or read level (0020.
Muchherla in view of Padilla and Kumar and Chen does not disclose, but Asano discloses
a number of read operations different from N (eg., 0051 - initial value setting circuit 221 randomly selects any number within a predetermined initial value range for each counting group; claim 6 - a threshold setting circuit configured to assign the threshold read count value for each group by randomly selecting numbers within the predetermined range.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, and Kumar, and Chen with Asano, providing the benefit of possible to prevent reliability reduction caused by the read disturb. It is also possible to significantly reduce the possibility that many counting groups will closely in time reach the refresh threshold (see Asano, 0075).
Claim 14 is rejected for reasons similar to Claim 8 above.
Claim 20 is rejected for reasons similar to Claim 8 above.
Response to Arguments
Applicant's arguments filed 10/16/2025 have been fully considered but they are not persuasive.
For claims 1, 9 and 15, Applicant argues that that the cited references do not disclose the amended limitations. The Office disagrees.
In the present OA, the updated combination of references render the amended limitations as obvious.
Muchherla discloses
and not scanning when the threshold number of read operations is not reached (eg., 0076 - If the current count of reads is not greater than the predetermined threshold for reads from NAND 742, this status need not be provided to calibration controller 744 and NAND read counter 746 continues to track the number of reads.)
Specifically, Muchherla in view of Padilla and Kumar does not disclose, but Chen discloses
when the threshold number is reached regardless of whether errors are found by the scan (eg., 0026 - read thresholds may be set dynamically for blocks or meta-blocks or other units of the memory to improve the optimization. Specifically, memory blocks or units may be organized and optimized dynamically with multiple read thresholds to avoid causing a high retry rate for different types of blocks (DR vs. RD blocks). The dynamic nature of the optimization takes feedback information and corrects the read threshold to minimize the retry rate.).
It would have been obvious to one of ordinary skill in the art prior to the filing date of the claimed invention to modify the memory device for tracking read counts of memory blocks as disclosed by Muchherla, with Padilla, and Kumar with Chen, providing the benefit of improve the optimization (see Chen, 0026).
Applicant’s arguments for dependent claims are based on their respective base independent claims, which are addressed above.
For Claims 2-8, 10-14, 16-20, Applicant’s arguments are based on dependency from base claims 1, 9 and/or 15 (addressed above).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/GAUTAM SAIN/Primary Examiner, Art Unit 2135
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