DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The amendment filed on 9 December 2025 has been entered.
Response to Arguments
Applicant’s arguments, see page 12, filed 9 December 2025, with respect to the rejection of claims 4-5 under 35 USC 112(b) have been fully considered and are persuasive. The 35 USC 112(b) rejection of claims 4-5 has been withdrawn. Specifically, the claims and specification were amended to remedy the issue.
Applicant's arguments filed 9 December 2025 have been fully considered but they are not persuasive.
Applicant argues that Shimizu does not teach “an orthographic projection of the bottom electrode layer on the base substrate is located within an outer boundary range of an orthographic projection of the partition part of a same subpixel on the base substrate and does not overlap with an outer boundary of the orthographic projection of the partition part of the same subpixel on the base substrate”. The examiner disagrees. Applicant points to Fig. 2a of the present application as illustrating the claimed subject matter, however, claim 1 includes the limitation “a bottom electrode laver and a partition laver arranged in layer configuration between the base substrate and the pixel defining layer, the bottom electrode layer being located between the base substrate and the partition layer”, which is untrue in Fig. 2a, as one can clearly see, the bottom electrode layer 22 is not between the base substrate 21 and the partition layer 25. The only embodiment of the invention that embodies the subject matter currently claimed in claim 1 is the intermediate product shown in Fig. 11C, and there is no clear difference between this embodiment and that of Shimizu at the same step of the process (see Shimizu Fig. 9).
Applicant points to surface 41b of the partition layer 41 of Shimizu overlapping the bottom electrode 22. However, the claim specifies that “an orthographic projection of the bottom electrode layer on the base substrate is located within an outer boundary range of an orthographic projection of the partition part of a same subpixel on the base substrate and does not overlap with an outer boundary of the orthographic projection of the partition part of the same subpixel on the base substrate”. As shown in Fig. 1 of Shimizu, it is the inner boundary range of each sub-pixel that overlaps the bottom electrodes; the outer boundary range of each sub-pixel extends past the boundary of the same sub-pixel and thus teaches the claimed subject matter. Further, as noted above, the limitation “a bottom electrode laver and a partition laver arranged in layer configuration between the base substrate and the pixel defining layer, the bottom electrode layer being located between the base substrate and the partition layer” is required in the present claim, thus Shimizu’s inner boundary of the partition layer overlapping the bottom electrode not only does not teach away from the claimed invention, it is a required limitation of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-8, 14-16, 18-21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shimizu (US 2018/0145115 A1).
With respect to claim 1: Shimizu teaches “a display substrate (Fig. 1), comprising: a base substrate (21); a pixel defining layer (41+42+43) arranged at one side of the base substrate (see Fig. 1), the pixel defining layer being configured for defining a plurality of opening areas (41a), and the opening area being configured for arranging a light emitting device (22+51+52+24); and a common transport layer (51) arranged at one side of the pixel defining layer away from the base substrate (see Figs. 1, 3); a bottom electrode layer (22) and a partition layer (41) arranged in layer configuration between the base substrate and the pixel defining layer (see Figs. 1, 3), the bottom electrode layer being located between the base substrate and the partition layer (see Fig. 3); wherein a surface of one side away from the base substrate of the pixel defining layer between at least two adjacent opening areas is covered by the common transport layer (see Fig. 1), and at least part of a side face of the pixel defining layer (side of 41) facing at least one opening area is not covered by the common transport layer (see Fig. 3); and orthographic projections of the common transport layers in the at least two adjacent opening areas on the base substrate and orthographic projections of the common transport layers on the pixel defining layers between the at least two adjacent opening areas on the base substrate are continuous (see Fig. 3); and an orthographic projection of the bottom electrode layer on the base substrate is located within an outer boundary range of an orthographic projection of the partition part of a same subpixel on the base substrate (see Fig. 1) and does not overlap with an outer boundary of the orthographic projection of the partition part of the same subpixel on the base substrate (see Fig. 1), wherein the outer boundary of the orthographic projection of the partition part of the same subpixel on the base substrate is a boundary of the orthographic projection of the partition part of the same subpixel close to the orthographic projection of the bottom electrode layer on the base substrate (see Fig. 1; note that since subpixels of a display are generally microscopic the outer boundary of the partition parts extending into adjacent subpixels are still considered close to the orthographic projection of the bottom electrode layer)”.
With respect to claim 2: Shimizu teaches “the display substrate according to claim 1 (see above), wherein the pixel defining layer comprises a partition structure (see Fig. 1), and the partition structure comprises: a partition groove (41a) arranged in a side face of the pixel defining layer facing the at least one opening area (see Fig. 3), and a notch of the partition groove facing the at least one opening area (see Fig. 3)”.
With respect to claim 3: Shimizu teaches “the display substrate according to claim 2 (see above), wherein an orthographic projection of the partition layer on the base substrate is located within an orthographic projection range of the pixel defining layer on the base substrate (see Fig. 2); and the partition layer is provided with a first end face facing the opening area (41a), the pixel defining layer located at one side of the partition layer away from the base substrate is provided with a second end face facing the opening area (42a), the first end face retracts in a direction away from the opening area relative to the second end face (see Fig. 3), and the first end face forms a groove bottom of the partition groove (see Fig. 3)”.
With respect to claim 6: Shimizu teaches “the display substrate according to claim 3 (see above), wherein the display substrate comprises a second active area (11R, 11G, or 11B); in the second active area, the bottom electrode layer comprises a second bottom electrode (see Fig. 1), and the plurality of opening areas comprise a second opening area (see Fig. 1); and an orthographic projection of the second bottom electrode on the base substrate covers an orthographic projection of the second opening area on the base substrate (see Fig. 1); and the display substrate further comprises: a thin film transistor layer (layer of 30) and an insulating layer (25) arranged in layer configuration between the base substrate and the bottom electrode layer (see Fig. 1), wherein the thin film transistor layer is located between the base substrate and the insulating layer (see Fig. 1); and the thin film transistor layer comprises: a second thin film transistor (30) and a second switching part (34 connected to 36) connected to a source electrode or a drain electrode (34 on other side) of the second thin film transistor; wherein orthographic projections of the second bottom electrode and the second switching part on the base substrate intersect or overlap (see Fig. 1), and the second bottom electrode and the second switching part are connected through a via hole (36) arranged on the insulating layer (see Fig. 1)”.
With respect to claim 7: Shimizu teaches “the display substrate according to claim 3, wherein a surface material of one side of the bottom electrode layer away from the base substrate comprises at least one of the following: a crystalline metallic oxide, an amorphous metallic oxide, a metal and residual particles of the partition layer (paragraph 52); and/or a material of the partition layer comprises at least one of the following: an amorphous metallic oxide, a metal, silicon oxide, silicon nitride and silicon oxynitride (paragraph 84); and/or a main material of the pixel defining layer is an organic material”.
With respect to claim 8: Shimizu teaches “the display substrate according to claim 1 (see above), wherein the display substrate further comprises: a composite electrode layer (22) arranged between the base substrate and the pixel defining layer (see Fig. 1); wherein the composite electrode layer comprises a plurality of composite electrodes (see Fig. 1), the composite electrode comprises a middle pattern (part of 22 in 41a) and an edge pattern surrounding the middle pattern (part of 22 under 42), orthographic projections of the middle pattern and the pixel defining layer on the base substrate do not intersect or overlap (see Fig. 2), and orthographic projections of at least part of the edge pattern and the pixel defining layer on the base substrate intersect or overlap (see Fig. 2); and the middle pattern and the edge pattern at least comprise a material with the same element (paragraph 53) but different structures (the edge pattern has via 36, the middle pattern does not), and the middle pattern and the edge pattern are at least partially located on a same surface of a same layer (see Fig. 2)”.
With respect to claim 14: Shimizu teaches “the display substrate according to claim 2 (see above), wherein a groove depth (L2) of the partition groove is greater than or equal to 0.1 micron, and less than or equal to 10 microns in a plane at which the base substrate is located (paragraph 84)”.
With respect to claim 15: Shimizu teaches “the display substrate according to claim 2 (see above), wherein a dimension (T1) of the partition groove is greater than or equal to 100 angstroms, and less than or equal to 10,000 angstroms in a normal direction of the base substrate (paragraph 84)”.
With respect to claim 16: Shimizu teaches “the display substrate according to claim 2 (see above), wherein the partition groove is a closed structure or a non-closed structure surrounding the opening area by one circle (paragraph 84)
With respect to claim 18: Shimizu teaches “the display substrate according to according to claim 1 (see above), wherein the display substrate further comprises: a top electrode layer (24) arranged at one side of the common transport layer away from the base substrate (see Fig. 1); wherein the top electrode layer in the at least two adjacent opening areas and the top electrode layer on the pixel defining layer between the at least two adjacent opening areas are at least partially lapped (see Fig. 1)”.
With respect to claim 19: Shimizu teaches “a display device (title), comprising the display substrate according to claim 1 (see above)”.
With respect to claim 20: Shimizu teaches “a manufacturing method (Figs. 2-10) of a display substrate (Fig. 1), comprising: providing a base substrate (25); forming a pixel defining layer (41+42+43) at one side of the base substrate (see Fig. 3), the pixel defining layer being configured for defining a plurality of opening areas (41a), and the opening area being configured for arranging a light emitting device (22+51+52+24); and forming a common transport layer (51) at one side of the pixel defining layer away from the base substrate (see Fig. 3); forming a bottom electrode laver (22) at one side of the base substrate (see Fig. 3); forming a partition material layer (41) at one side of the bottom electrode layer away from the base substrate (see Fig. 3) by patterning (Figs. 9-10); wherein a surface of one side away from the base substrate of the pixel defining layer between at least two adjacent opening areas is covered by the common transport layer (see Fig. 1), and at least part of a side face (face of 42) of the pixel defining layer facing at least one opening area is not covered by the common transport layer (see Fig. 3); and orthographic projections of the common transport layers in the at least two adjacent opening areas on the base substrate and orthographic projections of the common transport layers on the pixel defining layers between the at least two adjacent opening areas on the base substrate are continuous (see Figs. 1, 3); and an orthographic projection of the bottom electrode layer on the base substrate is located within an outer boundary range of an orthographic projection of the partition part of a same subpixel on the base substrate (see Fig. 1) and does not overlap with an outer boundary of the orthographic projection of the partition part of the same subpixel on the base substrate (see Fig. 1), wherein the outer boundary of the orthographic projection of the partition part of the same subpixel on the base substrate is a boundary of the orthographic projection of the partition part of the same subpixel close to the orthographic projection of the bottom electrode layer on the base substrate (see Fig. 1)”.
With respect to claim 21: Shimizu teaches “the manufacturing method according to claim 20 (see above), wherein the pixel defining layer comprises a partition structure (see Fig. 1), the partition structure comprises a partition groove (41b) arranged in a side face of the pixel defining layer facing the opening area (see Fig. 3), the bottom electrode laver comprises a plurality of bottom electrodes (see Fig. 1), and orthographic projections of the plurality of bottom electrodes on the base substrate covers orthographic projections of the plurality of opening areas on the base substrate (see Fig. 1); an orthographic projection of the partition material layer on the base substrate covers the orthographic projections of the plurality of bottom electrodes on the base substrate and the step of forming the pixel defining layer at one side of the base substrate comprises: forming a partition material layer (Figs. 6-10) at one side of the bottom electrode layer away from the base substrate by patterning (paragraph 107), an orthographic projection of the partition material layer on the base substrate covering the orthographic projections of the plurality of bottom electrodes on the base substrate (see Fig. 1); forming the pixel defining layer at one side of the partition material layer away from the base substrate (see Figs. 6-10); and etching the partition material layer located in the opening area to form a partition layer (paragraph 108); wherein an orthographic projection of the partition layer on the base substrate is located within an orthographic projection range of the pixel defining layer on the base substrate (see Fig. 1); and the partition layer is provided with a first end face facing the opening area (41b), the pixel defining layer located at one side of the partition layer away from the base substrate is provided with a second end face facing the opening area (42a), the first end face retracts in a direction away from the opening area relative to the second end face (see Fig. 3), and the first end face forms a groove bottom of the partition groove (see Fig. 3)”.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-5 are rejected under 35 U.S.C. 103 as being unpatentable over Shimizu as applied to claim 1 above, and further in view of Yang et al. (US 2021/0327976 A1), Pang (US 20150357388 A1) and Cai et al. (US 2017/0221762 A1).
With respect to claim 4: Shimizu teaches “the display substrate according to claim 3 (see above), wherein the display substrate comprises a first active area (11R, 11B, or 11G); in the first active area, the bottom electrode layer comprises a first bottom electrode (see Fig. 1), the plurality of opening areas comprise a first opening area (see Fig. 1), and the partition layer comprises a first partition part (see Fig. 1); and an orthographic projection of the first bottom electrode on the base substrate covers an orthographic projection of the first opening area on the base substrate (see Fig. 1), and the first partition part and the first bottom electrode are contacted with each other (see Fig. 3); and the display substrate further comprises: a thin film transistor layer (layer of 30) and an insulating layer (25) arranged in layer configuration between the base substrate and the bottom electrode layer, wherein the thin film transistor layer is located between the base substrate and the insulating layer (see Fig. 1); and the thin film transistor layer comprises: a first thin film transistor (30) and a first switching part (34 connected to 36) connected to a source electrode or a drain electrode (34 on other side) of the first thin film transistor; and orthographic projections of the first partition part and the first switching part on the base substrate intersect or overlap (see Fig. 1)”.
Shimizu does not specifically teach “wherein orthographic projections of the first bottom electrode and the first switching part on the base substrate do not intersect or overlap”.
However, Yang teaches “wherein orthographic projections (see Fig. 2) of the first bottom electrode (111) and the first switching part (21) on the base substrate (10) do not intersect or overlap (see Fig. 2)”.
It would have been obvious at the time the application was effectively filed for one of ordinary skill in the art to modify the display of Shimizu by not overlapping the first bottom electrode and first switching part as taught by Yang in order to avoid the transistor blocking light emission, thus permitting a double-sided display (Yang paragraphs 96-98).
Shimizu does not teach “the first partition part and the first switching part are connected through a via hole arranged on the insulating layer”.
However Pang teaches “the first partition part (431) and the first switching part (420) are connected through a via hole (see Figs. 1, 6b) arranged on the insulating layer (412)”.
It would have been obvious at the time the application was effectively filed for one of ordinary skill in the art to modify the display of Shimizu by allowing the material of the first partition part to connect to the first switching part as taught by Pang in order to prevent other materials from entering the through hole (Cai paragraphs 56-57).
With respect to claim 5: Shimizu in view of Yang, Pang, and Cai teaches “the display substrate according to claim 4 (see above)”.
Shimizu further teaches “the bottom electrode layer comprises a metallic material (paragraph 52), and the partition layer comprises a transparent conducting material (the portion of 51 formed in the partition layer is transparent conducting material; see paragraph 90)”.
Shimizu does not specifically teach “wherein the first active area is located within a transparent active area”.
However, Yang teaches “wherein the first active area is located within a transparent active area (paragraph 97)”.
It would have been obvious at the time the application was effectively filed for one of ordinary skill in the art to modify the display of Shimizu by not overlapping the first bottom electrode and first switching part as taught by Yang in order to avoid the transistor blocking light emission, thus permitting a double-sided display (Yang paragraphs 96-98).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Shimizu as applied to claims 1, 2 above, and further in view of Cai et al. (US 2017/0221762 A1).
With respect to claim 13: Shimizu teaches “the display substrate according to claim 2 (see above)”.
Shimizu does not specifically teach “wherein the display substrate further comprises: a filling layer arranged between the pixel defining layer and the common transport layer, wherein an orthographic projection of the filling layer on the base substrate and an orthographic projection of the partition groove on the base substrate intersect or overlap, and the filling layer is configured for filling the partition groove at a corresponding position”.
However, Cai teaches “wherein the display substrate (Fig. 1) further comprises: a filling layer (15) arranged between the pixel defining layer (11) and the common transport layer (12), wherein an orthographic projection of the filling layer on the base substrate and an orthographic projection of the partition groove on the base substrate intersect or overlap (see Figs. 1, 2), and the filling layer is configured for filling the partition groove at a corresponding position (see Fig. 1)”.
It would have been obvious at the time the application was effectively filed for one of ordinary skill in the art to modify the display of Shimizu by adding the filling layer of Cai in order to keep unwanted material out of the partition groove (Cai paragraphs 56-57).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Seong et al. (US 20230217721 A1), which teaches a light emitting display.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATHANIEL J. LEE whose telephone number is (571)270-5721. The examiner can normally be reached 9-5 EST M-F.
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/NATHANIEL J LEE/Examiner, Art Unit 2875
/ABDULMAJEED AZIZ/Supervisory Patent Examiner, Art Unit 2875