Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Note: The Examiner notes that claim language is extremely broad by using terms such as “plasma-etchable” and “plasma-resistant” however the materials of the rejection satisfy these requirements and if the Applicant wishes to narrow the limitations, then specific materials/etchants can be included in the claim language so that the specific materials/etchants can be addressed in the rejection. See case law, with regard to materials in the claims, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Claim(s) 1-7, 9, 14, 16-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shepard et al. (US 20160240692 A1) hereafter referred to as Shepard in view of Xianyu (US 20150179814 A1)
In regard to claim 1 Shepard teaches a method of producing an [see Fig. 6, see paragraph 0056, see Figs. 1-7] electronic device precursor, the method comprising:
(i) providing a plasma-etchable layer [see Fig. 2 “multilevel stack 200 includes a first two-dimensional layer 202 encapsulated between a second layer 204 and a third layer 206. The second layer 204 and third layer 206 can be insulating layers, The multilevel stack 200 is shown with three layers, but can also include more than three layers” “For example, the first two-dimensional layer can be, for example, graphene. The second and third materials can be, for example, hexagonal boron nitride” ] structure on a plasma-resistant [“substrate can be constructed from any suitable material including, for example, silicon or silicon dioxide”] substrate, wherein the layer structure has an exposed upper surface;
(ii) patterning a plasma-resistant dielectric [“A mask can be defined on the second layer (at 502). For example, a PMMA layer can be etched onto the second layer. The PMMA layer can be etched in an oxygen plasma. The PMMA layer can have a thickness of about 70 nm. Electron beam lithography can then be used to pattern a hydrogen silsesquioxane (HSQ) layer on the PMMA layer”] onto the exposed upper surface to form an intermediate [see Fig. 5B] having at least one covered region [center] and at least one uncovered region [periphery] of the layer structure;
(iii) subjecting the intermediate to plasma etching [see paragraph 0072 “The multilevel stack can then be etched (at 504). As illustrated in FIG. 5B, the mask protects the multilevel stack such that only regions of the multilevel stack outside the mask are etched. The stack can be etched using plasma etching”], whereby the at least one uncovered region of the layer structure is etched away to form at least one covered region [see Fig. 5B] of the layer structure having an exposed edge surface;
(iv) forming an ohmic contact [“With further reference to FIG. 1, a metal can be deposited to form an electrical contact (e.g., metal leads) (at 106). The metal can be deposited using, e.g., electron beam evaporation or thermal evaporation”] in direct contact with a portion of the exposed edge surface;
wherein the plasma-etchable layer structure comprises one or more graphene layers [“For example, the first two-dimensional layer can be, for example, graphene”] which extend across the covered regions of the layer structure to the [see Fig. 5B, Fig. 6] exposed edge surface;and
but does not state “by physical vapour deposition” and wherein, either before or after step (iv), the method further comprises (v) forming a coating layer to provide the covered region of the layer structure with a continuous air- resistant coating thereby enclosing the layer structure and protecting all remaining portions of the exposed edge surface.
See Shepard paragraph 0057 “multilevel stack 200 is shown with three layers, but can also include more than three layers. For example, multilevel stacks in accordance with other embodiments of the disclosed subject matter can include five, seven, or nine layers of two-dimensional layers”.
With regard to materials in the claims, the Examiner notes case law, it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
However these are commonly used fabrication steps known to a person of ordinary skill in the art, see Xianyu teaches see Fig. 6A-6J see paragraph 0060 “graphene layer 130” “insulating layer 140 may be, for example, a Si oxide, an Al oxide, an Hf oxide, or the like, but is not limited thereto. The insulating layer 140 may be formed by a method that does not damage the graphene layer 130, for example, evaporation. The evaporation may be electron-beam evaporation”, see Fig. 6E “capping layer 210 may be formed of an insulating material, such as a Si oxide, a Si nitride, or a Si oxynitride, and by using electron-beam evaporation method, for example”, see 120 is on the sides of graphene also, “capping layer 210 may firmly fix the graphene layer 130, the source electrode 120a, and the drain electrode 120b onto the second substrate 200. The capping layer 210 may prevent or inhibit the graphene layer 130 from peeling off from or being separated from the second substrate 200 during the manufacture of the graphene device. The shape of the capping layer 210 illustrated in FIG. 6F is an example, and may vary. For example, the shape of the capping layer 210 may be similar to that of the capping layer CP1' of FIG. 4”, see etching step in 6F, see 210 is a intermediate layer in this step. See “Referring to FIG. 6H, a passivation layer 240 may be formed to cover the gate 230 on the gate insulating layer 220. The passivation layer 240 may be formed of, for example, a Si oxide layer, a Si oxynitride layer, a Si nitride layer, or an organic layer, or may have a stacked structure including at least two layers from among these layers. [0091] Referring to FIG. 61, the passivation layer 240, the gate insulating layer 220, and the capping layer 210 may be partially etched to form first to third contact holes H1 to H3 ”, thus even here the 240 is a intermediate during etching, see “insulating layer 140 may be formed by an evaporation method as described above. The evaporation method may be a physical vapor deposition (PVD) process, and thus, a material of the insulating layer 140 may be deposited on an exposed upper surface of the first substrate 100”, see etch selectivity “sacrificial layer 110 is to be removed by etching in a subsequent process, and may be formed of a material that may be etched faster than the catalyst layer 120 or the graphene layer 130. In other words, the sacrificial layer 110 may be formed of a material having etch selectivity with respect to the other layers 120 to 140 of the stacked structure SS1. For example, the sacrificial layer 110 may be formed of a metallic material, e.g., titanium tungsten (TiW) or molybdenum (Mo), or a dielectric material, e.g., silicon oxide (SiO.sub.2). The sacrificial layer 110 may have a thickness of about several hundreds nm to about several .mu.m”, here also the sacrificial layer 110 is used during etching, see “Al oxide, the Hf oxide, and the Zr oxide may be formed by, for example, ALD”.
See Xianyu see Fig. 6I H1 and H2 are formed to make contacts as desired in the location as desired.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shepard to include commonly used dielectric masks/materials as taught by Xianyu and “by physical vapour deposition” and wherein, either before or after step (iv), the method further comprises (v) forming a coating layer to provide the covered region of the layer structure with a continuous air- resistant coating thereby enclosing the layer structure and protecting all remaining portions of the exposed edge surface.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that dielectric masks/materials as taught by Xianyu and PVD, ALD, sputtering are a standard deposition technique known to give excellent results for dielectric deposition for example for masking, and dielectric or passivation layers are commonly used protection layers for isolation of the device.
In regard to claim 2 Shepard and Xianyu as combined teaches wherein the plasma-resistant substrate is sapphire, silicon [see Shepard paragraph 0060 “substrate can be constructed from any suitable material including, for example, silicon or silicon dioxide”], silicon dioxide, silicon nitride, silicon carbide, germanium, or a III-V semiconductor.
In regard to claim 3 Shepard and Xianyu as combined teaches [see combination Xianyu, see dielectric masks such as oxide, nitride] wherein the plasma- resistant dielectric isand/or the coating layer [see combination Xianyu uses “sacrificial layer 110 may be formed of a material having etch selectivity with respect to the other layers 120 to 140 of the stacked structure SS1. For example, the sacrificial layer 110 may be formed of a metallic material, e.g., titanium tungsten (TiW) or molybdenum (Mo), or a dielectric material, e.g., silicon oxide (SiO.sub.2)”] are each an inorganic oxide, nitride, carbide, fluoride or sulphide.
In regard to claim 4 Shepard and Xianyu as combined teaches [see combination Xianyu, see Shepard paragraph 0072 “multilevel stack can then be etched (at 504). As illustrated in FIG. 5B, the mask protects the multilevel stack such that only regions of the multilevel stack outside the mask are etched. The stack can be etched using plasma etching. For example, the stack can be etched in an Oxford ICP 80 system using plasma generated from a mixture of O.sub.2 and CHF.sub.3 gases”] wherein the plasma etching comprises oxygen plasma etching.
In regard to claim 5 Shepard and Xianyu as combined teaches wherein the plasma-etchable layer structure consists of one [see Shepard paragraph 0057 “multilevel stack 200 includes a first two-dimensional layer 202 encapsulated between a second layer 204 and a third layer 206. The second layer 204 and third layer 206 can be insulating layers, The multilevel stack 200 is shown with three layers, but can also include more than three layers. For example, multilevel stacks in accordance with other embodiments of the disclosed subject matter can include five, seven, or nine layers of two-dimensional layers”] or more 2D-material layers.
In regard to claim 6 Shepard and Xianyu as combined teaches wherein the plasma-etchable layer structure consists of one or more graphene layers [see Shepard paragraph 0057 “multilevel stack 200 includes a first two-dimensional layer 202 encapsulated between a second layer 204 and a third layer 206. The second layer 204 and third layer 206 can be insulating layers, The multilevel stack 200 is shown with three layers, but can also include more than three layers. For example, multilevel stacks in accordance with other embodiments of the disclosed subject matter can include five, seven, or nine layers of two-dimensional layers” “first two-dimensional layer 202 can be constructed from graphene. However, in accordance with other embodiments of the disclosed subject matter, the first two-dimensional layer 202 can be construed from other suitable materials including, for example and without limitation, hexagonal boron nitride, transition metal dichalcogenides, molybdenum disulfide, germanane, silicene, and silicon carbide”] and, optionally, one or more layers of silicene, germanene, h-BN, borophene and/or a TMDC.
In regard to claim 7 Shepard and Xianyu as combined teaches wherein the one or more graphene layers [see Shepard paragraph 0064 “second material can be, for example, hexagonal boron nitride” “second material can then be stamped with the stamp to dispose the second material onto the polymer layer, as described below” “material forming the first two-dimensional layer (hereafter the “first material”) can then be stamped with the stamp (at 304). For example, one or more flakes of the first material (e.g., graphene) can be exfoliated or otherwise disposed onto a wafer such as a silicon wafer or a silicon oxide wafer. In accordance with another embodiment of the disclosed subject matter, the first material can be disposed onto a substrate using chemical vapor deposition” “material forming the third layer (hereafter the “third material”) can then be stamped (at 306). For example, the process described above with respect to the first material can be repeated” thus Shepard discloses use of CVD for the multilevel stack 200] and, where present, the one or more layers of silicene, germanene, h-BN, borophene and/or a TMDC, are each formed by CVD or MOCVD.
In regard to claim 9 Shepard and Xianyu as combined teaches [see combination Xianyu “insulating layer 140 may be formed by a method that does not damage the graphene layer 130, for example, evaporation. The evaporation may be electron-beam evaporation” “capping layer 210 may be formed of an insulating material, such as a Si oxide, a Si nitride, or a Si oxynitride, and by using electron-beam evaporation method, for example”] wherein step (ii) comprises patterning a plasma-resistant dielectric by e-beam evaporation.
In regard to claim 14 Shepard and Xianyu as combined teaches wherein:step (v) is performed [see combination Xianyu] after step (iv) and the ohmic contact is formed on [see Shepard] the plasma- resistant substrate; and wherein the coating layer is formed by ALD [see combination Xianyu, “Al oxide, the Hf oxide, and the Zr oxide may be formed by, for example, ALD”, ALD is a standard technique known to give excellent results] across the plasma-resistant substrate to provide the at least one covered region of the layer structure, the ohmic contact, and remaining exposed edge surface with a continuous air-resistant coating.
In regard to claim 16 Shepard and Xianyu as combined wherein:step (v) is performed after [see combination Xianyu] step (iv) and the ohmic contact is formed on [see Shepard] the plasma- resistant substrate; and wherein the coating layer is formed by patterning a coating layer onto the plasma- resistant substrate to provide the [see combination Xianyu, everything is covered and connections are made] at least one covered region of the layer structure and remaining exposed edge surface with a continuous air-resistant coating.
In regard to claim 17 Shepard and Xianyu as combined does not specifically teach wherein [see combination Xianyu “capping layer 210 may be formed of an insulating material, such as a Si oxide, a Si nitride, or a Si oxynitride, and by using electron-beam evaporation method, for example” “insulating layer 140 may be formed by a method that does not damage the graphene layer 130, for example, evaporation. The evaporation may be electron-beam evaporation”] the coating layer is formed by e-beam evaporation.
In regard to claim 18 Shepard and Xianyu as combined teaches wherein:step (v) is performed [see combination Xianyu] before step (iv) and comprises selectively etching away one or more portions of the coating layer to expose corresponding portions [see combination Xianyu see Fig. 6I H1 and H2 are formed to make contact as desired] of the edge surface, and step (iv) comprises forming an ohmic contact [see “With further reference to FIG. 1, a metal can be deposited to form an electrical contact (e.g., metal leads) (at 106). The metal can be deposited using, e.g., electron beam evaporation or thermal evaporation”] in direct contact with each exposed portion of the edge surface.
In regard to claim 19 Shepard and Xianyu as combined wherein the selective etching is performed by [see Shepard paragraph 0072 “stack can be etched using plasma etching. For example, the stack can be etched in an Oxford ICP 80 system using plasma generated from a mixture of O.sub.2 and CHF.sub.3 gases. The flow rates of the O.sub.2 and CHF.sub.3 gases can be about four standard cubic centimeters per minute (sccm) and 40 sccm, respectively. The etch rate of hexagonal boron nitride, which can be used as the second and/or third material in accordance with an exemplary embodiment of the disclosed subject matter, has an etch rate of approximately 30 nm/min under 60 W RF power”, see the use of plasma and RF power, the claim is satisfied under broadest reasonable interpretation] laser etching or reactive ion etching.
Claim(s) 8, 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shepard and Xianyu as combined and further in view of Engel et al. (US 20170108362 A1) hereafter referred to as Engel
In regard to claim 8 Shepard and Xianyu as combined does not specifically teach wherein step (ii) comprises forming: [[(i)]]_alone or more rectangular-shaped regions of the plasma-resistant dielectric and wherein the electronic device precursor is for forming a transistor; or [[(ii)]].(}one or more cross-shaped regions of the plasma-resistant dielectric and wherein the electronic device precursor is for forming a Hall-sensor.
However graphene is known in the art for Hall sensors, see Engel “FIGS. 1A and 1B are schematic representations of side and top views, respectively, of one exemplary embodiment of a graphene-based Hall effect sensor”, see cross shape in Fig. 1B “conductive substantially 2-dimensional lattice structure 130 may be any suitable single-layer or multi-layer organic or inorganic layered material such as graphene, MoS.sub.2, WSe.sub.2, black phosphorous, regular arrays or random networks/thin films made of quasi-one dimensional lattice structures such as organic and inorganic nanotubes/nanowires (e.g. carbon nanotubes, Si nanowires, etc.), combinations of any of the foregoing materials, or the like. However, the substantially 2-dimensional lattice structure 130 is hereinafter referred to as “graphene 130.””.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shepard to include wherein step (ii) comprises forming: [[(i)]]_alone or more rectangular-shaped regions of the plasma-resistant dielectric and wherein the electronic device precursor is for forming a transistor; or [[(ii)]].(}one or more cross-shaped regions of the plasma-resistant dielectric and wherein the electronic device precursor is for forming a Hall-sensor.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to use the graphene device to detect magnetic field.
In regard to claim 10 Shepard and Xianyu as combined does not specifically teach wherein the method comprises forming an array of covered regions, each corresponding to an electronic device precursor.
However this is standard in the art, see Shepard paragraph 0100 “integration with substrates (such as CMOS wafers”, see that a person of ordinary skill in the art knows that CMOS comprises a very large number of transistors.
See Engel “FIGS. 1A and 1B are schematic representations of side and top views, respectively, of one exemplary embodiment of a graphene-based Hall effect sensor”, see cross shape in Fig. 1B “conductive substantially 2-dimensional lattice structure 130 may be any suitable single-layer or multi-layer organic or inorganic layered material such as graphene, MoS.sub.2, WSe.sub.2, black phosphorous, regular arrays or random networks/thin films made of quasi-one dimensional lattice structures such as organic and inorganic nanotubes/nanowires (e.g. carbon nanotubes, Si nanowires, etc.), combinations of any of the foregoing materials, or the like. However, the substantially 2-dimensional lattice structure 130 is hereinafter referred to as “graphene 130.””, see paragraph 0061 “Such array of M equally spaced sensors 100 may improve the signal-to-noise ratio of the cross-correlation calculation involved in the determination of the time-shifts (Δt)” “cross-correlation of time-shifted signals coming from an array of sensors 100 at different positions” .
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shepard to include wherein the method comprises forming an array of covered regions, each corresponding to an electronic device precursor.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is using large number of devices allows processing more information to perform more work.
Claim(s) 15, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shepard and Xianyu as combined and further in view of Bath (CN 104103626 A)
In regard to claim 15 Shepard and Xianyu as combined does not specifically teach wherein the method further comprises wire bonding the ohmic contact of the device precursor through the coating layer.
However wire bonding is a common technique known to a person of ordinary skill in the art, see Bath paragraph 0105 “the metal wire 1351 can be used to couple the tuner to the loudspeaker or music player (e.g., CD player) or the electrical measurement device coupled with RF devices” “In some embodiments, the metal wire 1351 can be used as wire bond chip assembly line”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shepard to include wherein the method further comprises wire bonding the ohmic contact of the device precursor through the coating layer.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation wire bonding is a common technique known to a person of ordinary skill in the art to give excellent results for manking electrical connections to a device.
In regard to claim 20 Shepard and Xianyu as combined does not specifically teach wherein the method further comprises depositing a solder bump on the ohmic contact or wire bonding the ohmic contact.
However this is common in the art, see Bath Fig. 11e see “graphene layer 222” see “in FIG, describing the forming dielectric layer 1143, under bump metallization (UBM) 1145 and bump bonding pad interconnects 1147 after 1100”, wire bonding is a common technique known to a person of ordinary skill in the art, see Bath paragraph 0105 “the metal wire 1351 can be used to couple the tuner to the loudspeaker or music player (e.g., CD player) or the electrical measurement device coupled with RF devices” “In some embodiments, the metal wire 1351 can be used as wire bond chip assembly line”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shepard to include wherein the method further comprises depositing a solder bump on the ohmic contact or wire bonding the ohmic contact.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that solder bumps and wire bonding are a standard way to connect to other circuits and are known to give excellent electrical connections.
Claim(s) 21, 25, 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shepard et al. (US 20160240692 A1) hereafter referred to as Shepard in view of Xianyu (US 20150179814 A1)
In regard to claim 21 Shepard teaches an [see Fig. 6, see paragraph 0056, see Figs. 1-7] electronic device precursor comprising:
a substrate having a layer structure [see Fig. 2 “multilevel stack 200 includes a first two-dimensional layer 202 encapsulated between a second layer 204 and a third layer 206. The second layer 204 and third layer 206 can be insulating layers, The multilevel stack 200 is shown with three layers, but can also include more than three layers” “For example, the first two-dimensional layer can be, for example, graphene. The second and third materials can be, for example, hexagonal boron nitride” ] thereon, the layer structure comprising:
a lower layer [“the first two-dimensional layer can be, for example, graphene”] on a first region of the substrate, wherein the lower layer comprises one or more graphene layers which extend across [see Fig. 6] the lower layer, and an upper layer [“The second and third materials can be, for example, hexagonal boron nitride”] on the lower layer and formed of a dielectric material,
wherein the lower and upper layers share [see Fig. 6] a continuous outer edge surface,
an ohmic contact [“With further reference to FIG. 1, a metal can be deposited to form an electrical contact (e.g., metal leads) (at 106). The metal can be deposited using, e.g., electron beam evaporation or thermal evaporation”] provided on a further region of the substrate and in direct contact with the one or more graphene layers [see Fig. 6] via a portion of the continuous outer edge surface, and
but does not state a continuous air-resistant coating layer enclosing the layer structure thereby protecting all remaining portions of the continuous outer edge surface.
However these are commonly used fabrication steps known to a person of ordinary skill in the art, see Xianyu teaches see Fig. 6A-6J see paragraph 0060 “graphene layer 130” “insulating layer 140 may be, for example, a Si oxide, an Al oxide, an Hf oxide, or the like, but is not limited thereto. The insulating layer 140 may be formed by a method that does not damage the graphene layer 130, for example, evaporation. The evaporation may be electron-beam evaporation”, see Fig. 6E “capping layer 210 may be formed of an insulating material, such as a Si oxide, a Si nitride, or a Si oxynitride, and by using electron-beam evaporation method, for example”, see 120 is on the sides of graphene also, “capping layer 210 may firmly fix the graphene layer 130, the source electrode 120a, and the drain electrode 120b onto the second substrate 200. The capping layer 210 may prevent or inhibit the graphene layer 130 from peeling off from or being separated from the second substrate 200 during the manufacture of the graphene device. The shape of the capping layer 210 illustrated in FIG. 6F is an example, and may vary. For example, the shape of the capping layer 210 may be similar to that of the capping layer CP1' of FIG. 4”, see etching step in 6F, see 210 is a intermediate layer in this step. See “Referring to FIG. 6H, a passivation layer 240 may be formed to cover the gate 230 on the gate insulating layer 220. The passivation layer 240 may be formed of, for example, a Si oxide layer, a Si oxynitride layer, a Si nitride layer, or an organic layer, or may have a stacked structure including at least two layers from among these layers. [0091] Referring to FIG. 61, the passivation layer 240, the gate insulating layer 220, and the capping layer 210 may be partially etched to form first to third contact holes H1 to H3 ”, thus even here the 240 is a intermediate during etching, see “insulating layer 140 may be formed by an evaporation method as described above. The evaporation method may be a physical vapor deposition (PVD) process, and thus, a material of the insulating layer 140 may be deposited on an exposed upper surface of the first substrate 100”, see etch selectivity “sacrificial layer 110 is to be removed by etching in a subsequent process, and may be formed of a material that may be etched faster than the catalyst layer 120 or the graphene layer 130. In other words, the sacrificial layer 110 may be formed of a material having etch selectivity with respect to the other layers 120 to 140 of the stacked structure SS1. For example, the sacrificial layer 110 may be formed of a metallic material, e.g., titanium tungsten (TiW) or molybdenum (Mo), or a dielectric material, e.g., silicon oxide (SiO.sub.2). The sacrificial layer 110 may have a thickness of about several hundreds nm to about several .mu.m”, here also the sacrificial layer 110 is used during etching, see “Al oxide, the Hf oxide, and the Zr oxide may be formed by, for example, ALD”.
See Xianyu see Fig. 6I H1 and H2 are formed to make contacts as desired in the location as desired.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shepard to include a continuous air-resistant coating layer enclosing the layer structure thereby protecting all remaining portions of the continuous outer edge surface.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that enclosing dielectric layers as taught by Xianyu are commonly used protection layers for electrical isolation of electronic device.
In regard to claim 25 Shepard and Xianyu as combined teaches [see Shepard “both the second layer 204 and the third layer 206 can be construed from hexagonal boron nitride”] wherein the lower layer further comprises one or more layers of silicene, germanene, h-BN, borophene and/or a TMDC which extend across the lower layer.
In regard to claim 26 Shepard and Xianyu as combined does not specifically teaches wherein the electronic device precursor is for forming a Hall-sensor, and wherein the charge carrier density of the one or more graphene layers is less than 8x10" cm-2.
However see Shepard teaches Graphene with a range of carrier density was tested, see “FIG. 10 is a graph showing measured contact resistance R.sub.C as a function of carrier density” “FIG. 13A-FIG. 13C are graphs showing metal-graphene edge contact resistance as a function of carrier density of three devices in accordance with the disclosed subject matter”, see Franke teaches Hall sensor using Graphene
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Shepard to include wherein the electronic device precursor is for forming a Hall-sensor
The motivation is to use the graphene device to detect magnetic field.
Shepard and Xianyu as combined does not specifically teach wherein the charge carrier density of the one or more graphene layers is less than 8x10" cm-2, however see that Shepard teaches, see Figs. 10, 13A-13C, that Graphene with a range of carrier density was tested and resistance variation is determined, which will affect sensor output.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “wherein the charge carrier density of the one or more graphene layers is less than 8x10" cm-2 ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
Response to Arguments
Applicant's arguments filed 3/19/26 have been fully considered but they are not persuasive.
On page 8 the Applicant argues “Claim 1 as amended clarifies that the coating layer encloses the layer structure. As such, when the coating layer is deposited, the layer extends onto portions of the substrate surface adjacent the entire edge of the layer structure which is exposed. The insulating layer in Shepard is part of the multilayer stack which is etched in step 504 (see Fig. 5A). Nothing in Shepard teaches forming a coating layer as claimed after such etching”.
The Examiner responds that the claim amendment is addressed in the amended rejection using new secondary reference.
On page 8 the Applicant argues “The Examiner cites Franke in respect of the coating of the electronic device precursor defined in claim 21. However, like Shepard, there is no disclosure in Franke of a coating as claimed enclosing the layer structure. The Examiner refers to Fig. 2 of Franke and the disclosure of a cover layer as being similar to the coating layer. Franke only teaches forming a metallic cover plate 70 on the side of the Hall plate 40 facing away from the substrate layer 32 with one embodiment comprising a cover layer therebetween. As evident in Fig. 2, the cover plate, and by extension any cover layer that may be present to electrically isolate the cover plate, are not taught to enclose the edges of the Hall plate 40. As such, even if Franke were considered by a skilled person, the combination with Shepard would fail to arrive at the claimed electronic device precursor”.
The Examiner responds that see secondary reference the claim amendment of enclosing the graphene is taught by the combination of the new secondary reference Xianyu, any other features which the Applicant says are missing need to be added into the claim language as structural limitations so that the amended rejection can address each new structural limitation.
On page 8, 9 the Applicant argues “Returning to the further difference regarding PVD, the Examiner has failed to appreciate that step (ii) of the claimed method requires patterning of the plasma-resistant dielectric onto the exposed upper surface of the layer structure by physical vapour deposition. That is, the plasma- resistant dielectric is patterned simultaneously with being deposited on the exposed upper surface of the plasma-etchable layer structure (see page 8, lines 34 and 35 of the PCT specification). As discussed on page 11, lines 4-10, the claimed method avoids exposing the 2D-material, and in particular its edge, to lithography chemicals and solvents. These are however required by Shepard in the step to pattern a mask (e.g., the HSQ layer by electron beam lithography) onto the multilayer stack ahead of etching (see paragraph [0080] of Shepard, for example). By the claimed method of patterning by PVD, an improved contact between the ohmic contact and graphene edge can be achieved”.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “the plasma- resistant dielectric is patterned simultaneously with being deposited on the exposed upper surface of the plasma-etchable layer structure” “As discussed on page 11, lines 4-10, the claimed method avoids exposing the 2D-material, and in particular its edge, to lithography chemicals and solvents”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
On page 8, 9 the Applicant argues “The absence of contamination and impurities by directly patterning by PVD provides a robust device with greater performance and reliability, particularly for Hall-sensors due to the greater edge to area ratio than conventional transistors and other devices. Furthermore, Hall- sensors are particularly sensitive to degradation in device performance due to variations in charge carrier density such that the process is particularly advantageous for these products. Advantageously, a lower charge carrier density close to charge neutrality can be achieved which remains stable over time, this being much more important for Hall-sensors than other devices. By minimising the processing steps, the present method produces a consistent product for a Hall- sensor suitable for commercial mass manufacture whereas prior processes result in products of varying quality”.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “absence of contamination and impurities by directly patterning by PVD” ) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
In response to applicant's argument that “an improved contact between the ohmic contact and graphene edge can be achieved” “a lower charge carrier density close to charge neutrality can be achieved”, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
On page 10 the Applicant argues “Shepard is completely silent on the use of PVD (since Shepard teaches a process in which graphene and boron nitride flakes are transferred to a target substrate using organic polymers such as PMMA and organic masks such as HSQ - see paragraph [0100] of Shepard, for example). Barth provides no incentive for the person skilled in the art to modify Shepard given the difference in materials. That is, the dielectric layers that may be deposited in Barth are ceramics such as silicon oxide, silicon carbide, silicon carbonitride or silicon nitride (see paragraph [0041] of Barth). Even if the skilled person were to consider the teachings in Barth for depositing the PMMA or HSQ, firstly, they are taught in paragraph [0041] that the dielectric may be formed by any of a variety of techniques, namely atomic layer deposition (ALD), physical vapour deposition (PVD) or chemical vapour deposition (CVD). There is nothing to suggest to the skilled person that PVD would be beneficial in any way”.
The Examiner responds that see secondary reference PVD and evaporation are common in the art for dielectrics as taught by Xianyu, these dielectrics of Xianyu provide all the claimed novelty that the Applicant says is novel in the instant Application, however they are not novel but instead known and commonly used in the art as taught by Xianyu, thus the instant Application is not novel and thus allowance cannot be made.
On page 10, 11 the Applicant argues “For the avoidance of doubt, ALD is a chemical deposition technique (and is described on page 12, lines 30 to page 13, line 2 of the present PCT specification), as is CVD. ALD may be used in the present invention for depositing the coating layer since ALD provides a conformal coating over the entire substrate. PVD is a deposition technique that may also be used to deposit unpatterned coatings, but crucially is a technique which also allows deposition of the dielectric layer immediately patterned (for example by using a shadow mask). ALD and CVD are not suitable for this purpose. Neither Shepard nor Barth disclose, let alone consider, patterning by PVD a dielectric layer such that the combination of disclosures still fail to teach the claimed method. Indeed, in Barth, the dielectric layer 216 is a first layer coated across the substrate 214. The layer is not patterned, nor is the layer provided over the graphene such that there is no hint of enclosing the graphene”.
The Examiner responds that see secondary reference the claim amendment of enclosing the graphene is taught by the combination of the new secondary reference Xianyu.
In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “a technique which also allows deposition of the dielectric layer immediately patterned (for example by using a shadow mask)” ) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
On page 10, 11 the Applicant argues “Furthermore, none of the cited documents make the differences obvious to the skilled person in order to address the combination of problems associated with prior art methods and devices and arrive at the claimed device precursor having reduced contamination and an improved hermetic coating via the claimed method. This is turn provides long-term stability and improvements in temperature stability over the prior art due to reduced contamination and doping (see page 2, lines 22-29 of the PCT specification)”.
The Examiner responds that see secondary reference the claim amendment of enclosing the graphene (hermetic coating) is taught by the combination of the new secondary reference Xianyu.
In response to applicant's argument that “precursor having reduced contamination and an improved hermetic coating” “long-term stability and improvements in temperature stability”, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
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