Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
The instant application having Application No. 18/269,183 filed on 6/22/2023 is presented for examination.
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Priority
Acknowledgement is made of applicant’s claim for priority based on application JP2020-216116 filed in JAPAN on 12/25/2020.
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Authorization for Internet Communications
The examiner encourages Applicant to submit an authorization to communicate with the examiner via the Internet by making the following statement (from MPEP 502.03):
“Recognizing that Internet communications are not secure, I hereby authorize the USPTO to communicate with the undersigned and practitioners in accordance with 37 CFR 1.33 and 37 CFR 1.34 concerning any subject matter of this application by video conferencing, instant messaging, or electronic mail. I understand that a copy of these communications will be made of record in the application file.”
Please note that the above statement can only be submitted via Central Fax, Regular postal mail, or EFS Web.
Information Disclosure Statement
As required by M.P.E.P. 609, the applicant’s submissions of the Information Disclosure Statement dated 6/22/2023 and 3/25/2025 are acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2 and 4-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Gumimaraju (US 20130160016).
As per claim 1, Gumimaraju discloses a process allocation control device comprising:
at least one memory storing a computer program; and
at least one processor configured to execute the computer program to
receive a request to execute a process that is executable by a plurality of processors having different configurations and has different characteristics of execution performance exhibited by the different processors (Paragraph 38 “Kernel profiler 201 operates to generate and maintain kernel profiles 213. Kernel profiler may include functionality to analyze code, such as OpenCL code, and identify code fragments that can be advantageously scheduled for execution in a CPU or alternatively on a GPU. Kernel profiler 201 can determine characteristics of a kernel being analyzed according to one or more metrics. The characterization of the kernel with regard to the analysis of these one or more characteristics is then recorded as the particular kernel's "signature" or "profile." The initial kernel profiles may be generated at compile-time based upon static characteristics, and may be refined subsequently during system operation based upon dynamically determined characteristics. The assessed characteristics for kernels may include metrics quantifying the ratio of compute operations to memory access operation, degree of nesting and prevalence of conditional branching, prevalence of synchronization operations, memory latency tolerance (both in terms of load-to-use delay within a single thread and the number of threads available to switch to hide memory access delay), and use of specialized instructions, and/or features that are available only on some processors. Additionally, information such as the proximity of the data required by a kernel to respective processors may be part of the characterization of that kernel. Based upon the analysis of the kernels, a kernel profile 213 is generated for each kernel and stored in a memory, such as, one or more of a system memory 103, and processor-specific memory 107.);
detect states of the plurality of processors (Paragraph 39 "Processor profiler 202 operates to generate a signature or profile for processors available for computing in a heterogeneous computing system. The profiles for the processors are referred to herein as "processor profiles" 215. The processors may be characterized based upon metrics quantifying factors such as compute throughput, memory bandwidth, memory access latency, dispatch roundtrip time, CPU to GPU bandwidth, control flow capability, and synchronization throughput. The characterization of processors may be performed at the time of installation and/or at instances when the hardware is reconfigured."); and
allocate execution of the process to at least one of the plurality of processors based on the states of the plurality of processors and the characteristics of the process (Paragraph 43 "Work assigner 206 operates to schedule compute kernels to processors and to adjust the assignment based on performance and/or other criteria. Work assigner 206 can dequeue execution-ready compute kernels from a unified queue 111 and enqueue the compute kernels to respective processor-specific queues 210.”).
As per claim 2, Gumimaraju further discloses wherein the processor is configured to execute the computer program to
allocate the execution of the process in descending order from the processor having highest execution performance of the process (Paragraphs 88-89 show using historical information to select the assignment.).
As per claim 4, Gumimaraju further discloses wherein the processor is configured to execute the computer program to
acquire a number of the processes in execution standby states in each of the plurality of processors (Paragraphs 43-44 show using queues for store the tasks).
As per claim 5, Gumimaraju further discloses wherein the processor is configured to execute the computer program to
receive requests to execute a plurality of the processes having different execution priorities, and
allocate the processor for the process such that the higher an increase of the execution priority of the process causes the execution performance of the process by the processor to increase (Column 3, lines 5-26 shows using a performance database to find the fastest processor to execute the task.).
As per claim 6, Gumimaraju further discloses wherein the processor is configured to execute the computer program to
determine whether a state of the processor allows allocation of the process based on a predetermined criterion in descending order from the processor having highest execution performance of the process, and set the predetermined criterion such that a lowering of the predetermined criterion causes the execution priority of the process to increase (Paragraph 42-43).
As per claim 7, Gumimaraju further discloses further comprising
the plurality of processors (Paragraph 31).
As per claim 8, Gumimaraju further discloses wherein
the plurality of processors are a field programmable gate array (FPGA), a graphics processing unit (GPU), and a central processing unit (CPU) (Paragraph 31).
As per claim 9, it is a method claim having similar limitations as cited in claim 1 and is thus rejected under the same rationale.
As per claim 10, it is a medium claim having similar limitations as cited in claim 1 and is thus rejected under the same rationale.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Gumimaraju in view of Sander (US 2013/0339978)
As per claim 3, Gumimaraju does not expressly disclose but Sander discloses
wherein the processor is configured to execute the computer program to
detect load states of the plurality of processors, and
allocate the execution of the process in ascending order from the processor with lowest load indicated by the load state (Paragraphs 6-8 show load balancing of the work.).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Gumimaraju to include the teachings of Sander because it provides for the purpose of effectively utilizing the resources available in the most efficient manner.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Sarel (US 2014/0052965) discloses dynamic CPU GPU load balancing is described based on power. In one example, an instruction is received and power values are received for a central processing core (CPU) and a graphics processing core (GPU). The CPU or the GPU is selected based on the received power values and the instruction is sent to the selected core for processing.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIMOTHY A MUDRICK whose telephone number is (571)270-3374. The examiner can normally be reached 9am-5pm Central Time.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Pierre Vital can be reached at (571)272-4215. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TIMOTHY A MUDRICK/Primary Examiner, Art Unit 2198 1/08/2026