DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file.
Drawings
The subject matter of this application admits of illustration by a drawing to facilitate understanding of the invention. Applicant is required to furnish a drawing under 37 CFR 1.81(c). No new matter may be introduced in the required drawing. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1–11 are rejected under 35 U.S.C. § 103 as being unpatentable over Nemecek et al. (Universal Integrated Photodetector Platform, Published: 10 December 2018 in the proceedings of MDPI) in view of the general knowledge in the art concerning in-situ trimming of integrated circuits, as exemplified by Wu et al. (“A Multiple Time Programmable On-chip Trimming Technique for CMOS Bandgap Reference Circuits”, 2010 International Conference on Solid State Devices and Materials, Tokyo, 2010, pp. 345-346) and Zhou et al. (“Offset Correction Methods: Laser Trim, e-Trim™, and Chopper”, TI Technote, SBOT037–June 2017).
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Figs of Nemecek: Amplification stage of a transimpedance amplifier (left) 3(b) Active dual slope integration and (right) 4(a) Variable resistive feedback.
Regarding Claims 1, 7 and 9-11, Nemecek teaches an integrated electronic circuit configured as a universal photodetector platform for detecting, amplifying, and digitizing optical signals (Abstract). The circuit disclosed by Nemecek comprises an amplification component implemented as an operational amplifier having at least one input port and one output port, as illustrated in Figures 3(b) and 4(a). The amplification component is characterized by a bias current, supplied by a current source (idc bias), as shown in Figures 3(a) and 4(b).
Nemecek further discloses a resistive feedback component comprising resistors R1 and R2, each having a first terminal electrically coupled to the input port of the operational amplifier via switches T1 and T2, respectively, and a second terminal electrically coupled to the output port of the operational amplifier, as illustrated in Figure 4(a). The effective resistance value between the first and second terminals is selectable as R1, R2, or R1‖R2, depending on the switching state of T1 and T2. Also, per claim 3, the resistive component comprises a plurality of resistive circuit branches, each resistive circuit branch comprising a partial resistive component, a resistive branch switch, and a control circuit controlling the resistive branch switch.
Nemecek additionally teaches a capacitive feedback component comprising capacitors C1 and C2, each having a first terminal electrically coupled to the input port of the operational amplifier via switches T1 and T2, respectively, and a second terminal electrically coupled to the output port of the operational amplifier, as illustrated in Figure 3(b). The effective capacitance value may be C1, C2, C1 + C2, or none, depending on the switching states of T1, T2, and T3. And per claim 4, the capacitive component comprises a plurality of capacitive circuit branches, each capacitive circuit branch comprising a partial capacitive component, a capacitive branch switch, and a control circuit controlling the capacitive branch switch. Again, per claims 5 and 6, Nemecek also teaches that the resistive component and the capacitive component are integrated into a substrate, as part of the 0.18 mm CMOS process (section 3. Summary of Nemecek), made of a semiconductor (silicon) material.
Back to claims 1 and 9, Nemecek discloses a digital adjustment control circuit, implemented using a 4-bit logic-controlled multiplexing scheme (see Figure 1), capable of selectively determining:
the resistance value of the resistive feedback component by controlling switches T1 and T2 (Figure 4(a));
the capacitance value of the capacitive feedback component by controlling switches T1, T2, and T3 (Figure 3(b)); and
the bias current value of the amplification component via resistive elements R2 and R3, as illustrated in Figure 4(b).
Nemecek further teaches that the digital adjustment control includes a detection component for identifying when the output signal of the amplification component reaches a limit value (Section 1, “Chip Concept,” lines 4–9). A calculation unit, operatively coupled to the detection component (Section 1, lines 11–15), is configured to adjust the resistance and capacitance values of the feedback network upon detection of the output limit condition, thereby modifying a characteristic of the amplification component (Section 1, lines 9–10).
The digital adjustment command is communicated via a communication bus connecting the calculation unit to control circuits governing the resistive and capacitive branch switches (Section 1, lines 4–9; page 2, lines 1–5). Nemecek further discloses selectable gain settings implemented through multiplexed analog drivers and control logic.
Nemecek discloses that the integrated electronic circuit includes at least one input terminal (the inverting input of the operational amplifier) connected to a photonic sensor supplying an input current (iphoto). The photonic sensor comprises at least one photodiode (PD), as illustrated in Figures 3(b) and 4(a).
Obviousness of Parallel Feedback Configuration
While Nemecek presents separate embodiments illustrating variable resistive feedback and variable capacitive feedback, it would have been obvious to a person of ordinary skill in the art to employ both variable resistive and variable capacitive elements in parallel within a single feedback path. Such an arrangement would predictably provide enhanced flexibility in gain control, bandwidth shaping, and signal integration, thereby offering increased degrees of freedom in controlling amplifier behavior within an integrated circuit.
In-Situ Adjustment and Trimming
Although Nemecek does not explicitly describe in-situ trimming of bias current, resistance, and capacitance values without physical modification of the integrated circuit, such techniques were well known and routinely employed in the art at the time of the invention. In-situ trimming of CMOS integrated circuits—using laser trimming, one-time programmable (OTP), or multi-time programmable (MTP) elements—is a standard design-level practice intended to reduce fabrication cost, improve yield, and minimize the need for multiple fabrication iterations, as taught by Wu and Zhou.
Accordingly, it would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to apply in-situ trimming techniques to the transimpedance amplifier disclosed by Nemecek to provide adjustable gain, bandwidth stabilization, and saturation avoidance in an integrated optical receiver. Such modifications represent the combination of known techniques for predictable purposes, and therefore satisfy the obviousness standard articulated in KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Claims 9–11 recite method steps corresponding to detecting an output condition and adjusting circuit parameters, including bias current, resistance, and capacitance. Because the cited prior art discloses apparatuses that inherently perform these steps during normal operation, the method claims are unpatentable under In re Schreiber, 128 F.3d 1473 (Fed. Cir. 1997).
Finally, per claim 8, the conversion device (analog amplified photonic current into a digital signal) comprises a digitization component and wherein the output port of the amplification component is electrically connected to the digitization component (Fig. 1), a 10-bit dual-slope analog-to-digital converter (ADC).
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Fig. 3(f) of Noshahr: Amplification stages in cascade.
Claims 1–11 are rejected under 35 U.S.C. § 103 as being unpatentable over Nemecek, Wu and Zhou and further in view of Noshahr et al. (“Multi-Channel Neural Recording Implants: A Review”, Sensors 2020, 20, 904; www.mdpi.com/journal/sensors
Regarding claim 2, the resultant combination although doesn’t show explicitly multiple op-Amps are connected in cascade to boost the gain, it is well known in the art that plurality of stages of op-Amps are connected in cascade for increasing the gain of the amplifier as illustrated in Fig. 3(f) of a similar art Noshahr et al. as the amplification component comprises a plurality of differential operational amplifiers connected in cascade one after another.
It would have been obvious to a person of ordinary skill in the art, prior to the effective filing date of the claimed invention, to adopt a multistage transimpedance amplifiers in cascade like Noshahr to provide extra gain as well as extra control of gain and integration.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
/HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843.
Prosecution Insights