DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after 2013/03/16, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CZPV2020-731, filed on 2020/12/30.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 2023/06/29 was filed before the mailing date of 2024/06/13. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because:
the lines and strokes throughout the figures are not clean, sharp, and solid, as required by 37 CFR 1.84(l). The figures appear to have been reproduced at insufficient resolution, rendering reference characters, label text, and structural lines throughout the drawing sheets indistinct and difficult to discern with clarity.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: a title that reflects the inventive concept of this particular Battery Storage Management (BMS) Method and Apparatus, that separates it from other BMS methods and apparatuses.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
Claim(s) 1 – 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over ONNERUD et al. (US 2010/0121511 A1), further in view of POSAMENTIER et al. (US 2012/0194133 A1) and JARVINEN (US 2009/0218986 A1).
In re claim 1, ONNERUD discloses a circuit for battery storage management (array 114) including at least one battery storage having at least two cells (storage cells within each module 115) connected in at least one bank (battery modules 115), at least one main power supply bus (AC charging bus 125) and at least one communication bus (SMBD, SMBC lines 112, 113), where
the at least one bank includes at least one device for controlling the bank (FIG. 3; ¶[0036]: module management electronics (OVP 302, AFE 304, microcontroller 306));
within the at least one bank, the cells are interconnected through the main power supply bus (FIG. 3: storage cells 301 connected in series) and are also interconnected via the main power supply bus with the device (¶[0038], ¶[0040]: OVP 302 connected to storage cells 301 via VC1–VC5 terminals; AFE 304 draws power from storage cells 301);
each device includes a control unit for balancing the cells in the respective bank (¶[0028]: cell balancing function) and memory storage blocks for storing values regarding the history of each cell in the bank (¶[0013]);
ONNERUD is silent to
at least one of the two cells in each bank is equipped with at least one cell management device, wherein said cell management device includes at least one measurement device for measuring the cell status indicator;
inside each bank, there is at least one processor board having at least one cell management device, and the processor boards are interconnected via a communication bus; the communication bus also connects the processor boards to the device; and
characterized in that the circuit includes an independent power source outside the battery storage and an auxiliary power supply bus, the power supply bus being powered from said independent power source and connecting each device to the cell management devices contained in the respective bank.
POSAMENTIER discloses
at least one of the two cells in each bank is equipped with at least one cell management device (¶[0011]: power cells 102a – 102d coupled to active balancing circuit 104a – 104d), wherein said cell management device includes at least one measurement device (differential amplifier 212, temperature sensor 216) for measuring the cell status indicator (¶[0024 – 0025]);
A person having ordinary skill in the art (PHOSITA) would be motivated to incorporate POSAMENTIER's per-cell active balancing circuit topology into ONNERUD's battery array framework, to achieve single-cell balancing granularity that scales to any suitable number of power cells and any suitable balancing current requirement.
POSAMENTIER is silent to
inside each bank, there is at least one processor board having at least one cell management device, and the processor boards are interconnected via a communication bus; the communication bus also connects the processor boards to the device; and
characterized in that the circuit includes an independent power source outside the battery storage and an auxiliary power supply bus, the power supply bus being powered from said independent power source and connecting each device to the cell management devices contained in the respective bank.
JARVINEN discloses
inside each bank, there is at least one processor board (¶[0041]: circuit boards) having at least one cell management device (NODE), and the processor boards are interconnected via a communication bus (BUS); the communication bus also connects the processor boards to the device (CPU, ¶[0022]); and
characterized in that the circuit includes an independent power source (PS) outside the battery storage and an auxiliary power supply bus, the power supply bus (LPS) being powered from said independent power source and connecting each device to the cell management devices contained in the respective bank (¶[0022], ¶[0025]).
It would have been obvious for a PHOSITA to incorporate JARVINEN's per-cell circuit board architecture and separate auxiliary power supply bus into ONNERUD's battery array framework, to ensure that the operation of the cell management and measurement electronics is not dependent on the actual charge status of a cell connected to a relevant management device, and does not break up as a result of a blown fuse or a slump in terminal voltage of the battery.
In re claim 2, ONNERUD discloses wherein:
each device for controlling the bank includes a memory block for storing values regarding the history of the bank and at least one of a temperature measurement device and a current measurement device (¶[0013], ¶[0015]);
all banks containing the device for controlling the bank are interconnected through the main power supply bus (FIG. 1 – 2; ¶[0027]);
the devices for controlling the individual banks are interconnected through the communication bus (FIG. 1 – 2; ¶[0031]); and
the communication bus, the main power supply bus are connected to a central battery storage management device (¶[0031], ¶[0033]: controller 110 connected to SMBD, SMBC lines 112, 113; controls switches 118, 130, 131, connecting the battery modules).
ONNERUD is silent to the auxiliary power supply bus is connected to a central battery storage management device.
JARVINEN discloses
the auxiliary power supply bus is connected to a central battery storage management device (¶[0022], ¶[0025]: LPS powers CPU)
It would have been obvious for a PHOSITA to incorporate JARVINEN's separate auxiliary power supply bus into ONNERUD's battery array framework, to ensure that the operation of the cell management and measurement electronics does not break up as a result of a blown fuse or a slump in terminal voltage of the battery.
In re claim 3, ONNERUD is silent to the measuring device for measuring the cell status indicator is selected from a group comprising voltage measurement device, current measurement device, resistance measurement device and temperature measurement device.
POSAMENTIER discloses the measuring device for measuring the cell status indicator (active balancing circuit 104) is selected from a group comprising voltage measurement device (differential amplifier 212), current measurement device (open wire sense unit 222), resistance measurement device (thermistor 220) and temperature measurement device (temperature sensor 216).
It would have been obvious for a PHOSITA to incorporate POSAMENTIER's sensing circuitry into ONNERUD's battery array framework to equip each cell's management circuit with local intelligence and sensing capability for controlling charge and discharge functionality at the individual cell level.
In re claim 4, ONNERUD is silent to a method for battery storage management in the circuit according to claim 1, characterized by that it includes the following steps:
measuring at least one cell status indicator of the cell, where the cell status indicator is selected from a group comprising temperature, current, voltage and resistance, and storing the time course of this indicator's values in memory of the history of the cell;
predicting status of the cells on the basis of the time course established in step a);
recharging the cell or of the cells for which a failure is predicted during step b), through the auxiliary power supply bus powered from an independent power source outside the battery storage.
JARVINEN discloses a method for battery storage management in the circuit (¶[0001]), characterized by that it includes the following steps:
measuring at least one cell status indicator of the cell (voltmeter V, thermometer T), where the cell status indicator is selected from a group comprising temperature, current, voltage and resistance, and storing the time course of this indicator's values in memory of the history of the cell (¶[0011 – 0012], ¶[0022]);
predicting status of the cells on the basis of the time course established in step a) (¶[0007], ¶[0009 – 0010]);
recharging the cell or of the cells for which a failure is predicted during step b) (¶[0009], ¶[0023]: charger S charges individual cell linked with NODE based on predictive anticipation logic), through the auxiliary power supply bus powered from an independent power source outside the battery storage (¶[0022]: charger S acquires current directly from power supply PS).
It would have been obvious for a PHOSITA to incorporate JARVINEN's per-cell circuit board architecture and separate auxiliary power supply bus into ONNERUD's battery array framework, to ensure that the operation of the cell management and measurement electronics is not dependent on the actual charge status of a cell connected to a relevant management device, and does not break up as a result of a blown fuse or a slump in terminal voltage of the battery.
In re claim 5, ONNERUD discloses a method according to claim 4, characterized by that it further includes the following steps:
measuring the temperature and/or current at the input of each battery bank (¶[0015]) and storing the time course of at least one of these quantities in memory of the history of the bank (¶[0012 – 0013]);
disconnecting the bank or the banks for which at least one of the parameters measured in step d) shows failure and/or disconnecting this bank or the banks for which at least one of the parameters measured in step a) for at least one of the cells contained in said bank indicates a failure of said cell (¶[0032]).
In re claim 6, ONNERUD is silent to a method, wherein if at least one of the parameters measured in step a) indicates a failure of any of the cells, this cell is disconnected and replaced and at least one cell in the bank in which a cell was replaced is recharged through the auxiliary power supply bus.
JARVINEN discloses a method, wherein if at least one of the parameters measured in step a) indicates a failure of any of the cells, this cell is disconnected and replaced (¶[0029]) and at least one cell in the bank in which a cell was replaced is recharged through the auxiliary power supply bus (¶[0022 – 0023]: charger S acquires current from PS, charges cell linked with NODE 1-3).
It would have been obvious for a PHOSITA to incorporate JARVINEN's per-cell circuit board architecture and separate auxiliary power supply bus into ONNERUD's battery array framework, to ensure that the operation of the cell management and measurement electronics is not dependent on the actual charge status of a cell connected to a relevant management device, and does not break up as a result of a blown fuse or a slump in terminal voltage of the battery.
In re claim 7, ONNERUD is silent to a method, characterized in that at least one measurement device for measuring the cell status indicator and/or at least one cell management device is powered through the auxiliary power supply bus.
JARVINEN discloses a method, characterized in that at least one measurement device for measuring the cell status indicator and/or at least one cell management device is powered through the auxiliary power supply bus (¶[0025]: "The voltage source for all microprocessors and logical functions comprises a separate, secured power source").
It would have been obvious for a PHOSITA to incorporate JARVINEN's per-cell circuit board architecture and separate auxiliary power supply bus into ONNERUD's battery array framework, to ensure that the operation of the cell management and measurement electronics is not dependent on the actual charge status of a cell connected to a relevant management device, and does not break up as a result of a blown fuse or a slump in terminal voltage of the battery.
In re claims 8 – 9, ONNERUD discloses a method characterized by that the measurement in step a) and d) is performed continuously (¶[0045]: "The continuous sampling of the multiple storage cells 301 may allow the electronic circuitry to monitor or calculate characteristics of the battery module 115, such as SOH, SOC, temperature, charge, or the like").
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHANN DJANAL-MANN whose telephone number is (571)272-4697. The examiner can normally be reached Monday - Friday 8:00 - 17:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Drew Dunn can be reached at (571) 272-2312. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/D. JOHANN DJANAL-MANN/Examiner, Art Unit 2859
/DREW A DUNN/Supervisory Patent Examiner, Art Unit 2859
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