DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/10/25 has been entered.
Claims 1-3, 5-15,17-21 are pending.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-3,5-9, 20, and 21 ire rejected under 35 U.S.C. 103 as being unpatentable over Nilsson et al (US6189052) hereinafter Nilsson in view of Hundertmark et al (US5627840) hereinafter Hundertmark.
As to claim 1, Nilsson discloses an I/O circuit block (Fig.1) comprising: a register unit (Fig.1, and FIFO, 11); an input/output unit connected to a plurality of terminals (Fig.1 with element 6 comprising I/Os); an instruction memory (Fig.1, and RAM, 3); and a state machine configured to execute a program stored in the instruction memory to transfer
data between the register unit and the input/output unit (Fig.1, and element 12, and COL. 12, lines 5-20) .
wherein instructions executed by the state machine include an operation to set a value to at least one of the plurality of terminals concurrently with execution of another operation defined by the instruction (Fig. 9 where the data from the fifo comprises instruction that is transferred to busses, COL. 10, lines 1-43).
Nilsson does not teach a plurality of state machines. However, Hundertmark in Fig. 2 and COL. 8, lines 8 – 15 teaches a plurality of state machines. One of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to use the capabilities of Hundertmark in the system of Nilsson to achieve a robust and efficient test capability, (COL. 2, lines 47 – 57).
As to claim 2, Nilsson discloses an I/O circuit block (Such as Fig.1, element 15) wherein the state machine is configured to execute instructions of an instruction set, the instruction set including: an IN instruction to transfer a specified number of bits into the register unit 9, Fig.7, with input 31); and an OUT instruction to transfer a specified number of bits from the register unit (Fig.8, and set pin).
As to claim 3, Nilsson discloses an I/O circuit block wherein the instruction set consists of: the IN instruction; the OUT instruction; a JMP instruction (COL. 7, line 46 — COL. 7, line 12); a WAIT instruction (Table 3); a PUSH instruction (Table 3); a PULL instruction (Table 3); a MOV instruction (Table 3); an IRQ instruction (Table 3); and a SET instruction (Table 3), (COL. 10, lines 9-50).
As to claim 5, Nilsson discloses an I/O circuit block wherein the register unit comprises an input FIFO register and an output FIFO register, the input FIFO register and the
output FIFO register being configurable as a single, double length FIFO register for input or output (Fig. 1, with fifo 11, COL. 10, lines 1-50).
As to claim 6, Nilsson discloses an I/O circuit block wherein the state machine comprises an input shift register and an output shift register (Fig.1 , FIFO 11 providing said function) and is operable in an auto pull mode wherein a first predetermined number of bits are transferred from the register unit to the output shift register (Table 3 shares the operations) when the content of the output shift register is less than a first threshold and/or in an auto push mode wherein a second predetermined number of bits are transferred to the register unit from the input shift register when the content of the input shift register is greater than a second threshold (Fig.3, where register bank 19 is operated by commands, under different timing, COL.6, line 46 — COL. 7, line 12).
As to claim 7, Nilsson discloses an I/O circuit block wherein the state machine is configured to also execute instructions from one or more of: the register unit, a shift register within the state machine and a configuration register within the state machine (COL. 13, lines 1-20).
As to claim 8, Nilsson discloses an I/O circuit block wherein the state machine comprises a wrap control field specifying a sequence of instructions which are executed repeatedly (Fig.3, and COL. 6, lines 60 — 67).
As to claim 9, Nilsson discloses an I/O circuit wherein the state machine comprises a configurable clock divider to enable the state machine to operate at a lower clock rate than an external clock (Fig. 11, COL. 11, lines 47-62).
As to claims 20, and 21 Nilsson discloses an assembler fora state machine having an instruction set consisting of: an IN instruction (Table 7 modes); an OUT instruction (Table 7 modes); a JMP instruction (Table 7 modes); a WAIT instruction (Table 7 modes); a PUSH instruction (Table 7 modes); a PULL instruction (Table 7 modes); a MOV instruction (Table 7 modes); an IRQ instruction (table 7 modes); and a SET instruction (COL. 10, lines 9-50). wherein instructions executed by the state machine include an operation to set a value to at least one of the plurality of terminals concurrently with execution of another operation defined by the instruction (Fig. 9 where the data from the fifo comprises instruction that is transferred to busses, and where multiple transfers constitute multiple instructions COL. 10, lines 1-43).
Claims 10, 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Nilsson in view of Vangal et al (US20040125751) hereinafter Vangal.
As to claim 10, Nilsson does not discloses having a plurality of state machines and a corresponding plurality of register units.
Vangal teaches in Fig.3, having a plurality of state machines and a corresponding plurality of register units (para. 0037).One of ordinary skill in the art before the effective filing date of the claimed invention would have scalable options to adjust for upgrades, (para. 0025)
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Nilsson/Vangal in view of Leyrer et al (US20190370068) hereinafter Leyrer.
As to claim 11, Nilsson/Vangal does not disclose explicitly wherein the instruction memory is shared between the plurality of state machines and configured for multiple simultaneous reads.
Leyrer teaches in Fig. 3a explicitly wherein the instruction memory is shared between the plurality of state machines and configured for multiple simultaneous reads (para. 0101).One of ordinary skill in the art before the effective date of the claimed invention would have used to shared memory module of Leyrer in the system of Nilsson/Vangal to enable parallel processing, (para. 0004).
As to claim 12, Nilsson discloses an I/O circuit block wherein the input/output unit comprises a multiplexer configured to enable each of the state machines to be connected to any of the terminals (Fig.1 with config. Logic 5, COL2, line 64 — COL. 3, line 23).
As to claim 13, Nilsson discloses an I/O circuit block further comprising a plurality of IRQ flags and wherein each of the state machines can set and read each of the IRQ flags (COL. 9, lines 50 — 67 with table 7 illustrating said).
As to claim 14, Nilsson discloses an integrated circuit comprising at least one I/O circuit block (Fig.1 with on chip 2, and I/O pins 6).
Claims 15 - 19 are rejected under 35 U.S.C. 103 as being unpatentable over Nilsson/Vangal in view of Sengoku (US20160147684).
As to claim 15, Nilsson/Vangal does not disclose an integrated circuit further comprising a plurality of clock sources and wherein the integrated circuit is operable in a DORMANT mode wherein all the clock sources are halted.
Sengoku teaches in Fig. 17 , an integrated circuit further comprising a plurality of clock sources and wherein the integrated circuit is operable ina DORMANT mode wherein all the clock sources are halted, (para. 0107). One of ordinary art before the effective filing date of the claimed invention would have been motivated to use to scheme of Sengoku
in the system of Nilsson/Vangal/leyrer to manage multi-controller and power modes (para. 0004).
As to claim 17, Nilsson discloses an integrated circuit further comprising a plurality of peripheral registers and wherein the peripheral registers are addressable bitwise in at least one of the following modes:- atomic XOR on write - atomic bitmask set on write - atomic bitmask clear on write (COL. 9, lines 1-15).
As to claim 18, Nilsson disclose an integrated circuit wherein the peripheral register comprises a read/write accessible register and a bus interposer which translates upstream atomic writes into downstream read-modify-write sequences (Fig. 1 with fifo 11, and register 4 engagements, para. 0059).
As to claim 19, Nilsson discloses an integrated circuit further comprising at least one general purpose CPU (Fig. 1, and CPU , core, COL. 6, lines 1-30).
Conclusion
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/C.A.D/Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184