DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I in the reply filed on 10 July 2026 is acknowledged. Because applicants did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-6 and 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Itoga (WO 2021065512, for English translations purposes PG Pub 20220223782) and in view of Yamamoto (PG Pub 20180097502).
Considering claim 1, Itoga (Figure 5) teaches a piezoelectric device, comprising: a substrate (100 + paragraph 0026); a bottom electrode layer (101 + paragraph 0027) disposed on the substrate; a piezoelectric functional layer (102 + paragraph 0027) disposed on the bottom electrode layer; a top electrode layer (103 + paragraph 0027) disposed on the piezoelectric functional layer; an insulation layer (104 + paragraph 0030), wherein the insulation layer is arranged to cover an edge portion of the top electrode layer, and cover the piezoelectric functional layer exposed from the top electrode layer and the bottom electrode layer exposed from the piezoelectric functional layer (paragraph 0030), an edge of the insulation layer has a slope angle (see Figure 5), a wiring layer (105 + paragraph 0030) disposed on the insulation layer, wherein the wiring layer at least partially covers the top electrode layer (103 + paragraph 0027) exposed from the insulation layer (104 + paragraph 0030), and the wiring layer covers the edge of the insulation layer in an overlapping are of the wiring layer and the insulation layer (see Figure 5).
However, Itoga does not teach the slope angle is less than 60 degrees.
Yamamoto (Figure 4B) teaches the slope angle is less than 60 degrees (12b + C2 + paragraph 0065).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to include the slope angle is less than 60 degrees into Itoga’s device for the benefit of reducing the damage to a wiring electrode and other structures elements.
Considering claim 2, Yamamoto (Figure 4B) teaches wherein the slope angle is greater than 30 degrees (12b + C2 + paragraph 0065).
Considering claim 3, Itoga (Figure 5) teaches wherein, in a direction perpendicular to the substrate, a thickness of the insulation layer (104 + paragraph 0030) is greater than a thickness of the piezoelectric functional layer (see Figure 5).
Considering claim 4, Itoga teaches a signal terminal (60 + paragraph 0025) portion disposed on the substrate, wherein the signal terminal portion is arranged in the same layer as the bottom electrode layer, the insulation layer partially covers the signal termination portion, and the wiring layer partially covers the signal terminal portion (paragraph 0025).
Considering claim 5, Itoga discloses the claimed invention except for wherein a material of the insulation layer is a negative photoresist. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the insulation layer is a negative photoresist, since it has been held to be within the generally skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice.
Considering claim 6, Itoga (Figure 4) teaches wherein the piezoelectric functional layer comprises a plurality of discrete piezoelectric functional blocks (paragraph 0043 + see Figure 4).
Considering claim 12, Itoga (Figure 5) teaches a panel comprising a piezoelectric device wherein the piezoelectric device comprises: a substrate (100 + paragraph 0026); a bottom electrode layer (101 + paragraph 0027) disposed on the substrate; a piezoelectric functional layer (102 + paragraph 0027) disposed on the bottom electrode layer; a top electrode layer (103 + paragraph 0027) disposed on the piezoelectric functional layer; an insulation layer (104 + paragraph 0030), wherein the insulation layer is arranged to cover an edge portion of the top electrode layer, and cover the piezoelectric functional layer exposed from the top electrode layer and the bottom electrode layer exposed from the piezoelectric functional layer (paragraph 0030), an edge of the insulation layer has a slope angle (see Figure 5), a wiring layer (105 + paragraph 0030) disposed on the insulation layer, wherein the wiring layer at least partially covers the top electrode layer (103 + paragraph 0027) exposed from the insulation layer (104 + paragraph 0030), and the wiring layer covers the edge of the insulation layer in an overlapping are of the wiring layer and the insulation layer (see Figure 5).
However, Itoga does not teach the slope angle is less than 60 degrees.
Yamamoto (Figure 4B) teaches the slope angle is less than 60 degrees (12b + C2 + paragraph 0065).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to include the slope angle is less than 60 degrees into Itoga’s device for the benefit of reducing the damage to a wiring electrode and other structures elements.
Considering claim 13, Itoga teaches a tactile reproduction apparatus comprising the panel (paragraphs 0023-0026).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRYAN P GORDON whose telephone number is (571)272-5394. The examiner can normally be reached M-F 8 a.m. - 4:30 p.m..
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dedei K Hammond can be reached at 571-270-7938. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BRYAN P GORDON/Primary Examiner, Art Unit 2837
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